Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23492

1

T1

14

T2

18

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3644

1

T1

7

T2

23

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20910

1

T1

21

T2

30

T3

162

auto[1]

6226

1

T2

11

T4

25

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	291	1			T154	5		T130	1		T225	18
values[0]	28	1			T260	23		T262	5		-	-
values[1]	803	1			T7	34		T35	9		T48	37
values[2]	606	1			T1	14		T2	18		T47	10
values[3]	774	1			T2	11		T4	19		T10	1
values[4]	520	1			T43	15		T47	26		T137	14
values[5]	709	1			T2	12		T127	20		T154	12
values[6]	795	1			T1	7		T48	20		T29	20
values[7]	840	1			T4	25		T27	23		T30	1
values[8]	928	1			T29	21		T135	7		T124	2
values[9]	3235	1			T3	1		T4	25		T5	8
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	702	1			T2	18		T7	34		T47	10
values[1]	760	1			T1	14		T49	33		T127	12
values[2]	548	1			T2	11		T4	19		T10	1
values[3]	734	1			T43	15		T47	26		T127	20
values[4]	666	1			T1	7		T2	12		T154	12
values[5]	800	1			T48	20		T30	1		T56	8
values[6]	3034	1			T4	25		T5	8		T6	2
values[7]	961	1			T29	21		T135	7		T124	1
values[8]	850	1			T4	25		T8	25		T10	1
values[9]	211	1			T3	1		T123	1		T140	2
minimum	17870	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	18		T47	1		T48	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	14		T172	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	14		T49	5		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	10		T127	12		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	1		T13	3		T126	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	11		T4	4		T49	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T43	5		T47	14		T199	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T127	20		T188	11		T143	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	9		T29	10		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	7		T2	12		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	5		T56	4		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	1		T147	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T5	1		T6	2		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	14		T124	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T29	13		T135	7		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T124	1		T129	5		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T4	12		T8	6		T43	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	9		T10	1		T154	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T123	1		T140	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T3	1		T86	9		T258	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17606	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T35	7		T79	1		T82	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T47	9		T48	14		T29	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	20		T198	15		T141	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	5		T13	2		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T49	13		T37	1		T231	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	1		T126	8		T226	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	15		T49	11		T126	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T43	10		T47	12		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T188	10		T214	16		T206	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	10		T122	3		T132	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T56	9		T128	3		T216	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	15		T56	4		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T147	10		T14	2		T224	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T5	7		T11	7		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	11		T125	18		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	8		T197	15		T156	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T205	12		T188	10		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	13		T8	1		T43	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	9		T51	3		T126	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T140	1		T206	4		T81	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T86	7		T258	4		T261	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	2		T37	1		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T35	2		T82	1		T201	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T130	1		T139	6		T206	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T154	5		T225	8		T224	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T260	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T262	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T48	23		T29	9		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	14		T35	7		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	14		T2	18		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T49	22		T127	12		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	1		T13	3		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	11		T4	4		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	5		T47	14		T226	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T137	14		T206	1		T175	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T154	9		T122	1		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	12		T127	20		T154	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	5		T29	10		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	7		T147	1		T15	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T27	12		T172	1		T56	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	14		T30	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T29	13		T135	7		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T124	2		T129	5		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T4	12		T5	1		T6	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	1		T8	9		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T206	4		T81	12		T223	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T225	10		T224	8		T240	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T260	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	14		T29	7		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	20		T35	2		T198	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	9		T49	5		T13	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T49	24		T37	1		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T126	8		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	15		T126	8		T231	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	10		T47	12		T226	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T206	3		T175	7		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T122	3		T132	2		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T56	9		T128	3		T188	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	15		T29	10		T32	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T147	10		T15	14		T224	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	11		T56	4		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T4	11		T125	18		T131	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	8		T131	3		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T205	12		T175	12		T226	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T4	13		T5	7		T8	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	9		T51	3		T126	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	1		T47	10		T48	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	21		T172	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T49	6		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	14		T127	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T13	3		T126	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T4	16		T49	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T43	11		T47	13		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T127	1		T188	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T154	1		T29	11		T122	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	1		T2	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	16		T56	5		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T30	1		T147	11		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T5	8		T6	2		T11	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T4	12		T124	1		T125	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T29	9		T135	1		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T124	1		T129	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	14		T8	5		T43	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	12		T10	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T123	1		T140	2		T206	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T3	1		T86	8		T258	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17700	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T35	6		T79	1		T82	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	17		T48	22		T29	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	13		T132	12		T224	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	13		T49	4		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T49	9		T127	11		T231	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	1		T126	1		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T2	10		T4	3		T49	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T43	4		T47	13		T199	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T127	19		T188	10		T143	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T154	8		T29	9		T132	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	6		T2	11		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	4		T56	3		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	1		T224	4		T84	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T24	30		T25	34		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	13		T214	7		T204	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T29	12		T135	6		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T129	4		T205	9		T188	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	11		T8	2		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	6		T154	4		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T81	14		T223	10		T180	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T86	8		T258	14		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T138	12		T286	10		T251	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T35	3		T201	11		T268	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T130	1		T139	1		T206	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T154	1		T225	11		T224	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T260	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T262	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	15		T29	8		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	21		T35	6		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T2	1		T47	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	26		T127	1		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	1		T13	3		T126	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	1		T4	16		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T43	11		T47	13		T226	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T137	1		T206	4		T175	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T154	1		T122	4		T132	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	1		T127	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	16		T29	11		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	1		T147	11		T15	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T27	12		T172	1		T56	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T4	12		T30	1		T125	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T29	9		T135	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T124	2		T129	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T4	14		T5	8		T6	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	1		T8	12		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T139	5		T81	14		T223	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T154	4		T225	7		T224	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T260	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	22		T29	8		T138	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	13		T35	3		T132	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	13		T2	17		T49	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T49	20		T127	11		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T126	1		T39	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	10		T4	3		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T43	4		T47	13		T226	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T137	13		T175	8		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	8		T132	10		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	11		T127	19		T154	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	4		T29	9		T216	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	6		T15	15		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T27	11		T56	3		T139	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	13		T214	7		T204	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T29	12		T135	6		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T129	4		T205	9		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T4	11		T8	2		T43	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	6		T51	2		T126	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27