Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23115

1

T1

7

T2

11

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

4021

1

T1

14

T2

30

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20918

1

T1

21

T2

11

T3

162

auto[1]

6218

1

T2

30

T4

44

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T10	1		T174	11		T137	14
values[0]	38	1			T157	15		T213	17		T211	6
values[1]	806	1			T13	4		T29	21		T122	4
values[2]	937	1			T29	20		T128	8		T129	5
values[3]	776	1			T1	14		T3	1		T47	10
values[4]	690	1			T8	7		T35	9		T49	10
values[5]	855	1			T2	18		T48	37		T49	23
values[6]	636	1			T8	18		T43	20		T47	26
values[7]	666	1			T1	7		T2	12		T7	34
values[8]	2924	1			T2	11		T4	19		T5	8
values[9]	972	1			T4	50		T127	20		T13	4
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T13	4		T122	4		T51	25
values[1]	948	1			T3	1		T47	10		T29	36
values[2]	841	1			T1	14		T8	7		T35	9
values[3]	658	1			T49	10		T154	9		T124	1
values[4]	790	1			T2	18		T47	26		T48	37
values[5]	688	1			T1	7		T2	12		T8	18
values[6]	2953	1			T4	19		T5	8		T6	2
values[7]	647	1			T2	11		T10	1		T48	20
values[8]	843	1			T4	50		T127	20		T37	6
values[9]	153	1			T10	1		T181	1		T200	12
minimum	17872	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	3		T51	12		T143	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T122	1		T51	3		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T141	1		T138	13		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	1		T47	1		T29	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	6		T172	3		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	14		T35	7		T199	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T154	9		T126	15		T204	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	5		T124	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T48	23		T154	3		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	18		T47	14		T49	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	7		T8	9		T43	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	12		T123	1		T39	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T4	4		T5	1		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T43	5		T56	8		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	11		T10	1		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	2		T130	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T124	1		T51	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T4	26		T127	20		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T181	1		T200	12		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T10	1		T201	12		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17542	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T29	13		T175	12		T80	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	1		T51	7		T145	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T122	3		T51	3		T206	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T141	12		T138	11		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T47	9		T29	17		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T202	10		T81	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T35	2		T196	26		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T126	8		T204	2		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	5		T140	1		T149	41
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T48	14		T56	4		T125	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	12		T49	24		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	9		T43	6		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T39	9		T40	1		T188	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T4	15		T5	7		T7	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	10		T56	9		T126	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	15		T175	7		T224	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	2		T207	3		T18	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T141	10		T132	2		T206	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	24		T37	1		T133	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T196	4		T20	9		T208	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T201	8		T293	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	2		T37	1		T198	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T29	8		T175	12		T80	21

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T174	11		T196	1		T20	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T10	1		T137	14		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T211	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T157	7		T213	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	3		T198	1		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T29	13		T122	1		T51	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	12		T141	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T29	10		T128	5		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T172	3		T38	2		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	14		T3	1		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	6		T154	9		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T35	7		T49	5		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T48	23		T154	3		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	18		T49	10		T127	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	9		T43	14		T56	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	14		T49	12		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	7		T7	14		T154	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	12		T56	8		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T2	11		T4	4		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	5		T130	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T124	1		T51	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	410	1			T4	26		T127	20		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T196	4		T20	9		T208	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T275	8		T167	11		T294	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T211	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T157	8		T213	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T198	15		T126	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	8		T122	3		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T51	7		T141	12		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T29	10		T128	3		T212	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T81	11		T32	4		T221	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	9		T29	7		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T8	1		T126	8		T202	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T35	2		T49	5		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T48	14		T125	18		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T49	13		T85	2		T269	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	9		T43	6		T56	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	12		T49	11		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	20		T132	2		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	9		T126	13		T39	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T4	15		T5	7		T11	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T43	10		T207	3		T18	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T141	10		T132	2		T206	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T4	24		T13	2		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	3		T51	8		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T122	4		T51	4		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T141	13		T138	12		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T3	1		T47	10		T29	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	5		T172	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T1	1		T35	6		T199	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T154	1		T126	9		T204	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T49	6		T124	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T48	15		T154	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T47	13		T49	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T8	12		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T123	1		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T4	16		T5	8		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	11		T56	10		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	1		T10	1		T48	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	4		T130	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T124	1		T51	1		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	26		T127	1		T37	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T181	1		T200	1		T196	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T10	1		T201	9		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T29	9		T175	13		T80	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T51	11		T143	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T51	2		T142	14		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	12		T156	13		T203	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	17		T128	4		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	2		T172	2		T202	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	13		T35	3		T199	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T154	8		T126	14		T204	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T49	4		T215	12		T149	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	22		T154	2		T56	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	17		T47	13		T49	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	6		T8	6		T43	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	11		T39	10		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T4	3		T7	13		T154	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	4		T56	7		T126	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	10		T48	4		T175	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	11		T139	5		T207	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T174	10		T132	12		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	24		T127	19		T174	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T200	11		T20	7		T238	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T201	11		T218	10		T293	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T126	1		T139	18		T210	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T29	12		T175	11		T80	21

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T174	1		T196	5		T20	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T10	1		T137	1		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T211	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T157	9		T213	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	3		T198	16		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T29	9		T122	4		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T51	8		T141	13		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T29	11		T128	4		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T172	1		T38	2		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T3	1		T47	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	5		T154	1		T126	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T35	6		T49	6		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T48	15		T154	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T49	14		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	12		T43	7		T56	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	13		T49	12		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	1		T7	21		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T56	10		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T2	1		T4	16		T5	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T43	11		T130	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T124	1		T51	1		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T4	26		T127	1		T13	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T174	10		T20	7		T208	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T137	13		T275	13		T218	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T211	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T157	6		T213	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	1		T126	1		T139	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T29	12		T51	2		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T51	11		T143	12		T138	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T29	9		T128	4		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T172	2		T81	8		T221	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	13		T29	8		T199	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	2		T154	8		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	3		T49	4		T205	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	22		T154	2		T144	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	17		T49	9		T127	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T8	6		T43	13		T56	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	13		T49	11		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	6		T7	13		T154	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	11		T56	7		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T2	10		T4	3		T48	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T43	4		T144	11		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T132	12		T216	7		T146	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T4	24		T127	19		T174	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27