Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23034

1

T2

30

T3

162

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

4102

1

T1

21

T2

11

T4

50

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20474

1

T1

21

T2

11

T3

161

auto[1]

6662

1

T2

30

T3

1

T4

69

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	430	1			T3	1		T47	26		T129	5
values[0]	65	1			T168	33		T152	10		T295	1
values[1]	854	1			T1	21		T2	12		T4	19
values[2]	872	1			T4	25		T48	37		T30	1
values[3]	901	1			T43	15		T13	4		T123	1
values[4]	661	1			T4	25		T8	18		T49	23
values[5]	2879	1			T5	8		T6	2		T11	8
values[6]	542	1			T7	34		T35	9		T47	10
values[7]	799	1			T2	11		T43	20		T198	16
values[8]	705	1			T2	18		T10	2		T172	1
values[9]	821	1			T154	9		T56	8		T38	2
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	833	1			T1	14		T2	12		T4	19
values[1]	920	1			T4	25		T43	15		T48	37
values[2]	782	1			T8	18		T13	4		T123	1
values[3]	2920	1			T4	25		T5	8		T6	2
values[4]	662	1			T7	34		T47	10		T122	4
values[5]	554	1			T43	20		T35	9		T49	23
values[6]	716	1			T2	11		T10	1		T172	1
values[7]	748	1			T2	18		T10	1		T125	20
values[8]	866	1			T3	1		T47	26		T154	9
values[9]	229	1			T129	5		T137	14		T223	21
minimum	17906	1			T1	7		T3	161		T7	122

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	12		T4	4		T154	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	14		T8	6		T49	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	23		T124	1		T212	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T4	12		T43	5		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	9		T13	2		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T123	1		T129	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T5	1		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	14		T13	3		T29	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T47	1		T122	1		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	14		T126	2		T132	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	7		T49	12		T127	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	14		T126	14		T141	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T51	1		T202	3		T175	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	11		T10	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	18		T125	1		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T125	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	1		T56	4		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T47	14		T154	9		T199	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T236	3		T296	7		T228	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T129	5		T137	14		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17583	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	7		T154	5		T147	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	15		T27	11		T51	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	1		T49	5		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	14		T212	10		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	13		T43	10		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	9		T13	2		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	3		T205	12		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T5	7		T11	7		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	11		T13	1		T29	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T47	9		T122	3		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	20		T126	8		T132	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T35	2		T49	11		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	6		T126	13		T141	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T202	10		T175	7		T81	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T198	15		T225	10		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T125	18		T126	8		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T226	2		T224	8		T81	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T56	4		T131	3		T141	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	12		T156	21		T79	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T296	8		T228	11		T93	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T223	10		T250	15		T251	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	2		T48	15		T29	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T147	10		T149	3		T207	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	1		T39	1		T214	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T47	14		T129	5		T199	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T297	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T168	16		T152	10		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	12		T4	4		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	21		T8	6		T49	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T48	23		T155	1		T143	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T4	12		T30	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	2		T172	1		T128	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T43	5		T123	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	9		T49	10		T39	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	14		T29	9		T56	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T5	1		T6	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	3		T29	13		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	7		T47	1		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	14		T126	14		T133	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T51	1		T202	3		T175	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	11		T43	14		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	18		T125	1		T126	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	2		T172	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T56	4		T38	2		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T154	9		T249	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T214	16		T203	14		T221	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T47	12		T156	8		T79	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T168	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	15		T48	15		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T49	5		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	14		T14	2		T206	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	13		T132	2		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	2		T128	3		T212	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T43	10		T51	3		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	9		T49	13		T39	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	11		T29	7		T56	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T5	7		T11	7		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T29	8		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T35	2		T47	9		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	20		T126	13		T133	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T202	10		T175	7		T224	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T43	6		T198	15		T141	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T125	18		T126	8		T157	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T226	2		T81	8		T86	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T56	4		T131	3		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T156	13		T224	8		T196	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	1		T4	16		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T8	5		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	15		T124	1		T212	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	14		T43	11		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	12		T13	4		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T123	1		T129	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T5	8		T6	2		T11	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	12		T13	3		T29	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T47	10		T122	4		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	21		T126	9		T132	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	6		T49	12		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	7		T126	14		T141	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T51	1		T202	11		T175	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T10	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T125	19		T126	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	1		T125	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	1		T56	5		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	13		T154	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T236	1		T296	9		T228	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T129	1		T137	1		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17669	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T1	1		T154	1		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	11		T4	3		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	13		T8	2		T49	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	22		T212	10		T143	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	11		T43	4		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	6		T128	4		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T51	2		T205	9		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T49	9		T24	30		T25	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	13		T13	1		T29	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T142	14		T235	8		T257	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	13		T126	1		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T35	3		T49	11		T127	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T43	13		T126	13		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T202	2		T175	8		T81	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	10		T225	7		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	17		T126	14		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T199	11		T226	8		T224	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T56	3		T225	10		T214	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	13		T154	8		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T236	2		T296	6		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T129	4		T137	13		T223	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T48	4		T127	11		T29	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T1	6		T154	4		T146	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	1		T39	1		T214	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T47	13		T129	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T297	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T168	18		T152	1		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T4	16		T48	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	2		T8	5		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	15		T155	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	14		T30	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	4		T172	1		T128	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T43	11		T123	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	12		T49	14		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	12		T29	8		T56	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T5	8		T6	2		T11	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	3		T29	9		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T35	6		T47	10		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	21		T126	14		T133	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T51	1		T202	11		T175	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	1		T43	7		T198	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T2	1		T125	19		T126	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T10	2		T172	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T56	5		T38	2		T131	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T154	1		T249	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T214	15		T203	13		T221	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T47	13		T129	4		T199	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T297	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T168	15		T152	9		T298	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	11		T4	3		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	19		T8	2		T49	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	22		T143	19		T137	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	11		T174	10		T132	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T128	4		T212	10		T231	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	4		T51	2		T205	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	6		T49	9		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	13		T29	8		T56	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T24	30		T25	34		T234	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T29	12		T126	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T35	3		T49	11		T127	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	13		T126	13		T133	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T202	2		T175	8		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	10		T43	13		T225	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T2	17		T126	14		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T199	11		T226	8		T81	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T56	3		T225	10		T139	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T154	8		T156	13		T224	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27