Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	16		T127	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T1	2		T8	5		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T48	15		T212	11		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T4	14		T43	11		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	12		T172	1		T128	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T129	1		T130	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T5	8		T6	2		T11	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	12		T13	3		T29	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T47	10		T49	14		T122	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	21		T126	9		T132	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	6		T49	12		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T43	7		T126	14		T141	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	1		T202	11		T175	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T10	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T125	19		T126	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	1		T125	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T56	5		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	13		T154	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T131	4		T39	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T129	1		T137	1		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17624	1			T2	1		T3	161		T7	122
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T4	3		T127	11		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T1	19		T8	2		T49	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	22		T212	10		T143	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	11		T43	4		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	6		T128	4		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T205	9		T188	10		T204	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T24	30		T25	34		T234	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	13		T13	1		T29	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	9		T142	14		T235	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	13		T126	1		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T35	3		T49	11		T127	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T43	13		T126	13		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T202	2		T175	8		T81	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	10		T225	7		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	17		T126	14		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T199	11		T226	8		T224	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T56	3		T225	10		T214	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T47	13		T154	8		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T220	4		T227	12		T236	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T129	4		T137	13		T223	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T2	11		T48	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T214	17		T221	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T161	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T168	18		T152	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T4	16		T48	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	2		T8	5		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	15		T128	4		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	14		T30	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	4		T172	1		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T43	11		T123	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	12		T49	14		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	12		T29	8		T56	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T5	8		T6	2		T11	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	3		T29	9		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	6		T47	10		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	21		T198	16		T126	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T125	19		T51	1		T202	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T43	7		T141	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	1		T126	9		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T10	2		T172	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T3	1		T56	5		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T47	13		T154	1		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T214	15		T221	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T168	15		T152	9		T230	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	11		T4	3		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	19		T8	2		T49	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	22		T128	4		T143	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	11		T132	10		T81	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T212	10		T174	4		T231	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T43	4		T51	2		T174	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	6		T49	9		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	13		T29	8		T56	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T49	11		T24	30		T25	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T29	12		T126	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T35	3		T127	19		T172	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	13		T126	13		T133	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T202	2		T175	8		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	10		T43	13		T225	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T2	17		T126	14		T144	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T199	11		T226	8		T81	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T56	3		T225	10		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T47	13		T154	8		T129	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27