Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23293

1

T1

21

T2

23

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3843

1

T2

18

T3

1

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20843

1

T2

11

T3

162

T7

156

auto[1]

6293

1

T1

21

T2

30

T4

69

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T56	17		T237	11		T238	7
values[0]	82	1			T10	1		T129	5		T175	16
values[1]	515	1			T47	10		T13	4		T188	21
values[2]	1023	1			T7	34		T8	18		T43	20
values[3]	810	1			T1	14		T43	15		T35	9
values[4]	2708	1			T2	18		T4	19		T5	8
values[5]	647	1			T2	12		T4	25		T127	20
values[6]	815	1			T4	25		T10	1		T48	20
values[7]	1013	1			T1	7		T3	1		T8	7
values[8]	673	1			T51	19		T126	23		T147	9
values[9]	1208	1			T2	11		T47	26		T49	10
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	974	1			T7	34		T10	1		T43	20
values[1]	862	1			T172	1		T125	20		T141	11
values[2]	743	1			T1	14		T4	19		T8	18
values[3]	2747	1			T2	18		T5	8		T6	2
values[4]	771	1			T2	12		T4	25		T10	1
values[5]	651	1			T1	7		T4	25		T135	7
values[6]	1030	1			T3	1		T8	7		T48	37
values[7]	755	1			T212	21		T51	25		T126	23
values[8]	748	1			T47	26		T49	10		T27	23
values[9]	248	1			T2	11		T154	5		T38	2
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	14		T10	1		T43	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T47	1		T13	3		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T172	1		T125	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T125	1		T141	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	14		T4	4		T8	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	10		T155	1		T143	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T5	1		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	18		T29	9		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	12		T154	3		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	14		T10	1		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	7		T4	12		T174	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T135	7		T131	1		T132	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T8	6		T49	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T3	1		T48	23		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T212	11		T51	3		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T51	12		T199	12		T214	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T49	5		T198	1		T126	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T47	14		T27	12		T56	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T2	11		T130	1		T80	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T154	5		T38	2		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	20		T43	6		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T47	9		T13	1		T231	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T147	10		T133	14		T202	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T125	18		T141	10		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	15		T8	9		T43	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	13		T175	12		T240	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T5	7		T11	7		T35	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T29	7		T122	3		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	2		T29	10		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	11		T48	15		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	13		T216	10		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T131	13		T132	2		T225	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T49	11		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	14		T197	16		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T212	10		T51	3		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T51	7		T214	17		T206	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	5		T198	15		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T47	12		T27	11		T56	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T80	11		T18	4		T235	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T156	8		T196	11		T221	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T56	8		T237	1		T238	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T10	1		T129	5		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T175	9		T242	1		T92	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T188	11		T199	9		T223	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	1		T13	3		T231	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T7	14		T8	9		T43	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T123	1		T125	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T1	14		T43	5		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	10		T137	14		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T4	4		T5	1		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	18		T172	3		T56	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	12		T127	20		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	14		T29	22		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T4	12		T29	10		T174	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T48	5		T128	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	7		T8	6		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T3	1		T48	23		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T126	15		T147	1		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	12		T155	1		T214	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	11		T49	5		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T47	14		T154	5		T27	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T56	9		T237	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T175	7		T242	4		T92	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T188	10		T223	10		T168	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T47	9		T13	1		T231	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	20		T8	9		T43	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T125	18		T141	10		T81	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	10		T35	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	13		T145	11		T240	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T4	15		T5	7		T11	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T56	4		T202	10		T188	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T204	10		T80	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T4	11		T29	15		T122	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	13		T29	10		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	15		T128	3		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	1		T49	11		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	14		T225	10		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T126	8		T147	8		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	7		T214	10		T206	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T49	5		T212	10		T198	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T47	12		T27	11		T126	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	21		T10	1		T43	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T47	10		T13	3		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T172	1		T125	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T125	19		T141	11		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T4	16		T8	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T49	14		T155	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T5	8		T6	2		T11	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	1		T29	8		T122	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T154	1		T13	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	12		T10	1		T48	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T4	14		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	1		T131	14		T132	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	5		T49	12		T141	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T3	1		T48	15		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T212	11		T51	4		T126	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T51	8		T199	1		T214	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	6		T198	16		T126	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T47	13		T27	12		T56	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T2	1		T130	1		T80	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T154	1		T38	2		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	13		T43	13		T154	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T231	17		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T174	10		T133	13		T197	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	18		T81	8		T85	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	13		T4	3		T8	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	9		T143	19		T137	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T35	3		T127	19		T24	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	17		T29	8		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	11		T154	2		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	13		T48	4		T29	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	6		T4	11		T174	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T135	6		T132	12		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	2		T49	11		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T48	22		T197	10		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T212	10		T51	2		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	11		T199	11		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T49	4		T126	13		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	13		T27	11		T56	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T2	10		T80	10		T18	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T154	4		T156	7		T221	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T56	10		T237	11		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T10	1		T129	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T175	8		T242	5		T92	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T188	11		T199	1		T223	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	10		T13	3		T231	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	21		T8	12		T43	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T123	1		T125	19		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T43	11		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T49	14		T137	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T4	16		T5	8		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	1		T172	1		T56	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T127	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	12		T29	17		T122	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T4	14		T29	11		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	1		T48	16		T128	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T8	5		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	1		T48	15		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T126	9		T147	9		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	8		T155	1		T214	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T2	1		T49	6		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T47	13		T154	1		T27	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T56	7		T238	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T129	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T175	8		T92	13		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T188	10		T199	8		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T231	17		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	13		T8	6		T43	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T139	18		T81	8		T85	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	13		T43	4		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	9		T137	13		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T4	3		T24	30		T25	34
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	17		T172	2		T56	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	11		T127	19		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	13		T29	20		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	11		T29	9		T174	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	4		T128	4		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	6		T8	2		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T48	22		T225	7		T197	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T126	14		T132	10		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	11		T214	7		T197	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	10		T49	4		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T47	13		T154	4		T27	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27