Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20976

1

T1

21

T2

18

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

6160

1

T2

23

T4

50

T5

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20585

1

T1

14

T2

12

T3

161

auto[1]

6551

1

T1

7

T2

29

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T244	3		-	-		-	-
values[0]	72	1			T156	5		T81	18		T221	23
values[1]	727	1			T2	18		T8	18		T43	20
values[2]	584	1			T1	21		T49	10		T154	5
values[3]	1018	1			T8	7		T10	1		T35	9
values[4]	686	1			T2	11		T43	15		T48	20
values[5]	674	1			T47	10		T13	4		T29	20
values[6]	750	1			T2	12		T3	1		T10	1
values[7]	772	1			T4	25		T27	23		T128	8
values[8]	731	1			T4	25		T38	2		T130	1
values[9]	3512	1			T4	19		T5	8		T6	2
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	919	1			T2	18		T43	20		T154	9
values[1]	2993	1			T1	21		T5	8		T6	2
values[2]	1007	1			T125	19		T141	11		T205	22
values[3]	550	1			T2	11		T43	15		T47	10
values[4]	677	1			T13	4		T29	20		T30	1
values[5]	817	1			T2	12		T3	1		T10	1
values[6]	812	1			T4	25		T49	23		T127	12
values[7]	694	1			T4	25		T13	4		T135	7
values[8]	856	1			T7	34		T47	26		T48	37
values[9]	204	1			T4	19		T129	5		T147	11
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	18		T154	9		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T43	14		T29	9		T51	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T1	21		T8	9		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1540	1			T5	1		T6	2		T8	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T199	9		T204	8		T139	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T125	1		T141	1		T205	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T47	1		T48	5		T154	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	11		T43	5		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	3		T29	10		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T56	8		T129	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T49	12		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	12		T10	1		T172	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T27	12		T123	1		T128	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T4	14		T49	10		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T147	1		T231	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	12		T135	7		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T48	23		T127	20		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	14		T47	14		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T4	4		T129	5		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T144	12		T175	9		T196	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T212	10		T141	3		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	6		T29	7		T51	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	9		T35	2		T39	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	977	1			T5	7		T8	1		T11	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T204	10		T156	13		T224	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T125	18		T141	10		T205	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T47	9		T48	15		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	10		T51	7		T126	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T29	10		T122	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T56	9		T131	13		T204	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	11		T32	4		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T37	1		T133	14		T214	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T27	11		T128	3		T175	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	11		T49	13		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	2		T231	15		T197	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	13		T41	1		T80	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	14		T126	13		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	20		T47	12		T29	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T4	15		T147	10		T245	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T175	7		T196	15		T222	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T156	3		T246	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T81	10		T221	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	18		T8	9		T154	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	14		T29	9		T51	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	21		T154	5		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T49	5		T198	1		T188	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T35	7		T155	1		T199	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T8	6		T10	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	5		T154	3		T56	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	11		T43	5		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	1		T13	3		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T172	1		T129	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T49	12		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	12		T10	1		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	12		T128	5		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	14		T147	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T126	14		T147	1		T144	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	12		T38	2		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T4	4		T48	23		T127	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1705	1			T5	1		T6	2		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T244	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T156	2		T246	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T81	8		T221	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	9		T212	10		T188	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	6		T29	7		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T141	3		T39	9		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T49	5		T198	15		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	2		T156	13		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	1		T141	10		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	15		T56	4		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	10		T125	18		T51	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	9		T13	1		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	13		T204	2		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	11		T145	11		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	13		T56	9		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T27	11		T128	3		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	11		T147	8		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T126	13		T175	5		T86	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	13		T80	11		T149	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	15		T48	14		T13	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1151	1			T5	7		T7	20		T11	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	1		T154	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T43	7		T29	8		T51	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	2		T8	12		T35	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1313	1			T5	8		T6	2		T8	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T199	1		T204	11		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T125	19		T141	11		T205	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	10		T48	16		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T43	11		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	3		T29	11		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	10		T129	1		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T49	12		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	1		T10	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T27	12		T123	1		T128	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	12		T49	14		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	4		T147	1		T231	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	14		T135	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	15		T127	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	21		T47	13		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T4	16		T129	1		T147	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T144	1		T175	8		T196	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	17		T154	8		T212	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	13		T29	8		T51	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	19		T8	6		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1204	1			T8	2		T49	4		T24	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T199	8		T204	7		T139	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T205	9		T225	10		T137	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T48	4		T154	2		T56	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	10		T43	4		T51	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T29	9		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T56	7		T204	13		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	11		T143	13		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	11		T172	2		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	11		T128	4		T175	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	13		T49	9		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T231	17		T197	10		T86	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	11		T135	6		T80	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T48	22		T127	19		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	13		T47	13		T29	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T4	3		T129	4		T245	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T144	11		T175	8		T222	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T244	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T156	3		T246	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T81	9		T221	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T8	12		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T43	7		T29	8		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T154	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T49	6		T198	16		T188	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T35	6		T155	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T8	5		T10	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	16		T154	1		T56	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T43	11		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T47	10		T13	3		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T172	1		T129	1		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T49	12		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T10	1		T49	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T27	12		T128	4		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	12		T147	9		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T126	14		T147	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T4	14		T38	2		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T4	16		T48	15		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1509	1			T5	8		T6	2		T7	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T156	2		T246	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T81	9		T221	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	17		T8	6		T154	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T43	13		T29	8		T51	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	19		T154	4		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T49	4		T188	11		T138	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T35	3		T199	8		T139	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	2		T205	9		T225	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	4		T154	2		T56	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	10		T43	4		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T29	9		T126	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T204	13		T16	1		T207	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T49	11		T143	13		T247	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	11		T49	9		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	11		T128	4		T146	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	13		T139	18		T84	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T126	13		T144	6		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	11		T143	19		T80	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T4	3		T48	22		T127	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1347	1			T7	13		T47	13		T24	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27