Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23305

1

T2

23

T3

161

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3831

1

T1

21

T2

18

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21069

1

T2

41

T3

161

T4

19

auto[1]

6067

1

T1

21

T3

1

T4

50

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T79	1		-	-		-	-
values[0]	56	1			T188	22		T206	5		T248	1
values[1]	798	1			T1	14		T3	1		T10	1
values[2]	2807	1			T5	8		T6	2		T11	8
values[3]	747	1			T4	25		T29	16		T172	1
values[4]	852	1			T4	25		T8	18		T154	3
values[5]	638	1			T1	7		T127	12		T13	4
values[6]	629	1			T123	1		T124	2		T51	25
values[7]	802	1			T2	18		T4	19		T10	1
values[8]	745	1			T43	20		T48	57		T29	20
values[9]	1454	1			T2	23		T7	34		T8	7
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	991	1			T1	14		T3	1		T10	1
values[1]	2946	1			T5	8		T6	2		T11	8
values[2]	755	1			T4	50		T29	16		T172	1
values[3]	619	1			T8	18		T154	3		T128	8
values[4]	616	1			T1	7		T127	12		T13	4
values[5]	686	1			T122	4		T123	1		T172	1
values[6]	994	1			T2	18		T4	19		T10	1
values[7]	658	1			T48	20		T29	20		T135	7
values[8]	1015	1			T2	23		T7	34		T49	10
values[9]	241	1			T8	7		T125	19		T126	10
minimum	17615	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T10	1		T35	7		T47	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	14		T3	1		T43	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T5	1		T6	2		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T172	3		T147	1		T214	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	14		T172	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	12		T29	9		T126	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	9		T154	3		T128	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	5		T129	5		T212	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T124	1		T51	3		T174	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	7		T127	12		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T122	1		T172	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T123	1		T124	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T43	14		T249	1		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	18		T4	4		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	5		T29	10		T135	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T155	1		T132	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T2	23		T7	14		T49	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T130	1		T126	15		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T8	6		T125	1		T126	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T79	1		T207	8		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T56	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T35	2		T47	12		T49	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T43	10		T47	9		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T5	7		T11	7		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	10		T214	23		T206	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	11		T39	9		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	13		T29	7		T126	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	9		T128	3		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T37	1		T212	10		T202	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T51	3		T205	12		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	2		T51	7		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T122	3		T141	12		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T198	15		T133	14		T80	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T43	6		T14	2		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	15		T48	14		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	15		T29	10		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T204	1		T145	11		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	20		T49	5		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T126	8		T131	13		T132	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T8	1		T125	18		T126	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T207	11		T250	10		T251	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T56	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T79	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T206	1		T248	1		T252	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T188	12		T253	12		T254	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	1		T49	10		T127	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	14		T3	1		T43	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T5	1		T6	2		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	1		T202	1		T214	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	14		T172	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T29	9		T126	14		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T8	9		T154	3		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	12		T37	5		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T205	10		T142	15		T41	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	7		T127	12		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T124	1		T51	3		T174	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T123	1		T124	1		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T122	1		T172	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	18		T4	4		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T43	14		T48	5		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	23		T174	11		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T2	23		T7	14		T8	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	421	1			T130	1		T126	15		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T206	4		T252	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T188	10		T254	2		T255	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T49	13		T147	8		T84	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	10		T47	9		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T5	7		T11	7		T35	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T147	10		T202	2		T214	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	11		T39	9		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	7		T126	13		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	9		T128	3		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	13		T37	1		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T205	12		T41	1		T81	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	2		T141	3		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T51	3		T14	2		T82	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T51	7		T226	2		T80	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T122	3		T141	12		T225	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	15		T198	15		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	6		T48	15		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	14		T204	1		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T7	20		T8	1		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T126	8		T131	13		T132	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	1		T35	6		T47	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	1		T3	1		T43	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T5	8		T6	2		T11	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T172	1		T147	11		T214	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	12		T172	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	14		T29	8		T126	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	12		T154	1		T128	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	6		T129	1		T212	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T124	1		T51	4		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T127	1		T13	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T122	4		T172	1		T141	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T123	1		T124	1		T198	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T43	7		T249	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T2	1		T4	16		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	16		T29	11		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T155	1		T132	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	2		T7	21		T49	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T130	1		T126	9		T131	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	5		T125	19		T126	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T79	1		T207	12		T250	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T56	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T35	3		T47	13		T49	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	13		T43	4		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T49	11		T24	30		T25	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T172	2		T214	22		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	13		T39	10		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	11		T29	8		T126	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	6		T154	2		T128	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	4		T212	10		T202	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T51	2		T174	4		T205	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	6		T127	11		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T225	7		T197	3		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	13		T199	8		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	13		T14	1		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	17		T4	3		T48	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	4		T29	9		T135	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T144	6		T175	11		T15	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	21		T7	13		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T126	14		T174	10		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T8	2		T126	1		T256	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T207	7		T251	10		T219	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T56	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T79	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T206	5		T248	1		T252	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T188	11		T253	1		T254	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T49	14		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T3	1		T43	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	8		T6	2		T11	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T147	11		T202	3		T214	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	12		T172	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	8		T126	14		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	12		T154	1		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	14		T37	6		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T205	13		T142	1		T41	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T127	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T124	1		T51	4		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T123	1		T124	1		T51	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T122	4		T172	1		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T4	16		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T43	7		T48	16		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	15		T174	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T2	2		T7	21		T8	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T130	1		T126	9		T131	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T188	11		T253	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	9		T127	19		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	13		T43	4		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T35	3		T47	13		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T214	15		T156	13		T257	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	13		T39	10		T203	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	8		T126	13		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	6		T154	2		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	11		T129	4		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T205	9		T142	14		T81	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	6		T127	11		T202	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	2		T174	4		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	11		T199	8		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T225	7		T16	1		T203	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	17		T4	3		T133	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T43	13		T48	4		T29	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	22		T174	10		T144	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T2	21		T7	13		T8	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T126	14		T132	10		T139	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27