Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23553

1

T1

14

T2

18

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3583

1

T1

7

T2

23

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20824

1

T1

21

T2

30

T3

162

auto[1]

6312

1

T2

11

T4

25

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T140	2		T258	19		-	-
values[0]	95	1			T48	37		T259	1		T260	23
values[1]	696	1			T7	34		T35	9		T47	10
values[2]	690	1			T1	14		T2	18		T49	56
values[3]	695	1			T2	11		T4	19		T10	1
values[4]	583	1			T43	15		T47	26		T172	3
values[5]	654	1			T2	12		T127	20		T154	12
values[6]	822	1			T1	7		T48	20		T29	20
values[7]	852	1			T4	25		T27	23		T30	1
values[8]	920	1			T29	21		T135	7		T124	2
values[9]	3501	1			T3	1		T4	25		T5	8
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	962	1			T2	18		T7	34		T35	9
values[1]	746	1			T1	14		T47	10		T49	33
values[2]	570	1			T2	11		T4	19		T10	1
values[3]	620	1			T43	15		T127	20		T188	21
values[4]	755	1			T1	7		T2	12		T154	12
values[5]	887	1			T48	20		T30	1		T124	1
values[6]	2984	1			T4	25		T5	8		T6	2
values[7]	911	1			T29	21		T124	1		T38	2
values[8]	829	1			T4	25		T8	18		T10	1
values[9]	245	1			T3	1		T8	7		T43	20
minimum	17627	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T2	18		T7	14		T48	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T35	7		T172	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	14		T47	1		T49	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	10		T127	12		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	1		T47	14		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T2	11		T4	4		T49	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	5		T199	12		T226	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T127	20		T188	11		T143	33
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	9		T29	10		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	7		T2	12		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T48	5		T30	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T125	1		T141	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T5	1		T6	2		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	14		T27	12		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T29	13		T38	2		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T124	1		T129	5		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T4	12		T130	1		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	9		T10	1		T154	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T8	6		T43	14		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T3	1		T240	9		T258	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T201	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	20		T48	14		T29	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T35	2		T198	15		T141	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	9		T49	5		T13	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	13		T37	1		T231	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	12		T13	1		T226	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	15		T49	11		T126	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	10		T226	2		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T188	10		T214	16		T206	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T29	10		T122	3		T56	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T128	3		T216	10		T15	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	15		T197	16		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T125	18		T141	10		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T5	7		T11	7		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	11		T27	11		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	8		T197	15		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T205	12		T188	10		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	13		T204	1		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	9		T51	3		T126	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T8	1		T43	6		T140	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T240	5		T258	4		T261	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T201	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T140	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T258	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T48	23		T259	1		T260	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	14		T47	1		T29	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T35	7		T172	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	14		T2	18		T49	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T49	22		T127	12		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	1		T13	3		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	11		T4	4		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T43	5		T47	14		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	14		T182	1		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T154	9		T122	1		T56	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	12		T127	20		T154	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T48	5		T29	10		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	7		T15	23		T80	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	1		T172	1		T56	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	14		T27	12		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T29	13		T135	7		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T124	2		T129	5		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1829	1			T4	12		T5	1		T6	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	1		T8	9		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T140	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T258	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T48	14		T260	10		T262	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	20		T47	9		T29	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T35	2		T198	15		T141	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	5		T13	2		T212	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	24		T37	1		T231	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	1		T126	8		T39	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	15		T126	8		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T43	10		T47	12		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T206	3		T175	7		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T122	3		T56	9		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T128	3		T188	10		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	15		T29	10		T132	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	14		T80	10		T247	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	4		T141	12		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T4	11		T27	11		T125	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	8		T131	3		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T205	12		T214	10		T226	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T4	13		T5	7		T8	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	9		T51	3		T126	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	1		T7	21		T48	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T35	6		T172	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T47	10		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T49	14		T127	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	1		T47	13		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T4	16		T49	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	11		T199	1		T226	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T127	1		T188	11		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T154	1		T29	11		T122	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T2	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T48	16		T30	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T125	19		T141	11		T147	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T5	8		T6	2		T11	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T4	12		T27	12		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T29	9		T38	2		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T124	1		T129	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	14		T130	1		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	12		T10	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T8	5		T43	7		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T3	1		T240	6		T258	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T201	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	17		T7	13		T48	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	3		T132	12		T224	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	13		T49	4		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T49	9		T127	11		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T47	13		T13	1		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T2	10		T4	3		T49	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	4		T199	11		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T127	19		T188	10		T143	31
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T154	8		T29	9		T56	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	6		T2	11		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	4		T197	10		T216	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T84	16		T247	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T24	30		T25	34		T56	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	13		T27	11		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T29	12		T143	13		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T129	4		T205	9		T188	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	11		T174	10		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	6		T154	4		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T8	2		T43	13		T81	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T240	8		T258	14		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T201	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T140	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T258	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T48	15		T259	1		T260	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	21		T47	10		T29	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T35	6		T172	1		T198	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T2	1		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	26		T127	1		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	1		T13	3		T126	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T4	16		T126	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T43	11		T47	13		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T137	1		T182	1		T206	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T154	1		T122	4		T56	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	1		T127	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T48	16		T29	11		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T15	22		T80	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T30	1		T172	1		T56	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T4	12		T27	12		T125	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T29	9		T135	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T124	2		T129	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T4	14		T5	8		T6	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T3	1		T8	12		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T258	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T48	22		T260	12		T262	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	13		T29	8		T202	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T35	3		T132	12		T247	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	13		T2	17		T49	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T49	20		T127	11		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T126	1		T39	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	10		T4	3		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T43	4		T47	13		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T137	13		T175	8		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T154	8		T56	7		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	11		T127	19		T154	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	4		T29	9		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	6		T15	15		T80	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T56	3		T197	10		T175	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	13		T27	11		T214	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T29	12		T135	6		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T129	4		T205	9		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T4	11		T8	2		T43	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	6		T154	4		T51	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27