Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23401

1

T1

7

T2

23

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

3735

1

T1

14

T2

18

T4

69

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20978

1

T1

7

T2

41

T3

161

auto[1]

6158

1

T1

14

T3

1

T4

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	288	1			T2	12		T135	7		T141	11
values[0]	30	1			T56	17		T238	13		-	-
values[1]	909	1			T4	50		T49	10		T128	8
values[2]	871	1			T3	1		T35	9		T154	3
values[3]	641	1			T8	18		T49	23		T127	20
values[4]	718	1			T10	1		T172	3		T124	1
values[5]	2764	1			T5	8		T6	2		T7	34
values[6]	759	1			T2	11		T8	7		T13	4
values[7]	676	1			T1	7		T2	18		T43	20
values[8]	614	1			T1	14		T43	15		T48	37
values[9]	1259	1			T4	19		T10	1		T47	36
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	909	1			T3	1		T4	25		T49	10
values[1]	868	1			T35	9		T49	23		T127	20
values[2]	531	1			T8	18		T154	9		T30	1
values[3]	2904	1			T5	8		T6	2		T10	1
values[4]	756	1			T7	34		T48	20		T29	20
values[5]	661	1			T2	11		T8	7		T13	4
values[6]	593	1			T1	7		T2	18		T43	20
values[7]	628	1			T1	14		T43	15		T47	10
values[8]	1281	1			T2	12		T4	19		T10	1
values[9]	124	1			T47	26		T81	18		T250	9
minimum	17881	1			T3	161		T4	25		T7	122

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	1		T154	3		T27	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	12		T49	5		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T122	1		T130	1		T132	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T35	7		T49	12		T127	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	9		T56	4		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T154	9		T30	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T5	1		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T172	3		T126	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T172	1		T125	1		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	14		T48	5		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	11		T8	6		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	2		T126	15		T156	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	7		T129	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	18		T43	14		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	5		T48	23		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	14		T47	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T2	12		T13	3		T29	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T4	4		T10	1		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T81	10		T250	1		T257	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T47	14		T265	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17582	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T4	14		T128	5		T204	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T27	11		T51	7		T126	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	13		T49	5		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T122	3		T132	2		T214	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	2		T49	11		T29	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	9		T56	4		T131	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T206	3		T79	2		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T5	7		T11	7		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T126	8		T39	9		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T125	18		T40	1		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	20		T48	15		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	1		T202	2		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	2		T126	8		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T147	10		T225	10		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	6		T175	5		T81	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T43	10		T48	14		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T47	9		T205	12		T206	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	1		T29	7		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T4	15		T49	13		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T81	8		T250	8		T263	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T47	12		T266	7		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	2		T56	9		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T4	11		T128	3		T204	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T2	12		T141	1		T149	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T135	7		T167	1		T267	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T56	8		T238	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T51	12		T126	14		T143	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	26		T49	5		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T154	3		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T35	7		T29	13		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	9		T56	4		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T49	12		T127	20		T154	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T124	1		T130	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	1		T172	3		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T5	1		T6	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	14		T48	5		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	11		T8	6		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	2		T125	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	7		T129	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	18		T43	14		T126	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	5		T48	23		T154	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	14		T123	1		T205	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T127	12		T13	3		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T4	4		T10	1		T47	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T141	10		T149	2		T263	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T167	11		T267	14		T258	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T56	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T51	7		T126	13		T231	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	24		T49	5		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T27	11		T122	3		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	2		T29	8		T141	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	9		T56	4		T131	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T49	11		T212	10		T79	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T225	10		T41	1		T80	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T126	8		T39	9		T202	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T5	7		T11	7		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	20		T48	15		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	1		T202	2		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	2		T198	15		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T147	10		T225	10		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T43	6		T126	8		T81	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T43	10		T48	14		T197	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T205	12		T175	5		T149	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	1		T29	7		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T4	15		T47	21		T49	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T154	1		T27	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T4	14		T49	6		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T122	4		T130	1		T132	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	6		T49	12		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	12		T56	5		T131	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	1		T30	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T5	8		T6	2		T11	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	1		T172	1		T126	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T172	1		T125	19		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T7	21		T48	16		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T8	5		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	4		T126	9		T156	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T129	1		T147	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T43	7		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	11		T48	15		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	1		T47	10		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T2	1		T13	3		T29	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T4	16		T10	1		T49	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T81	9		T250	9		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T47	13		T265	1		T266	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17669	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T4	12		T128	4		T204	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T154	2		T27	11		T51	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	11		T49	4		T188	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	10		T214	15		T197	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T35	3		T49	11		T127	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	6		T56	3		T226	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T154	8		T268	14		T235	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T24	30		T25	34		T234	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T172	2		T126	1		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T214	7		T156	13		T207	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	13		T48	4		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	10		T8	2		T143	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T126	14		T156	7		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	6		T225	7		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	17		T43	13		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	4		T48	22		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	13		T205	9		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	11		T13	1		T29	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T4	3		T49	9		T135	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T81	9		T257	11		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T47	13		T97	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T56	7		T143	13		T231	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T4	13		T128	4		T204	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T2	1		T141	11		T149	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T135	1		T167	12		T267	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T56	10		T238	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T51	8		T126	14		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T4	26		T49	6		T128	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T154	1		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	6		T29	9		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	12		T56	5		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T49	12		T127	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T124	1		T130	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T172	1		T126	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T5	8		T6	2		T11	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	21		T48	16		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	1		T8	5		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	4		T125	1		T198	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T129	1		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	1		T43	7		T126	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	11		T48	15		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T123	1		T205	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T127	1		T13	3		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T4	16		T10	1		T47	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T2	11		T149	1		T257	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T135	6		T267	9		T258	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T56	7		T238	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T51	11		T126	13		T143	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	24		T49	4		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T154	2		T27	11		T138	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T35	3		T29	12		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	6		T56	3		T132	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	11		T127	19		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T225	10		T80	11		T149	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T172	2		T126	1		T39	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T24	30		T25	34		T234	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	13		T48	4		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	10		T8	2		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T137	14		T156	7		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	6		T225	7		T143	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	17		T43	13		T126	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	4		T48	22		T154	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	13		T205	9		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T127	11		T13	1		T29	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T4	3		T47	13		T49	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27