Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21013

1

T1

21

T2

18

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

6123

1

T2

23

T4

50

T5

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20566

1

T1

14

T2

12

T3

161

auto[1]

6570

1

T1

7

T2

29

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	163	1			T175	16		T226	11		T269	12
values[0]	42	1			T175	24		T81	18		-	-
values[1]	788	1			T2	18		T43	20		T154	9
values[2]	566	1			T1	21		T8	18		T49	10
values[3]	1006	1			T8	7		T10	1		T35	9
values[4]	699	1			T2	11		T43	15		T48	20
values[5]	683	1			T47	10		T13	4		T29	20
values[6]	717	1			T3	1		T10	1		T49	46
values[7]	800	1			T2	12		T4	25		T127	12
values[8]	734	1			T4	25		T13	4		T135	7
values[9]	3331	1			T4	19		T5	8		T6	2
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	757	1			T2	18		T43	20		T49	10
values[1]	2881	1			T1	21		T5	8		T6	2
values[2]	1089	1			T43	15		T125	19		T141	11
values[3]	515	1			T2	11		T47	10		T48	20
values[4]	723	1			T13	4		T29	20		T30	1
values[5]	820	1			T2	12		T3	1		T10	1
values[6]	781	1			T4	25		T127	12		T27	23
values[7]	713	1			T4	25		T13	4		T135	7
values[8]	904	1			T7	34		T47	26		T48	37
values[9]	146	1			T4	19		T129	5		T175	16
minimum	17807	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	18		T154	9		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T43	14		T49	5		T29	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	21		T35	7		T154	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1536	1			T5	1		T6	2		T8	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T199	9		T204	8		T139	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T43	5		T125	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T47	1		T48	5		T154	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	11		T172	1		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	3		T29	10		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T56	8		T37	5		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T49	12		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	12		T10	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T27	12		T123	1		T128	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T4	14		T127	12		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	2		T126	14		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	12		T135	7		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T48	23		T127	20		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	14		T47	14		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T4	4		T129	5		T228	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T175	9		T248	1		T222	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17575	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T206	1		T175	12		T221	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T212	10		T141	3		T145	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T43	6		T49	5		T29	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	2		T39	9		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	964	1			T5	7		T8	10		T11	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T204	10		T156	13		T224	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T43	10		T125	18		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T47	9		T48	15		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	7		T126	8		T132	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T29	10		T122	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T56	9		T37	1		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T49	11		T32	4		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T49	13		T133	14		T214	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	11		T128	3		T175	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	11		T147	8		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	2		T126	13		T231	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	13		T41	1		T80	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	14		T147	10		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	20		T47	12		T29	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T4	15		T228	11		T270	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T175	7		T222	18		T260	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	2		T37	1		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T206	8		T175	12		T221	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T226	9		T271	1		T244	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T175	9		T269	1		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T175	12		T81	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T2	18		T154	9		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	14		T29	9		T51	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	21		T154	5		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	9		T49	5		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T35	7		T155	1		T199	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	6		T10	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	5		T154	3		T56	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	11		T43	5		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	1		T13	3		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T172	1		T56	8		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	1		T49	12		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	1		T49	10		T172	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T27	12		T123	1		T128	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	12		T4	14		T127	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	2		T126	14		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	12		T135	7		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T4	4		T48	23		T127	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1669	1			T5	1		T6	2		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T226	2		T271	9		T244	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T175	7		T269	11		T222	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T175	12		T81	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T212	10		T188	10		T226	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	6		T29	7		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T141	3		T39	9		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T8	9		T49	5		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T35	2		T156	13		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	1		T141	10		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	15		T56	4		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	10		T125	18		T51	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	9		T13	1		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T56	9		T131	13		T204	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	11		T145	11		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	13		T37	1		T133	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T27	11		T128	3		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	11		T147	8		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	2		T126	13		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	13		T149	3		T203	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	15		T48	14		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1104	1			T5	7		T7	20		T11	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T154	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T43	7		T49	6		T29	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	2		T35	6		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1298	1			T5	8		T6	2		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T199	1		T204	11		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T43	11		T125	19		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	10		T48	16		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T172	1		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	3		T29	11		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T56	10		T37	6		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T49	12		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	1		T10	1		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T27	12		T123	1		T128	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	12		T127	1		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	4		T126	14		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	14		T135	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	15		T127	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	21		T47	13		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T4	16		T129	1		T228	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T175	8		T248	1		T222	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17667	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T206	9		T175	13		T221	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	17		T154	8		T212	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	13		T49	4		T29	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	19		T35	3		T154	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T8	8		T24	30		T25	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T199	8		T204	7		T139	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T43	4		T205	9		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T48	4		T154	2		T56	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	10		T51	11		T126	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T29	9		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T56	7		T204	13		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	11		T143	13		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	11		T49	9		T172	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T27	11		T128	4		T175	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	13		T127	11		T143	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T126	13		T231	17		T86	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	11		T135	6		T80	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T48	22		T127	19		T144	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	13		T47	13		T29	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T4	3		T129	4		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T175	8		T222	15		T260	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T188	10		T156	9		T224	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T175	11		T221	8		T272	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T226	3		T271	10		T244	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T175	8		T269	12		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T175	13		T81	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T154	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T43	7		T29	8		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	2		T154	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	12		T49	6		T198	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T35	6		T155	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T8	5		T10	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	16		T154	1		T56	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T43	11		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T47	10		T13	3		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T172	1		T56	10		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T49	12		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	1		T49	14		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	12		T123	1		T128	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	1		T4	12		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	4		T126	14		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	14		T135	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T4	16		T48	15		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1448	1			T5	8		T6	2		T7	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T226	8		T273	6		T228	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T175	8		T222	1		T274	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T175	11		T81	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	17		T154	8		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	13		T29	8		T51	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	19		T154	4		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	6		T49	4		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T35	3		T199	8		T139	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	2		T205	9		T225	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	4		T154	2		T56	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	10		T43	4		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T29	9		T126	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T56	7		T204	13		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T49	11		T143	13		T247	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	9		T172	2		T133	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T27	11		T128	4		T146	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	11		T4	13		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T126	13		T175	2		T86	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	11		T135	6		T203	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T4	3		T48	22		T127	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T7	13		T47	13		T24	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27