Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23680

1

T1

7

T2

12

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3456

1

T1

14

T2

29

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20709

1

T1

7

T2

18

T3

160

auto[1]

6427

1

T1

14

T2

23

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	429	1			T3	2		T7	1		T8	1
values[0]	97	1			T48	20		T269	2		T152	10
values[1]	742	1			T2	12		T4	25		T47	10
values[2]	2860	1			T1	14		T5	8		T6	2
values[3]	743	1			T7	34		T35	9		T49	23
values[4]	479	1			T37	6		T198	16		T141	13
values[5]	762	1			T43	20		T29	16		T129	5
values[6]	723	1			T3	1		T27	23		T122	4
values[7]	730	1			T1	7		T4	19		T10	1
values[8]	894	1			T4	25		T8	18		T49	23
values[9]	1467	1			T2	29		T8	7		T10	1
minimum	17210	1			T3	159		T7	121		T8	90

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	857	1			T4	25		T47	10		T48	20
values[1]	2997	1			T1	14		T2	12		T5	8
values[2]	760	1			T56	17		T38	2		T141	13
values[3]	523	1			T7	34		T43	20		T35	9
values[4]	796	1			T126	10		T131	14		T147	9
values[5]	671	1			T1	7		T3	1		T27	23
values[6]	693	1			T4	19		T8	18		T13	4
values[7]	840	1			T2	11		T4	25		T10	1
values[8]	1115	1			T2	18		T8	7		T10	1
values[9]	267	1			T124	2		T155	1		T137	14
minimum	17617	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T48	5		T127	32		T29	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	12		T47	1		T172	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T2	12		T5	1		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	14		T172	1		T135	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T249	1		T182	1		T197	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T56	8		T38	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	14		T43	14		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T35	7		T29	9		T37	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T126	2		T131	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T147	1		T155	1		T202	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	7		T27	12		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T132	13		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	4		T8	9		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	3		T141	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T10	1		T154	5		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	11		T4	14		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	6		T49	5		T51	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T2	18		T10	1		T47	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T124	1		T155	1		T137	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T124	1		T214	8		T203	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T152	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T48	15		T29	10		T56	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	13		T47	9		T125	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T5	7		T11	7		T43	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T128	3		T216	10		T81	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T197	15		T226	4		T82	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	9		T141	12		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	20		T43	6		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T35	2		T29	7		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T126	8		T131	13		T202	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T147	8		T202	10		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T27	11		T122	3		T39	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T132	2		T140	1		T197	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	15		T8	9		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T13	1		T141	3		T205	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	2		T147	10		T132	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	11		T49	13		T212	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T49	5		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T47	12		T48	14		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T275	8		T276	7		T277	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T214	10		T203	2		T194	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T3	2		T7	1		T8	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T147	1		T278	11		T279	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T48	5		T269	1		T230	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T152	10		T229	4		T256	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	12		T127	32		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	12		T47	1		T172	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T5	1		T6	2		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	14		T172	1		T128	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	14		T49	12		T154	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T35	7		T56	8		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T198	1		T182	1		T226	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	5		T141	1		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T43	14		T129	5		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T29	9		T147	1		T202	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	12		T122	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T155	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	7		T4	4		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	3		T51	12		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T8	9		T154	5		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	14		T49	10		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	429	1			T8	6		T49	5		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T2	29		T10	1		T47	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17101	1			T3	159		T7	121		T8	88
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T278	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T48	15		T269	1		T230	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T229	7		T258	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T29	10		T56	4		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	13		T47	9		T125	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T5	7		T11	7		T43	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T128	3		T196	4		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T7	20		T49	11		T197	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	2		T56	9		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T198	15		T226	4		T224	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T37	1		T141	12		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T43	6		T126	8		T188	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T29	7		T147	8		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T27	11		T122	3		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	10		T140	1		T197	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	15		T13	2		T39	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T51	7		T141	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	9		T141	10		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	11		T49	13		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T8	1		T49	5		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T47	12		T48	14		T214	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T48	16		T127	2		T29	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	14		T47	10		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T2	1		T5	8		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T172	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T249	1		T182	1		T197	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T56	10		T38	2		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	21		T43	7		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T35	6		T29	8		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T126	9		T131	14		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T147	9		T155	1		T202	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T27	12		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T132	3		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	16		T8	12		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	3		T141	4		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T10	1		T154	1		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	1		T4	12		T49	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T8	5		T49	6		T51	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T2	1		T10	1		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T124	1		T155	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T124	1		T214	11		T203	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T152	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	4		T127	30		T29	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	11		T172	2		T138	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T2	11		T43	4		T49	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	13		T135	6		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T197	15		T226	18		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T56	7		T143	13		T81	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	13		T43	13		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T35	3		T29	8		T139	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T126	1		T188	11		T175	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T202	2		T240	8		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	6		T27	11		T39	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T132	12		T197	10		T175	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	3		T8	6		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T205	9		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T154	4		T132	10		T199	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	10		T4	13		T49	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	2		T49	4		T51	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	17		T47	13		T48	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T137	13		T144	6		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T214	7		T203	13		T280	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T152	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T3	2		T7	1		T8	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T147	1		T278	5		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T48	16		T269	2		T230	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T152	1		T229	9		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	1		T127	2		T29	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	14		T47	10		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T5	8		T6	2		T11	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T172	1		T128	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	21		T49	12		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T35	6		T56	10		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T198	16		T182	1		T226	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	6		T141	13		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T43	7		T129	1		T126	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	8		T147	9		T202	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T27	12		T122	4		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T155	1		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T4	16		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	3		T51	8		T141	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T8	12		T154	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	12		T49	14		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T8	5		T49	6		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T2	2		T10	1		T47	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T3	159		T7	121		T8	90
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T278	10		T279	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T48	4		T230	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T152	9		T229	2		T256	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	11		T127	30		T29	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	11		T172	2		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T43	4		T24	30		T25	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	13		T128	4		T139	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	13		T49	11		T154	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	3		T56	7		T174	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T226	18		T224	4		T207	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T143	13		T139	18		T215	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T43	13		T129	4		T126	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T29	8		T202	2		T253	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T27	11		T214	15		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T197	10		T175	8		T224	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	6		T4	3		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T51	11		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	6		T154	4		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	13		T49	9		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T8	2		T49	4		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T2	27		T47	13		T48	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27