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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.27


Total test records in report: 920
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T795 /workspace/coverage/default/11.adc_ctrl_poweron_counter.4204530045 Jul 15 06:07:20 PM PDT 24 Jul 15 06:07:24 PM PDT 24 3134451264 ps
T796 /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2780521502 Jul 15 06:10:39 PM PDT 24 Jul 15 06:32:17 PM PDT 24 608797268284 ps
T797 /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3194729103 Jul 15 06:09:48 PM PDT 24 Jul 15 06:10:31 PM PDT 24 41655952656 ps
T798 /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.263494217 Jul 15 06:07:45 PM PDT 24 Jul 15 06:16:36 PM PDT 24 499715406824 ps
T300 /workspace/coverage/default/25.adc_ctrl_fsm_reset.953378837 Jul 15 06:08:36 PM PDT 24 Jul 15 06:14:46 PM PDT 24 88174359500 ps
T799 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1260318646 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:41 PM PDT 24 506792160 ps
T800 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2094074113 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:50 PM PDT 24 380007021 ps
T60 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2141219763 Jul 15 06:06:22 PM PDT 24 Jul 15 06:06:26 PM PDT 24 968551640 ps
T61 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2514304511 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:33 PM PDT 24 627245452 ps
T53 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2632481986 Jul 15 06:06:42 PM PDT 24 Jul 15 06:06:47 PM PDT 24 2062699278 ps
T62 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2349283669 Jul 15 06:06:22 PM PDT 24 Jul 15 06:06:25 PM PDT 24 554514507 ps
T801 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3237267249 Jul 15 06:06:50 PM PDT 24 Jul 15 06:06:53 PM PDT 24 453822596 ps
T101 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3470047839 Jul 15 06:06:20 PM PDT 24 Jul 15 06:06:21 PM PDT 24 521320740 ps
T802 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1329374698 Jul 15 06:06:35 PM PDT 24 Jul 15 06:06:36 PM PDT 24 535547388 ps
T102 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1204758477 Jul 15 06:06:35 PM PDT 24 Jul 15 06:06:36 PM PDT 24 554417330 ps
T71 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2197099789 Jul 15 06:06:25 PM PDT 24 Jul 15 06:06:27 PM PDT 24 345828813 ps
T103 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.607160413 Jul 15 06:06:17 PM PDT 24 Jul 15 06:06:19 PM PDT 24 402501419 ps
T54 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3650201459 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:18 PM PDT 24 4498610000 ps
T55 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1090407405 Jul 15 06:06:21 PM PDT 24 Jul 15 06:06:25 PM PDT 24 2572416621 ps
T66 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.399281003 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:35 PM PDT 24 597293677 ps
T116 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1042526792 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:31 PM PDT 24 2373987568 ps
T69 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.965919217 Jul 15 06:06:13 PM PDT 24 Jul 15 06:06:16 PM PDT 24 713935273 ps
T803 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2596958920 Jul 15 06:06:41 PM PDT 24 Jul 15 06:06:43 PM PDT 24 429998719 ps
T87 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1085322234 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:18 PM PDT 24 509334077 ps
T67 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1491116424 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:26 PM PDT 24 718962607 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.386342351 Jul 15 06:06:15 PM PDT 24 Jul 15 06:06:17 PM PDT 24 354070964 ps
T104 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.776405369 Jul 15 06:06:13 PM PDT 24 Jul 15 06:06:19 PM PDT 24 1195641559 ps
T74 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.7401990 Jul 15 06:06:34 PM PDT 24 Jul 15 06:06:36 PM PDT 24 583161156 ps
T804 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.457498883 Jul 15 06:06:22 PM PDT 24 Jul 15 06:06:24 PM PDT 24 347599797 ps
T118 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2721877672 Jul 15 06:06:22 PM PDT 24 Jul 15 06:06:25 PM PDT 24 395283562 ps
T805 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3239591037 Jul 15 06:06:23 PM PDT 24 Jul 15 06:09:05 PM PDT 24 52721977206 ps
T70 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3371025555 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:27 PM PDT 24 445938168 ps
T806 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1281105280 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:49 PM PDT 24 313781037 ps
T119 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2336395845 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:42 PM PDT 24 3057488079 ps
T807 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.529764245 Jul 15 06:06:52 PM PDT 24 Jul 15 06:06:53 PM PDT 24 525232187 ps
T57 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2233706784 Jul 15 06:06:40 PM PDT 24 Jul 15 06:06:48 PM PDT 24 4262854107 ps
T120 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2528859648 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:27 PM PDT 24 387126753 ps
T98 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1327643209 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:25 PM PDT 24 581355945 ps
T72 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3749678007 Jul 15 06:06:29 PM PDT 24 Jul 15 06:06:32 PM PDT 24 320109036 ps
T58 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4090839779 Jul 15 06:06:35 PM PDT 24 Jul 15 06:06:58 PM PDT 24 8297476234 ps
T808 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1094763432 Jul 15 06:06:22 PM PDT 24 Jul 15 06:06:23 PM PDT 24 379551482 ps
T105 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2262433646 Jul 15 06:06:13 PM PDT 24 Jul 15 06:07:13 PM PDT 24 51657115758 ps
T809 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2251544106 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 312585928 ps
T68 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3523676521 Jul 15 06:06:04 PM PDT 24 Jul 15 06:06:07 PM PDT 24 704205225 ps
T810 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1490507209 Jul 15 06:06:43 PM PDT 24 Jul 15 06:06:47 PM PDT 24 2307814062 ps
T106 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3702329139 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:33 PM PDT 24 516785214 ps
T811 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1543288079 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:34 PM PDT 24 786081578 ps
T812 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2806963243 Jul 15 06:06:40 PM PDT 24 Jul 15 06:06:43 PM PDT 24 533348172 ps
T73 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.807831167 Jul 15 06:06:15 PM PDT 24 Jul 15 06:06:19 PM PDT 24 526803598 ps
T59 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.806557939 Jul 15 06:06:30 PM PDT 24 Jul 15 06:06:42 PM PDT 24 4614368546 ps
T813 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3250608403 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:26 PM PDT 24 989441354 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1180995606 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:28 PM PDT 24 1482164018 ps
T815 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1980010851 Jul 15 06:06:29 PM PDT 24 Jul 15 06:06:32 PM PDT 24 398935280 ps
T75 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1084379626 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:32 PM PDT 24 8327661863 ps
T299 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.790970723 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:44 PM PDT 24 8394962619 ps
T816 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2289307993 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:38 PM PDT 24 2113308533 ps
T817 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2263781867 Jul 15 06:06:41 PM PDT 24 Jul 15 06:06:43 PM PDT 24 476387068 ps
T818 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.158824984 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:26 PM PDT 24 449294100 ps
T819 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.403209127 Jul 15 06:07:16 PM PDT 24 Jul 15 06:07:18 PM PDT 24 541566951 ps
T820 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3036567130 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:16 PM PDT 24 314826201 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.189276973 Jul 15 06:06:15 PM PDT 24 Jul 15 06:07:12 PM PDT 24 25711975848 ps
T822 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3588428170 Jul 15 06:06:30 PM PDT 24 Jul 15 06:06:31 PM PDT 24 335925739 ps
T823 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3693804943 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:50 PM PDT 24 290431385 ps
T824 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1230471833 Jul 15 06:06:47 PM PDT 24 Jul 15 06:06:49 PM PDT 24 422379118 ps
T825 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1656277525 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 287979194 ps
T826 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1917581818 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:51 PM PDT 24 448079308 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2455984830 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:33 PM PDT 24 283566306 ps
T828 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.358247251 Jul 15 06:06:35 PM PDT 24 Jul 15 06:06:37 PM PDT 24 402416717 ps
T829 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3825224869 Jul 15 06:06:21 PM PDT 24 Jul 15 06:06:24 PM PDT 24 476636966 ps
T830 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4283037273 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:18 PM PDT 24 420365427 ps
T831 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.56175883 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 585226831 ps
T832 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2128687012 Jul 15 06:06:13 PM PDT 24 Jul 15 06:06:15 PM PDT 24 654476635 ps
T833 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4150248719 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:18 PM PDT 24 570491885 ps
T834 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3853953603 Jul 15 06:06:15 PM PDT 24 Jul 15 06:06:20 PM PDT 24 4510960162 ps
T76 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2828677149 Jul 15 06:06:17 PM PDT 24 Jul 15 06:06:22 PM PDT 24 10010221868 ps
T835 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3506603550 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:57 PM PDT 24 8410413167 ps
T836 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3700870721 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:50 PM PDT 24 476039724 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1535499407 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:59 PM PDT 24 4932162385 ps
T838 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.802542148 Jul 15 06:06:50 PM PDT 24 Jul 15 06:06:51 PM PDT 24 620810781 ps
T839 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2537076266 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:17 PM PDT 24 342760197 ps
T840 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3719216385 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:30 PM PDT 24 2208813815 ps
T841 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1563975035 Jul 15 06:06:05 PM PDT 24 Jul 15 06:06:20 PM PDT 24 9112058567 ps
T842 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3180432163 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 413611614 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3868681111 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:26 PM PDT 24 555656243 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2163434168 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:16 PM PDT 24 389506304 ps
T845 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.288588219 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:34 PM PDT 24 775951931 ps
T846 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1183325228 Jul 15 06:06:40 PM PDT 24 Jul 15 06:06:42 PM PDT 24 316727736 ps
T847 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2457196531 Jul 15 06:06:40 PM PDT 24 Jul 15 06:06:42 PM PDT 24 421851294 ps
T848 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3684531821 Jul 15 06:06:41 PM PDT 24 Jul 15 06:06:44 PM PDT 24 421756011 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3529785746 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:39 PM PDT 24 446813491 ps
T850 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3496383620 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 401023760 ps
T851 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3417308145 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:48 PM PDT 24 4612065092 ps
T852 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3425329928 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:18 PM PDT 24 930221524 ps
T853 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2330813962 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:29 PM PDT 24 8543920851 ps
T854 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2598892916 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:50 PM PDT 24 458691105 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2394494757 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:28 PM PDT 24 2429492958 ps
T107 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1071003882 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:18 PM PDT 24 1508724601 ps
T856 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3843352663 Jul 15 06:06:47 PM PDT 24 Jul 15 06:06:49 PM PDT 24 440350964 ps
T857 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.430720343 Jul 15 06:06:25 PM PDT 24 Jul 15 06:06:36 PM PDT 24 3862702293 ps
T858 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3758313679 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:41 PM PDT 24 500979427 ps
T859 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2344463303 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:28 PM PDT 24 372388110 ps
T108 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.660884227 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:17 PM PDT 24 520374922 ps
T860 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2095458388 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:30 PM PDT 24 4475604051 ps
T861 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2059144907 Jul 15 06:06:44 PM PDT 24 Jul 15 06:06:46 PM PDT 24 332632506 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1605561259 Jul 15 06:06:17 PM PDT 24 Jul 15 06:06:21 PM PDT 24 803772044 ps
T863 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3072092629 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:27 PM PDT 24 533209460 ps
T864 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.919135942 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:52 PM PDT 24 326534594 ps
T865 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3403307713 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:26 PM PDT 24 319646002 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1014671098 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:15 PM PDT 24 326802850 ps
T867 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3248555652 Jul 15 06:06:17 PM PDT 24 Jul 15 06:06:20 PM PDT 24 506795230 ps
T868 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3925378755 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:34 PM PDT 24 471132049 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.859398509 Jul 15 06:06:33 PM PDT 24 Jul 15 06:06:39 PM PDT 24 5342554048 ps
T870 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.994166446 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:36 PM PDT 24 857359118 ps
T871 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4071917070 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 380550567 ps
T872 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2067307501 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:42 PM PDT 24 491400876 ps
T873 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3232410182 Jul 15 06:06:34 PM PDT 24 Jul 15 06:06:38 PM PDT 24 4025360257 ps
T874 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1861154223 Jul 15 06:06:21 PM PDT 24 Jul 15 06:06:23 PM PDT 24 335857939 ps
T875 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1142867023 Jul 15 06:06:52 PM PDT 24 Jul 15 06:06:54 PM PDT 24 457134141 ps
T876 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1014492313 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:27 PM PDT 24 559698400 ps
T109 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2711440438 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:33 PM PDT 24 436304238 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3341929742 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:32 PM PDT 24 8260924762 ps
T878 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.389369721 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:19 PM PDT 24 538911704 ps
T110 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1078565004 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:35 PM PDT 24 570403372 ps
T111 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1130054437 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:41 PM PDT 24 390401873 ps
T879 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2818326722 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:50 PM PDT 24 405667871 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2921796030 Jul 15 06:06:13 PM PDT 24 Jul 15 06:06:25 PM PDT 24 4244939969 ps
T881 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2103349385 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 475725736 ps
T882 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.206752732 Jul 15 06:06:51 PM PDT 24 Jul 15 06:06:52 PM PDT 24 493311540 ps
T883 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.204187566 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:23 PM PDT 24 2182153533 ps
T884 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3622687313 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:42 PM PDT 24 1099814355 ps
T885 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.417836436 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:42 PM PDT 24 425156285 ps
T886 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1402119933 Jul 15 06:06:49 PM PDT 24 Jul 15 06:06:51 PM PDT 24 470897927 ps
T887 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2901663049 Jul 15 06:06:40 PM PDT 24 Jul 15 06:06:49 PM PDT 24 4302625477 ps
T888 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3651784200 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:37 PM PDT 24 4421473752 ps
T889 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3498853566 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:18 PM PDT 24 1285859188 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.454953511 Jul 15 06:06:13 PM PDT 24 Jul 15 06:06:40 PM PDT 24 37667096025 ps
T113 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2863877794 Jul 15 06:06:15 PM PDT 24 Jul 15 06:06:18 PM PDT 24 728738757 ps
T890 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1188598358 Jul 15 06:06:14 PM PDT 24 Jul 15 06:06:16 PM PDT 24 460583421 ps
T891 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2896958265 Jul 15 06:06:30 PM PDT 24 Jul 15 06:06:32 PM PDT 24 471618132 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.845387767 Jul 15 06:06:15 PM PDT 24 Jul 15 06:06:31 PM PDT 24 4797803966 ps
T893 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1890166866 Jul 15 06:06:51 PM PDT 24 Jul 15 06:06:54 PM PDT 24 457763037 ps
T894 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1251001025 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:49 PM PDT 24 372138564 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2059123209 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:44 PM PDT 24 8205810887 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3768484357 Jul 15 06:06:40 PM PDT 24 Jul 15 06:06:44 PM PDT 24 1028323491 ps
T897 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2974876328 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:33 PM PDT 24 573202735 ps
T898 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2971907647 Jul 15 06:06:41 PM PDT 24 Jul 15 06:06:43 PM PDT 24 352379999 ps
T899 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4036724933 Jul 15 06:06:23 PM PDT 24 Jul 15 06:06:28 PM PDT 24 590364433 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.37516120 Jul 15 06:06:05 PM PDT 24 Jul 15 06:06:06 PM PDT 24 337939448 ps
T901 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.939732745 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:39 PM PDT 24 2456380692 ps
T902 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2364763035 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:35 PM PDT 24 906327418 ps
T903 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1171192881 Jul 15 06:06:32 PM PDT 24 Jul 15 06:06:53 PM PDT 24 7934559551 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.807811424 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:41 PM PDT 24 450820699 ps
T905 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2274011545 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:41 PM PDT 24 423615981 ps
T906 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4119550249 Jul 15 06:06:14 PM PDT 24 Jul 15 06:08:25 PM PDT 24 26507325595 ps
T907 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1591615560 Jul 15 06:06:30 PM PDT 24 Jul 15 06:06:37 PM PDT 24 3995058174 ps
T908 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2671575807 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:33 PM PDT 24 465039959 ps
T909 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1533690415 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:42 PM PDT 24 470510293 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2922160634 Jul 15 06:06:38 PM PDT 24 Jul 15 06:06:51 PM PDT 24 4433827956 ps
T911 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3737907117 Jul 15 06:06:48 PM PDT 24 Jul 15 06:06:50 PM PDT 24 528092946 ps
T912 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.186852939 Jul 15 06:06:42 PM PDT 24 Jul 15 06:07:05 PM PDT 24 8278902765 ps
T913 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2098483931 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:39 PM PDT 24 8793004848 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.553682339 Jul 15 06:06:16 PM PDT 24 Jul 15 06:06:21 PM PDT 24 785668379 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2125897719 Jul 15 06:06:30 PM PDT 24 Jul 15 06:06:31 PM PDT 24 393476067 ps
T115 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2630564365 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:35 PM PDT 24 566020553 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.272951748 Jul 15 06:06:15 PM PDT 24 Jul 15 06:06:17 PM PDT 24 491600009 ps
T916 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3436941227 Jul 15 06:06:21 PM PDT 24 Jul 15 06:06:33 PM PDT 24 8020288376 ps
T917 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3606180137 Jul 15 06:06:31 PM PDT 24 Jul 15 06:06:32 PM PDT 24 450841459 ps
T918 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3098048802 Jul 15 06:06:24 PM PDT 24 Jul 15 06:06:26 PM PDT 24 491129598 ps
T919 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1471486852 Jul 15 06:06:47 PM PDT 24 Jul 15 06:06:49 PM PDT 24 521386483 ps
T920 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3958705098 Jul 15 06:06:39 PM PDT 24 Jul 15 06:06:51 PM PDT 24 4679123037 ps

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2812112654
Short name T8
Test name
Test status
Simulation time 385979424235 ps
CPU time 285.7 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:12:09 PM PDT 24
Peak memory 210440 kb
Host smart-de05dff1-0611-420a-a2ad-02e23efb8348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812112654 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2812112654
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1877159063
Short name T4
Test name
Test status
Simulation time 529987226184 ps
CPU time 73.38 seconds
Started Jul 15 06:07:58 PM PDT 24
Finished Jul 15 06:09:12 PM PDT 24
Peak memory 201856 kb
Host smart-e901eecf-8165-45fa-ac70-55ba383bf368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877159063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1877159063
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1885839557
Short name T51
Test name
Test status
Simulation time 686172366631 ps
CPU time 2141.59 seconds
Started Jul 15 06:07:48 PM PDT 24
Finished Jul 15 06:43:30 PM PDT 24
Peak memory 210464 kb
Host smart-a679c5eb-fc8a-4301-922e-c83cd8cd34a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885839557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1885839557
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1339230756
Short name T13
Test name
Test status
Simulation time 159101660503 ps
CPU time 98.17 seconds
Started Jul 15 06:09:40 PM PDT 24
Finished Jul 15 06:11:18 PM PDT 24
Peak memory 210288 kb
Host smart-2be9ddc6-bdb6-499f-8458-c5b0623a52cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339230756 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1339230756
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2260355154
Short name T3
Test name
Test status
Simulation time 295419794721 ps
CPU time 333.08 seconds
Started Jul 15 06:08:40 PM PDT 24
Finished Jul 15 06:14:14 PM PDT 24
Peak memory 202200 kb
Host smart-7d6b5c17-f827-4bd6-8693-8ba499fefc27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260355154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2260355154
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2046876055
Short name T175
Test name
Test status
Simulation time 573076670112 ps
CPU time 253.03 seconds
Started Jul 15 06:08:23 PM PDT 24
Finished Jul 15 06:12:37 PM PDT 24
Peak memory 201900 kb
Host smart-eb6721cd-8b2b-4424-a163-cb6d641b54ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046876055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2046876055
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1012755621
Short name T29
Test name
Test status
Simulation time 503552158978 ps
CPU time 306.55 seconds
Started Jul 15 06:08:45 PM PDT 24
Finished Jul 15 06:13:52 PM PDT 24
Peak memory 201876 kb
Host smart-a0264292-0269-47fb-a425-20e5b73bac60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012755621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1012755621
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2501365053
Short name T49
Test name
Test status
Simulation time 578272589478 ps
CPU time 369.1 seconds
Started Jul 15 06:09:45 PM PDT 24
Finished Jul 15 06:15:54 PM PDT 24
Peak memory 201908 kb
Host smart-ed0b2dbe-46c9-42c2-acda-71ff3bd64e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501365053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2501365053
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2875920681
Short name T40
Test name
Test status
Simulation time 56385695205 ps
CPU time 148.62 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:09:26 PM PDT 24
Peak memory 211496 kb
Host smart-116f61e6-dc63-4462-a99b-4f52f8b85f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875920681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2875920681
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3811193190
Short name T154
Test name
Test status
Simulation time 656323780162 ps
CPU time 344.28 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 201980 kb
Host smart-6d0e99bd-4950-4222-8d59-322c42aff8e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811193190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3811193190
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2141219763
Short name T60
Test name
Test status
Simulation time 968551640 ps
CPU time 2.94 seconds
Started Jul 15 06:06:22 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201728 kb
Host smart-89edebef-a058-42ac-ad04-13d2a48e39df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141219763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2141219763
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.413683072
Short name T126
Test name
Test status
Simulation time 504548110555 ps
CPU time 558.29 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:16:41 PM PDT 24
Peak memory 201924 kb
Host smart-333542bb-310e-4707-acd3-9a060d864ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413683072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.413683072
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1314430613
Short name T203
Test name
Test status
Simulation time 505148039837 ps
CPU time 451.02 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:14:38 PM PDT 24
Peak memory 201972 kb
Host smart-7d505639-4377-4d17-9b71-bce449f261f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314430613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1314430613
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1149537755
Short name T81
Test name
Test status
Simulation time 531157780630 ps
CPU time 1095.27 seconds
Started Jul 15 06:09:45 PM PDT 24
Finished Jul 15 06:28:01 PM PDT 24
Peak memory 201948 kb
Host smart-374f93a7-6d3b-4fc3-bcc0-1d345a30dbc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149537755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1149537755
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1337350821
Short name T44
Test name
Test status
Simulation time 333498176 ps
CPU time 1.41 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:07:55 PM PDT 24
Peak memory 201636 kb
Host smart-447438bc-60be-48ce-862e-aca20516de0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337350821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1337350821
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.615720679
Short name T224
Test name
Test status
Simulation time 582281180487 ps
CPU time 1245.48 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:32:01 PM PDT 24
Peak memory 201792 kb
Host smart-ff2381cd-10af-4878-9e27-f46faa9718d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615720679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.615720679
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2133615519
Short name T225
Test name
Test status
Simulation time 353069617361 ps
CPU time 817.71 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:20:54 PM PDT 24
Peak memory 201900 kb
Host smart-7f16d85b-715b-4313-9f2b-9827aeee7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133615519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2133615519
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2262433646
Short name T105
Test name
Test status
Simulation time 51657115758 ps
CPU time 59.65 seconds
Started Jul 15 06:06:13 PM PDT 24
Finished Jul 15 06:07:13 PM PDT 24
Peak memory 201820 kb
Host smart-66ddf4a6-7235-4b09-b197-99c1bb123886
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262433646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2262433646
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2118996525
Short name T77
Test name
Test status
Simulation time 8238720160 ps
CPU time 17.89 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:07:14 PM PDT 24
Peak memory 217884 kb
Host smart-bdc61632-10d0-4af5-a4e6-5c13c832d755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118996525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2118996525
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3088033329
Short name T56
Test name
Test status
Simulation time 329504253944 ps
CPU time 175.79 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:10:19 PM PDT 24
Peak memory 201888 kb
Host smart-02f87d0c-0bd6-490e-8380-7d353c4707a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088033329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3088033329
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3750430854
Short name T226
Test name
Test status
Simulation time 491884975773 ps
CPU time 586.38 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:17:21 PM PDT 24
Peak memory 202008 kb
Host smart-852dc38b-4883-43b2-b2f5-a0381e0ae146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750430854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3750430854
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.139454602
Short name T157
Test name
Test status
Simulation time 531908171476 ps
CPU time 239.87 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:11:05 PM PDT 24
Peak memory 201804 kb
Host smart-2740cb9c-ae49-4007-94e6-1cf74eb7f120
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139454602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.139454602
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1359518422
Short name T172
Test name
Test status
Simulation time 665702427729 ps
CPU time 1317.35 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:28:48 PM PDT 24
Peak memory 201912 kb
Host smart-d7eb2231-3a7e-4a40-8757-5fcbbe389aab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359518422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1359518422
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1628227385
Short name T258
Test name
Test status
Simulation time 349609541371 ps
CPU time 361.96 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:13:25 PM PDT 24
Peak memory 201952 kb
Host smart-8708f37d-3f35-45a3-97f7-875a06e834f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628227385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1628227385
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.108566968
Short name T251
Test name
Test status
Simulation time 526808270040 ps
CPU time 318.24 seconds
Started Jul 15 06:08:41 PM PDT 24
Finished Jul 15 06:14:00 PM PDT 24
Peak memory 201876 kb
Host smart-319de1ec-8b0b-4f87-8489-e47f96409ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108566968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.108566968
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2122017710
Short name T260
Test name
Test status
Simulation time 496318078958 ps
CPU time 308.01 seconds
Started Jul 15 06:08:56 PM PDT 24
Finished Jul 15 06:14:05 PM PDT 24
Peak memory 201948 kb
Host smart-d5810a75-5a7e-4cb7-b7a0-0de5b446bd39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122017710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2122017710
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1996077856
Short name T20
Test name
Test status
Simulation time 187570419795 ps
CPU time 208.69 seconds
Started Jul 15 06:11:20 PM PDT 24
Finished Jul 15 06:14:50 PM PDT 24
Peak memory 210516 kb
Host smart-124ab9e9-f5ce-472c-a5a2-6f5280b8e62c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996077856 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1996077856
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1926791843
Short name T168
Test name
Test status
Simulation time 350576981238 ps
CPU time 73.79 seconds
Started Jul 15 06:11:35 PM PDT 24
Finished Jul 15 06:12:49 PM PDT 24
Peak memory 201924 kb
Host smart-3f14bea4-7228-4068-9621-d26f9d971981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926791843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1926791843
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.495206138
Short name T201
Test name
Test status
Simulation time 348278305586 ps
CPU time 194.12 seconds
Started Jul 15 06:11:19 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 201876 kb
Host smart-086c6e08-62b5-4dfe-8df8-bd54c19cf224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495206138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
495206138
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1084379626
Short name T75
Test name
Test status
Simulation time 8327661863 ps
CPU time 7.27 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:32 PM PDT 24
Peak memory 201736 kb
Host smart-d4535cc4-cd9a-42d7-a346-505454351712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084379626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1084379626
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2391645198
Short name T214
Test name
Test status
Simulation time 486083025868 ps
CPU time 277.95 seconds
Started Jul 15 06:07:34 PM PDT 24
Finished Jul 15 06:12:13 PM PDT 24
Peak memory 201856 kb
Host smart-12032ace-86ec-4450-8476-1516deb22f64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391645198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2391645198
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3855745335
Short name T47
Test name
Test status
Simulation time 330991722356 ps
CPU time 780.83 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:19:58 PM PDT 24
Peak memory 201980 kb
Host smart-6858481d-1b8b-4dea-a8e8-d8735198b9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855745335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3855745335
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3737990995
Short name T24
Test name
Test status
Simulation time 395229738087 ps
CPU time 243.33 seconds
Started Jul 15 06:08:18 PM PDT 24
Finished Jul 15 06:12:22 PM PDT 24
Peak memory 201876 kb
Host smart-433aae5d-10dd-41ba-9c3f-9ed6284a4cff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737990995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3737990995
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3650201459
Short name T54
Test name
Test status
Simulation time 4498610000 ps
CPU time 3.21 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201808 kb
Host smart-82fa0d03-1397-4f4c-9765-c6d4db4fc4b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650201459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3650201459
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1025091356
Short name T144
Test name
Test status
Simulation time 523639134226 ps
CPU time 316.11 seconds
Started Jul 15 06:07:56 PM PDT 24
Finished Jul 15 06:13:12 PM PDT 24
Peak memory 201968 kb
Host smart-8fcb059e-9362-4eef-8313-89c4d87d29dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025091356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1025091356
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1982421717
Short name T2
Test name
Test status
Simulation time 573011841822 ps
CPU time 651.6 seconds
Started Jul 15 06:07:38 PM PDT 24
Finished Jul 15 06:18:30 PM PDT 24
Peak memory 201956 kb
Host smart-e6a654ea-26c9-4335-bef7-1be296cbb450
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982421717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1982421717
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2497529114
Short name T206
Test name
Test status
Simulation time 493763482905 ps
CPU time 979.68 seconds
Started Jul 15 06:08:10 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 202072 kb
Host smart-fa884897-14e8-4386-81b4-3a5a0c17bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497529114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2497529114
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.517578753
Short name T236
Test name
Test status
Simulation time 562634621072 ps
CPU time 1011.51 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:23:59 PM PDT 24
Peak memory 202004 kb
Host smart-2026295f-d1e4-44b9-8bac-c637acfe03a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517578753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.517578753
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.854065526
Short name T211
Test name
Test status
Simulation time 31550644823 ps
CPU time 92.45 seconds
Started Jul 15 06:07:42 PM PDT 24
Finished Jul 15 06:09:15 PM PDT 24
Peak memory 210528 kb
Host smart-3c005e03-043b-451a-882f-10966e03e905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854065526 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.854065526
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3082202600
Short name T129
Test name
Test status
Simulation time 363855797388 ps
CPU time 218.1 seconds
Started Jul 15 06:08:10 PM PDT 24
Finished Jul 15 06:11:49 PM PDT 24
Peak memory 201924 kb
Host smart-97f4973d-1704-4ca9-bfef-f753b4eac822
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082202600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3082202600
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3361247509
Short name T188
Test name
Test status
Simulation time 491487060017 ps
CPU time 924.47 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:22:32 PM PDT 24
Peak memory 210448 kb
Host smart-91e5fa3d-91be-4a71-950a-fc270434d656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361247509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3361247509
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.854848398
Short name T230
Test name
Test status
Simulation time 489665716654 ps
CPU time 1034.11 seconds
Started Jul 15 06:10:54 PM PDT 24
Finished Jul 15 06:28:08 PM PDT 24
Peak memory 201900 kb
Host smart-e89baad5-dd12-4bf3-ab81-da8d7add34eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854848398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.854848398
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.4156155023
Short name T275
Test name
Test status
Simulation time 345719621767 ps
CPU time 695.11 seconds
Started Jul 15 06:08:04 PM PDT 24
Finished Jul 15 06:19:40 PM PDT 24
Peak memory 201832 kb
Host smart-ddc2935b-6705-4de5-a528-2b7696131441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156155023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.4156155023
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3791476233
Short name T128
Test name
Test status
Simulation time 166113822585 ps
CPU time 90.74 seconds
Started Jul 15 06:08:31 PM PDT 24
Finished Jul 15 06:10:02 PM PDT 24
Peak memory 201920 kb
Host smart-7b0f1778-f6f4-47ef-9896-bb9ed67fe09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791476233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3791476233
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.973207498
Short name T243
Test name
Test status
Simulation time 324539270417 ps
CPU time 186.01 seconds
Started Jul 15 06:10:47 PM PDT 24
Finished Jul 15 06:13:54 PM PDT 24
Peak memory 201888 kb
Host smart-d055e51e-01b5-4d82-8d75-7bf8e89b159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973207498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.973207498
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.807831167
Short name T73
Test name
Test status
Simulation time 526803598 ps
CPU time 2.77 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:06:19 PM PDT 24
Peak memory 217548 kb
Host smart-608f634c-4d0c-4ac0-9f9b-650782939da9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807831167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.807831167
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3119866041
Short name T33
Test name
Test status
Simulation time 303121711312 ps
CPU time 1073.86 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:24:51 PM PDT 24
Peak memory 210484 kb
Host smart-a53c79d4-d871-4a67-8ede-13176c9c64a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119866041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3119866041
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2957000035
Short name T296
Test name
Test status
Simulation time 342606050922 ps
CPU time 219.93 seconds
Started Jul 15 06:07:25 PM PDT 24
Finished Jul 15 06:11:06 PM PDT 24
Peak memory 201856 kb
Host smart-9d997e7d-a2c6-4aa9-aca1-8535d915e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957000035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2957000035
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.246792660
Short name T244
Test name
Test status
Simulation time 333890072250 ps
CPU time 763.39 seconds
Started Jul 15 06:08:03 PM PDT 24
Finished Jul 15 06:20:48 PM PDT 24
Peak memory 201876 kb
Host smart-37b0794f-6e83-46cc-99fb-86a304585f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246792660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
246792660
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2532189290
Short name T262
Test name
Test status
Simulation time 55308664134 ps
CPU time 57.88 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:09:01 PM PDT 24
Peak memory 210540 kb
Host smart-42312f86-c1c7-423d-b30d-e6dc521551c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532189290 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2532189290
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3798213229
Short name T278
Test name
Test status
Simulation time 216207549453 ps
CPU time 501.44 seconds
Started Jul 15 06:08:38 PM PDT 24
Finished Jul 15 06:17:00 PM PDT 24
Peak memory 201868 kb
Host smart-e21e2c70-014c-43ad-b87c-91fea4c380da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798213229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3798213229
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3028835794
Short name T196
Test name
Test status
Simulation time 485310713672 ps
CPU time 531.01 seconds
Started Jul 15 06:09:57 PM PDT 24
Finished Jul 15 06:18:48 PM PDT 24
Peak memory 201972 kb
Host smart-03b3e2eb-eaf3-4683-953d-6b88e7229509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028835794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3028835794
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2350386763
Short name T297
Test name
Test status
Simulation time 528100112361 ps
CPU time 229.94 seconds
Started Jul 15 06:10:15 PM PDT 24
Finished Jul 15 06:14:06 PM PDT 24
Peak memory 201872 kb
Host smart-f178c17d-9a27-429f-afa9-9bae3f640dc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350386763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2350386763
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.430162823
Short name T156
Test name
Test status
Simulation time 493377050746 ps
CPU time 153.1 seconds
Started Jul 15 06:10:54 PM PDT 24
Finished Jul 15 06:13:28 PM PDT 24
Peak memory 201916 kb
Host smart-a467ac83-df6f-45ab-b8f6-9d28b94834f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430162823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.430162823
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3811512500
Short name T288
Test name
Test status
Simulation time 358660633653 ps
CPU time 212.89 seconds
Started Jul 15 06:10:53 PM PDT 24
Finished Jul 15 06:14:27 PM PDT 24
Peak memory 201956 kb
Host smart-e34a2811-e3c4-4d0c-bfc2-e5ec0be1cfae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811512500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3811512500
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2397874537
Short name T269
Test name
Test status
Simulation time 479911017840 ps
CPU time 1024.04 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:24:20 PM PDT 24
Peak memory 201956 kb
Host smart-1c54bada-1371-4b3b-9dbc-3233387cb41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397874537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2397874537
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2352804403
Short name T97
Test name
Test status
Simulation time 226116570840 ps
CPU time 118.79 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:09:20 PM PDT 24
Peak memory 202076 kb
Host smart-e06940a9-ee6b-4cc0-8b68-05df0612b9ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352804403 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2352804403
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2562023276
Short name T165
Test name
Test status
Simulation time 172225999976 ps
CPU time 106.76 seconds
Started Jul 15 06:06:58 PM PDT 24
Finished Jul 15 06:08:46 PM PDT 24
Peak memory 201892 kb
Host smart-dbd8981c-a593-4ebb-8f03-5941fc518d2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562023276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2562023276
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.691642244
Short name T162
Test name
Test status
Simulation time 508789970473 ps
CPU time 216.77 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:11:10 PM PDT 24
Peak memory 201920 kb
Host smart-c29efd1e-cdcc-40e3-8abb-d9edf5520042
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691642244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.691642244
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2167113765
Short name T140
Test name
Test status
Simulation time 446654987741 ps
CPU time 24.27 seconds
Started Jul 15 06:07:43 PM PDT 24
Finished Jul 15 06:08:08 PM PDT 24
Peak memory 201884 kb
Host smart-53c3d342-315d-406d-9399-8874250e1fe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167113765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2167113765
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3793787099
Short name T79
Test name
Test status
Simulation time 325383513065 ps
CPU time 735.82 seconds
Started Jul 15 06:07:56 PM PDT 24
Finished Jul 15 06:20:12 PM PDT 24
Peak memory 201916 kb
Host smart-be296200-d435-47fb-a7ff-fa12dc435639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793787099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3793787099
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3733398879
Short name T143
Test name
Test status
Simulation time 569366582007 ps
CPU time 223.64 seconds
Started Jul 15 06:08:20 PM PDT 24
Finished Jul 15 06:12:04 PM PDT 24
Peak memory 201900 kb
Host smart-2d1922c0-69d1-4ce3-8a26-74d7d0e262a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733398879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3733398879
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.407414428
Short name T152
Test name
Test status
Simulation time 365892391948 ps
CPU time 86.02 seconds
Started Jul 15 06:11:42 PM PDT 24
Finished Jul 15 06:13:09 PM PDT 24
Peak memory 201932 kb
Host smart-d72f69ae-6a7f-4d88-96ca-25da2ab77c4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407414428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.407414428
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1714613403
Short name T28
Test name
Test status
Simulation time 108161615325 ps
CPU time 563.9 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:16:31 PM PDT 24
Peak memory 202196 kb
Host smart-9e74c454-18d6-4bdd-a150-32807e5f6436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714613403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1714613403
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1888479142
Short name T194
Test name
Test status
Simulation time 419789718700 ps
CPU time 669.88 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:18:15 PM PDT 24
Peak memory 202152 kb
Host smart-750a1e11-2ccb-44f9-bf8a-c990aa512432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888479142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1888479142
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.233568538
Short name T413
Test name
Test status
Simulation time 87289668772 ps
CPU time 26.7 seconds
Started Jul 15 06:08:41 PM PDT 24
Finished Jul 15 06:09:08 PM PDT 24
Peak memory 210340 kb
Host smart-d8abcfa2-f9db-445e-95e3-0fcac9c18975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233568538 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.233568538
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.868769200
Short name T18
Test name
Test status
Simulation time 111911065396 ps
CPU time 179.12 seconds
Started Jul 15 06:08:49 PM PDT 24
Finished Jul 15 06:11:49 PM PDT 24
Peak memory 210260 kb
Host smart-f4779ca0-de92-4921-add6-47e0f7090070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868769200 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.868769200
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4052224538
Short name T185
Test name
Test status
Simulation time 192833493408 ps
CPU time 470.67 seconds
Started Jul 15 06:09:11 PM PDT 24
Finished Jul 15 06:17:03 PM PDT 24
Peak memory 211980 kb
Host smart-0295e0b7-dc2a-4ea6-92ba-7bcd4de1c731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052224538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4052224538
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.70057394
Short name T161
Test name
Test status
Simulation time 318439724946 ps
CPU time 196.65 seconds
Started Jul 15 06:10:31 PM PDT 24
Finished Jul 15 06:13:48 PM PDT 24
Peak memory 201896 kb
Host smart-6c40f017-beeb-42ba-905d-01bf9ccde07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70057394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.70057394
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2233706784
Short name T57
Test name
Test status
Simulation time 4262854107 ps
CPU time 6.82 seconds
Started Jul 15 06:06:40 PM PDT 24
Finished Jul 15 06:06:48 PM PDT 24
Peak memory 201752 kb
Host smart-e4f6c17e-80c7-427a-92b4-da5cb6e981fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233706784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2233706784
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1894173267
Short name T255
Test name
Test status
Simulation time 484413041182 ps
CPU time 264.56 seconds
Started Jul 15 06:06:47 PM PDT 24
Finished Jul 15 06:11:13 PM PDT 24
Peak memory 201844 kb
Host smart-5a217730-be76-429d-b8f5-b08207043708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894173267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1894173267
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2619207773
Short name T703
Test name
Test status
Simulation time 163969591605 ps
CPU time 195.46 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:10:39 PM PDT 24
Peak memory 201972 kb
Host smart-9b340444-1b5a-4f67-9f0a-48dccfce3acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619207773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2619207773
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.4213458991
Short name T302
Test name
Test status
Simulation time 444284587352 ps
CPU time 570.71 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:17:05 PM PDT 24
Peak memory 210396 kb
Host smart-307d02c8-96af-490f-bf7f-ea691639ff7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213458991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.4213458991
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4119428709
Short name T192
Test name
Test status
Simulation time 1089767933896 ps
CPU time 882.88 seconds
Started Jul 15 06:07:58 PM PDT 24
Finished Jul 15 06:22:41 PM PDT 24
Peak memory 212392 kb
Host smart-3f6586d2-0e05-4aa6-9832-0471cc2ccc23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119428709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4119428709
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3816717991
Short name T187
Test name
Test status
Simulation time 90500171122 ps
CPU time 295.69 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:12:58 PM PDT 24
Peak memory 202192 kb
Host smart-02084561-f668-4cf6-bf71-0f96c2f2a993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816717991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3816717991
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1380072231
Short name T193
Test name
Test status
Simulation time 155647201015 ps
CPU time 201.88 seconds
Started Jul 15 06:08:10 PM PDT 24
Finished Jul 15 06:11:33 PM PDT 24
Peak memory 210880 kb
Host smart-3743cec4-9e5a-4327-b336-70f316429bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380072231 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1380072231
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.772107962
Short name T276
Test name
Test status
Simulation time 169643662399 ps
CPU time 369.2 seconds
Started Jul 15 06:09:14 PM PDT 24
Finished Jul 15 06:15:24 PM PDT 24
Peak memory 201956 kb
Host smart-db1c1cd2-201f-47d9-afe1-df5a41055f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772107962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.772107962
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.139782563
Short name T600
Test name
Test status
Simulation time 101751950019 ps
CPU time 356.88 seconds
Started Jul 15 06:10:09 PM PDT 24
Finished Jul 15 06:16:06 PM PDT 24
Peak memory 202232 kb
Host smart-04b41c97-9690-4493-83a0-40502c74cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139782563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.139782563
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2095038734
Short name T274
Test name
Test status
Simulation time 176511576135 ps
CPU time 106.39 seconds
Started Jul 15 06:11:44 PM PDT 24
Finished Jul 15 06:13:31 PM PDT 24
Peak memory 210612 kb
Host smart-09d38d8d-df86-40dd-acdf-ceddb9b5402e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095038734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2095038734
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1071003882
Short name T107
Test name
Test status
Simulation time 1508724601 ps
CPU time 2.87 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201768 kb
Host smart-055c7e94-c3f6-4056-a66b-de0b77766875
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071003882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1071003882
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3250608403
Short name T813
Test name
Test status
Simulation time 989441354 ps
CPU time 1.25 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201508 kb
Host smart-2cfcdc69-ef83-4592-a9dc-cfd1cc32c13a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250608403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3250608403
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.389369721
Short name T878
Test name
Test status
Simulation time 538911704 ps
CPU time 1.96 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:19 PM PDT 24
Peak memory 201500 kb
Host smart-367d72e5-4548-42c9-9641-6d17528846ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389369721 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.389369721
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.660884227
Short name T108
Test name
Test status
Simulation time 520374922 ps
CPU time 2.01 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:17 PM PDT 24
Peak memory 201424 kb
Host smart-fcb9ff50-1b03-425f-96df-c924b06a7269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660884227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.660884227
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.37516120
Short name T900
Test name
Test status
Simulation time 337939448 ps
CPU time 0.87 seconds
Started Jul 15 06:06:05 PM PDT 24
Finished Jul 15 06:06:06 PM PDT 24
Peak memory 201420 kb
Host smart-50003a02-cbde-47ff-ba75-f7107b753cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.37516120
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3523676521
Short name T68
Test name
Test status
Simulation time 704205225 ps
CPU time 1.98 seconds
Started Jul 15 06:06:04 PM PDT 24
Finished Jul 15 06:06:07 PM PDT 24
Peak memory 201808 kb
Host smart-0346adb4-64d1-4806-85fa-6be21ce994a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523676521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3523676521
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1563975035
Short name T841
Test name
Test status
Simulation time 9112058567 ps
CPU time 13.89 seconds
Started Jul 15 06:06:05 PM PDT 24
Finished Jul 15 06:06:20 PM PDT 24
Peak memory 201816 kb
Host smart-2870350b-26bf-4a26-8673-672ceb7af0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563975035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1563975035
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1605561259
Short name T862
Test name
Test status
Simulation time 803772044 ps
CPU time 3.07 seconds
Started Jul 15 06:06:17 PM PDT 24
Finished Jul 15 06:06:21 PM PDT 24
Peak memory 201648 kb
Host smart-5c55b6ff-274c-4451-b9d7-a2fd58c5086b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605561259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1605561259
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.454953511
Short name T112
Test name
Test status
Simulation time 37667096025 ps
CPU time 26.19 seconds
Started Jul 15 06:06:13 PM PDT 24
Finished Jul 15 06:06:40 PM PDT 24
Peak memory 201772 kb
Host smart-60e0e576-76b1-40f1-aa48-7582b3db0ef6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454953511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.454953511
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2863877794
Short name T113
Test name
Test status
Simulation time 728738757 ps
CPU time 2.31 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201496 kb
Host smart-05d03237-65e1-4169-a824-1d5db14b5ce2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863877794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2863877794
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4283037273
Short name T830
Test name
Test status
Simulation time 420365427 ps
CPU time 1.09 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201500 kb
Host smart-3e845bfc-2233-4e55-bd6e-d143ec9716a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283037273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4283037273
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.386342351
Short name T117
Test name
Test status
Simulation time 354070964 ps
CPU time 0.91 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:06:17 PM PDT 24
Peak memory 201472 kb
Host smart-3bd1e2bb-2ae0-4d44-b465-81ba4a8a05dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386342351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.386342351
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3036567130
Short name T820
Test name
Test status
Simulation time 314826201 ps
CPU time 0.86 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:16 PM PDT 24
Peak memory 201444 kb
Host smart-2493c4e3-ef4b-4ddf-9110-944090c48fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036567130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3036567130
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3853953603
Short name T834
Test name
Test status
Simulation time 4510960162 ps
CPU time 3.39 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:06:20 PM PDT 24
Peak memory 201828 kb
Host smart-8d21a0a5-a357-45db-8d3d-f36c3ff675e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853953603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3853953603
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2921796030
Short name T880
Test name
Test status
Simulation time 4244939969 ps
CPU time 11.48 seconds
Started Jul 15 06:06:13 PM PDT 24
Finished Jul 15 06:06:25 PM PDT 24
Peak memory 201780 kb
Host smart-df5cdd28-403b-48c3-a0ac-6f24bb66c687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921796030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2921796030
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1543288079
Short name T811
Test name
Test status
Simulation time 786081578 ps
CPU time 1.35 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:34 PM PDT 24
Peak memory 201512 kb
Host smart-82ae101f-6e73-4558-b810-6a1d111445d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543288079 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1543288079
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3702329139
Short name T106
Test name
Test status
Simulation time 516785214 ps
CPU time 1.37 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201472 kb
Host smart-6c15a02e-eb92-468f-a957-f9a1de986360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702329139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3702329139
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2671575807
Short name T908
Test name
Test status
Simulation time 465039959 ps
CPU time 0.98 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201440 kb
Host smart-5b5247a3-719d-42e8-ac86-b49fa7a54a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671575807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2671575807
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2289307993
Short name T816
Test name
Test status
Simulation time 2113308533 ps
CPU time 5.34 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:38 PM PDT 24
Peak memory 201472 kb
Host smart-56a3a983-0cd1-4e9a-97d3-56319f8e594f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289307993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2289307993
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3436941227
Short name T916
Test name
Test status
Simulation time 8020288376 ps
CPU time 11.28 seconds
Started Jul 15 06:06:21 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201872 kb
Host smart-894d4495-b60f-4135-9cf1-e88cbd5cfc75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436941227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3436941227
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2974876328
Short name T897
Test name
Test status
Simulation time 573202735 ps
CPU time 1.54 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201480 kb
Host smart-dee14e49-89b2-4801-8c50-5c5c1ae026c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974876328 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2974876328
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2896958265
Short name T891
Test name
Test status
Simulation time 471618132 ps
CPU time 1.27 seconds
Started Jul 15 06:06:30 PM PDT 24
Finished Jul 15 06:06:32 PM PDT 24
Peak memory 201464 kb
Host smart-62235c4c-e246-45c5-995b-8bf1dcbab376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896958265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2896958265
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2455984830
Short name T827
Test name
Test status
Simulation time 283566306 ps
CPU time 1.27 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201388 kb
Host smart-98a0c4ac-7597-481f-a59c-57c11c00625f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455984830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2455984830
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.939732745
Short name T901
Test name
Test status
Simulation time 2456380692 ps
CPU time 5.59 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:39 PM PDT 24
Peak memory 201612 kb
Host smart-a7334fda-ce86-49fe-9cd6-2db6a69b38c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939732745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.939732745
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.399281003
Short name T66
Test name
Test status
Simulation time 597293677 ps
CPU time 2.1 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:35 PM PDT 24
Peak memory 201688 kb
Host smart-912e700b-135b-43a7-91c8-b5c405604a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399281003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.399281003
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4090839779
Short name T58
Test name
Test status
Simulation time 8297476234 ps
CPU time 21.81 seconds
Started Jul 15 06:06:35 PM PDT 24
Finished Jul 15 06:06:58 PM PDT 24
Peak memory 201776 kb
Host smart-19787d4a-bd08-4822-8f9a-af6fd3fb0b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090839779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4090839779
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2514304511
Short name T61
Test name
Test status
Simulation time 627245452 ps
CPU time 1.69 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201816 kb
Host smart-229b7d97-c0d2-4c07-9982-f49adc497f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514304511 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2514304511
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2630564365
Short name T115
Test name
Test status
Simulation time 566020553 ps
CPU time 2.05 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:35 PM PDT 24
Peak memory 201452 kb
Host smart-d5076319-b97b-412c-97e6-14e8b077c077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630564365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2630564365
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3588428170
Short name T822
Test name
Test status
Simulation time 335925739 ps
CPU time 0.84 seconds
Started Jul 15 06:06:30 PM PDT 24
Finished Jul 15 06:06:31 PM PDT 24
Peak memory 201416 kb
Host smart-ede96b14-9f50-4fd7-aead-5d5cd3e6ab56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588428170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3588428170
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.859398509
Short name T869
Test name
Test status
Simulation time 5342554048 ps
CPU time 5.4 seconds
Started Jul 15 06:06:33 PM PDT 24
Finished Jul 15 06:06:39 PM PDT 24
Peak memory 201820 kb
Host smart-f39b455e-4a57-4ae0-89d7-e7f1562d2bc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859398509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.859398509
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.288588219
Short name T845
Test name
Test status
Simulation time 775951931 ps
CPU time 1.87 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:34 PM PDT 24
Peak memory 201768 kb
Host smart-dfdb00b5-509b-472f-bdb0-6745a1186787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288588219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.288588219
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1591615560
Short name T907
Test name
Test status
Simulation time 3995058174 ps
CPU time 6.46 seconds
Started Jul 15 06:06:30 PM PDT 24
Finished Jul 15 06:06:37 PM PDT 24
Peak memory 201744 kb
Host smart-52330b02-3f81-428c-aac4-ba8eb1d4480c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591615560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1591615560
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.7401990
Short name T74
Test name
Test status
Simulation time 583161156 ps
CPU time 1.3 seconds
Started Jul 15 06:06:34 PM PDT 24
Finished Jul 15 06:06:36 PM PDT 24
Peak memory 201592 kb
Host smart-e57f0b68-e0ae-468f-967b-83216140b4f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7401990 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.7401990
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1204758477
Short name T102
Test name
Test status
Simulation time 554417330 ps
CPU time 1.46 seconds
Started Jul 15 06:06:35 PM PDT 24
Finished Jul 15 06:06:36 PM PDT 24
Peak memory 201412 kb
Host smart-e3abd21b-bcef-428e-a004-f595abcc26ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204758477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1204758477
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3606180137
Short name T917
Test name
Test status
Simulation time 450841459 ps
CPU time 0.74 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:32 PM PDT 24
Peak memory 201400 kb
Host smart-dd90daa5-f507-47a5-9c62-6c17cbe10971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606180137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3606180137
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3232410182
Short name T873
Test name
Test status
Simulation time 4025360257 ps
CPU time 3.99 seconds
Started Jul 15 06:06:34 PM PDT 24
Finished Jul 15 06:06:38 PM PDT 24
Peak memory 201820 kb
Host smart-a1dea18a-82d1-4bd1-bda8-af3f910dfe72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232410182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3232410182
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3749678007
Short name T72
Test name
Test status
Simulation time 320109036 ps
CPU time 1.96 seconds
Started Jul 15 06:06:29 PM PDT 24
Finished Jul 15 06:06:32 PM PDT 24
Peak memory 201664 kb
Host smart-21709877-7330-4a7c-b3e6-0940ecb091ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749678007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3749678007
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3651784200
Short name T888
Test name
Test status
Simulation time 4421473752 ps
CPU time 3.77 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:37 PM PDT 24
Peak memory 201704 kb
Host smart-5c3f328f-d073-48cb-89a7-d705693be685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651784200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3651784200
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3925378755
Short name T868
Test name
Test status
Simulation time 471132049 ps
CPU time 2.07 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:34 PM PDT 24
Peak memory 201524 kb
Host smart-b52a99ca-b38c-485b-8eb8-02ec967212b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925378755 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3925378755
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1078565004
Short name T110
Test name
Test status
Simulation time 570403372 ps
CPU time 2.06 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:35 PM PDT 24
Peak memory 201504 kb
Host smart-ff668c92-c0ef-4c40-9b7a-09f99ab94ca7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078565004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1078565004
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1329374698
Short name T802
Test name
Test status
Simulation time 535547388 ps
CPU time 0.97 seconds
Started Jul 15 06:06:35 PM PDT 24
Finished Jul 15 06:06:36 PM PDT 24
Peak memory 201348 kb
Host smart-a6d1896d-e605-47d6-9e23-bea2de25b8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329374698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1329374698
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3417308145
Short name T851
Test name
Test status
Simulation time 4612065092 ps
CPU time 15 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:48 PM PDT 24
Peak memory 201700 kb
Host smart-d8420ad4-e648-426a-83ae-4bb5ce1b293e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417308145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3417308145
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2364763035
Short name T902
Test name
Test status
Simulation time 906327418 ps
CPU time 2.56 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:35 PM PDT 24
Peak memory 218112 kb
Host smart-d4ab48ae-f84f-43c1-8fac-f598dfddf729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364763035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2364763035
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2098483931
Short name T913
Test name
Test status
Simulation time 8793004848 ps
CPU time 6.47 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:39 PM PDT 24
Peak memory 201800 kb
Host smart-d0643896-2d50-4b69-abed-2959778a7bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098483931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2098483931
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1533690415
Short name T909
Test name
Test status
Simulation time 470510293 ps
CPU time 1.86 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201480 kb
Host smart-37ec5403-ce99-4c63-866c-83de37e4f553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533690415 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1533690415
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1980010851
Short name T815
Test name
Test status
Simulation time 398935280 ps
CPU time 1.72 seconds
Started Jul 15 06:06:29 PM PDT 24
Finished Jul 15 06:06:32 PM PDT 24
Peak memory 201500 kb
Host smart-3e493ba5-d748-4e4f-883a-268ad2c6dbd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980010851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1980010851
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.358247251
Short name T828
Test name
Test status
Simulation time 402416717 ps
CPU time 0.93 seconds
Started Jul 15 06:06:35 PM PDT 24
Finished Jul 15 06:06:37 PM PDT 24
Peak memory 201348 kb
Host smart-e7fc54a2-c2f2-4e65-9cc2-80bc33d9448e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358247251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.358247251
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3958705098
Short name T920
Test name
Test status
Simulation time 4679123037 ps
CPU time 10.72 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201792 kb
Host smart-15ea4e0e-0388-4bab-a6bd-276ac798627d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958705098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3958705098
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.994166446
Short name T870
Test name
Test status
Simulation time 857359118 ps
CPU time 3.57 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:36 PM PDT 24
Peak memory 210960 kb
Host smart-80183f1b-00e0-4d67-a8c2-3774eec62fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994166446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.994166446
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1171192881
Short name T903
Test name
Test status
Simulation time 7934559551 ps
CPU time 20.69 seconds
Started Jul 15 06:06:32 PM PDT 24
Finished Jul 15 06:06:53 PM PDT 24
Peak memory 201868 kb
Host smart-ed5f8b51-1cb8-4cd4-b480-01d00a051e45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171192881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1171192881
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.417836436
Short name T885
Test name
Test status
Simulation time 425156285 ps
CPU time 1.73 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201524 kb
Host smart-3469bf7a-e617-4c15-8646-b69b39ac125b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417836436 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.417836436
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.807811424
Short name T904
Test name
Test status
Simulation time 450820699 ps
CPU time 1.19 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:41 PM PDT 24
Peak memory 201480 kb
Host smart-9df49df9-888d-490a-8ac6-9ae3369c811b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807811424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.807811424
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2274011545
Short name T905
Test name
Test status
Simulation time 423615981 ps
CPU time 0.9 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:41 PM PDT 24
Peak memory 201428 kb
Host smart-d1df0322-be8f-4522-a28b-4cdbe1775385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274011545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2274011545
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1490507209
Short name T810
Test name
Test status
Simulation time 2307814062 ps
CPU time 3.13 seconds
Started Jul 15 06:06:43 PM PDT 24
Finished Jul 15 06:06:47 PM PDT 24
Peak memory 201632 kb
Host smart-0be541b5-f072-4286-8186-1c0b1f13d16e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490507209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1490507209
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3768484357
Short name T896
Test name
Test status
Simulation time 1028323491 ps
CPU time 3.32 seconds
Started Jul 15 06:06:40 PM PDT 24
Finished Jul 15 06:06:44 PM PDT 24
Peak memory 210944 kb
Host smart-4171edfc-7328-44ce-8fa5-739ceb68282c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768484357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3768484357
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2067307501
Short name T872
Test name
Test status
Simulation time 491400876 ps
CPU time 1.69 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201556 kb
Host smart-16895a23-e392-41e7-8f14-19686b997342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067307501 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2067307501
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1130054437
Short name T111
Test name
Test status
Simulation time 390401873 ps
CPU time 1.03 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:41 PM PDT 24
Peak memory 201504 kb
Host smart-2a4b687f-cc97-4db2-bcb3-d3543c87d552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130054437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1130054437
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3529785746
Short name T849
Test name
Test status
Simulation time 446813491 ps
CPU time 0.7 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:39 PM PDT 24
Peak memory 201392 kb
Host smart-875d86ce-7761-41c6-a78e-f90b683b83e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529785746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3529785746
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1535499407
Short name T837
Test name
Test status
Simulation time 4932162385 ps
CPU time 20.67 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:59 PM PDT 24
Peak memory 201828 kb
Host smart-c22f3cee-cb86-43d6-980d-1447670d8187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535499407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1535499407
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3684531821
Short name T848
Test name
Test status
Simulation time 421756011 ps
CPU time 2.41 seconds
Started Jul 15 06:06:41 PM PDT 24
Finished Jul 15 06:06:44 PM PDT 24
Peak memory 201752 kb
Host smart-61638577-ddfd-470d-a3c6-87b00a820024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684531821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3684531821
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3506603550
Short name T835
Test name
Test status
Simulation time 8410413167 ps
CPU time 17.17 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:57 PM PDT 24
Peak memory 201820 kb
Host smart-f09fd2ed-4bc5-4306-a31a-ddc2d05a4f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506603550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3506603550
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3758313679
Short name T858
Test name
Test status
Simulation time 500979427 ps
CPU time 1.53 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:41 PM PDT 24
Peak memory 201552 kb
Host smart-009c10d8-0c9e-4768-8530-d0e5b2f515f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758313679 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3758313679
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2457196531
Short name T847
Test name
Test status
Simulation time 421851294 ps
CPU time 1 seconds
Started Jul 15 06:06:40 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201484 kb
Host smart-498ad21d-e966-428a-b234-62bd1b0010ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457196531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2457196531
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1183325228
Short name T846
Test name
Test status
Simulation time 316727736 ps
CPU time 1.41 seconds
Started Jul 15 06:06:40 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201392 kb
Host smart-dcc1a407-123f-4ea2-82aa-2b12a2a3a0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183325228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1183325228
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2901663049
Short name T887
Test name
Test status
Simulation time 4302625477 ps
CPU time 8.69 seconds
Started Jul 15 06:06:40 PM PDT 24
Finished Jul 15 06:06:49 PM PDT 24
Peak memory 201812 kb
Host smart-8a387515-ac73-4e40-a737-06cd46271d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901663049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2901663049
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2059144907
Short name T861
Test name
Test status
Simulation time 332632506 ps
CPU time 1.99 seconds
Started Jul 15 06:06:44 PM PDT 24
Finished Jul 15 06:06:46 PM PDT 24
Peak memory 201804 kb
Host smart-762141e7-d205-4457-98e7-543549be7bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059144907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2059144907
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2922160634
Short name T910
Test name
Test status
Simulation time 4433827956 ps
CPU time 11.34 seconds
Started Jul 15 06:06:38 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201836 kb
Host smart-9690e9f8-e84a-42d2-a82d-8934965ca3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922160634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2922160634
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2263781867
Short name T817
Test name
Test status
Simulation time 476387068 ps
CPU time 1.54 seconds
Started Jul 15 06:06:41 PM PDT 24
Finished Jul 15 06:06:43 PM PDT 24
Peak memory 201548 kb
Host smart-44fc8f3f-5c7c-42a7-9d3f-c57202291ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263781867 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2263781867
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2971907647
Short name T898
Test name
Test status
Simulation time 352379999 ps
CPU time 1.53 seconds
Started Jul 15 06:06:41 PM PDT 24
Finished Jul 15 06:06:43 PM PDT 24
Peak memory 201488 kb
Host smart-d20f663b-e044-45cf-b48f-87cec06397f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971907647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2971907647
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2806963243
Short name T812
Test name
Test status
Simulation time 533348172 ps
CPU time 1.82 seconds
Started Jul 15 06:06:40 PM PDT 24
Finished Jul 15 06:06:43 PM PDT 24
Peak memory 201408 kb
Host smart-31aa810c-ec8f-4a61-a57a-39a6ffb9b307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806963243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2806963243
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2632481986
Short name T53
Test name
Test status
Simulation time 2062699278 ps
CPU time 4.68 seconds
Started Jul 15 06:06:42 PM PDT 24
Finished Jul 15 06:06:47 PM PDT 24
Peak memory 201488 kb
Host smart-25c0049a-ea67-4c2d-9868-d7659d617ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632481986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2632481986
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3622687313
Short name T884
Test name
Test status
Simulation time 1099814355 ps
CPU time 2.51 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 217700 kb
Host smart-f3158c75-b683-4353-8805-7102aa388b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622687313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3622687313
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.186852939
Short name T912
Test name
Test status
Simulation time 8278902765 ps
CPU time 22.23 seconds
Started Jul 15 06:06:42 PM PDT 24
Finished Jul 15 06:07:05 PM PDT 24
Peak memory 201812 kb
Host smart-73b6a205-b3ff-4a8d-9f1f-7a017d1fb30c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186852939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.186852939
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.553682339
Short name T114
Test name
Test status
Simulation time 785668379 ps
CPU time 4.46 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:21 PM PDT 24
Peak memory 201660 kb
Host smart-8e74bd01-3781-4391-b7dc-c4acf13516b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553682339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.553682339
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4119550249
Short name T906
Test name
Test status
Simulation time 26507325595 ps
CPU time 131.36 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:08:25 PM PDT 24
Peak memory 201824 kb
Host smart-ae608a38-018f-40a6-8e09-fdbcbbbf8c26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119550249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4119550249
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3498853566
Short name T889
Test name
Test status
Simulation time 1285859188 ps
CPU time 1.52 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201496 kb
Host smart-c0f9cb69-8226-4a2c-b2cf-a3bd115a410d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498853566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3498853566
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2128687012
Short name T832
Test name
Test status
Simulation time 654476635 ps
CPU time 1.42 seconds
Started Jul 15 06:06:13 PM PDT 24
Finished Jul 15 06:06:15 PM PDT 24
Peak memory 201592 kb
Host smart-4db7026a-e601-46ce-af2e-1086d3a78501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128687012 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2128687012
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1188598358
Short name T890
Test name
Test status
Simulation time 460583421 ps
CPU time 0.93 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:16 PM PDT 24
Peak memory 201448 kb
Host smart-e9ff7a64-c74a-4664-b811-45c0742718a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188598358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1188598358
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1014671098
Short name T866
Test name
Test status
Simulation time 326802850 ps
CPU time 1 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:15 PM PDT 24
Peak memory 201404 kb
Host smart-09fe8f3b-2f15-4d8b-8b14-1411c9e47039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014671098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1014671098
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.845387767
Short name T892
Test name
Test status
Simulation time 4797803966 ps
CPU time 14.6 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:06:31 PM PDT 24
Peak memory 201836 kb
Host smart-43581951-e1c2-4d41-a563-4d7cfbbe9684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845387767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.845387767
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2537076266
Short name T839
Test name
Test status
Simulation time 342760197 ps
CPU time 2 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:17 PM PDT 24
Peak memory 201748 kb
Host smart-03e7ee3d-5462-43ff-b607-952d70226811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537076266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2537076266
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2828677149
Short name T76
Test name
Test status
Simulation time 10010221868 ps
CPU time 3.65 seconds
Started Jul 15 06:06:17 PM PDT 24
Finished Jul 15 06:06:22 PM PDT 24
Peak memory 201836 kb
Host smart-b890fd43-99b9-43fa-8486-8b3b0be57639
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828677149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2828677149
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2596958920
Short name T803
Test name
Test status
Simulation time 429998719 ps
CPU time 1.14 seconds
Started Jul 15 06:06:41 PM PDT 24
Finished Jul 15 06:06:43 PM PDT 24
Peak memory 201400 kb
Host smart-1cfa2288-1dfc-4f10-9c81-e9e9b1091ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596958920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2596958920
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1260318646
Short name T799
Test name
Test status
Simulation time 506792160 ps
CPU time 0.99 seconds
Started Jul 15 06:06:39 PM PDT 24
Finished Jul 15 06:06:41 PM PDT 24
Peak memory 201420 kb
Host smart-584895aa-a586-4747-9ccb-e6a2bc85d184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260318646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1260318646
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.529764245
Short name T807
Test name
Test status
Simulation time 525232187 ps
CPU time 0.84 seconds
Started Jul 15 06:06:52 PM PDT 24
Finished Jul 15 06:06:53 PM PDT 24
Peak memory 201372 kb
Host smart-d7783702-eb63-4cb0-8569-af24ff1ce23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529764245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.529764245
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1890166866
Short name T893
Test name
Test status
Simulation time 457763037 ps
CPU time 1.72 seconds
Started Jul 15 06:06:51 PM PDT 24
Finished Jul 15 06:06:54 PM PDT 24
Peak memory 201420 kb
Host smart-5d7d7461-8b1d-445d-8929-bbd5cbcbb971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890166866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1890166866
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1471486852
Short name T919
Test name
Test status
Simulation time 521386483 ps
CPU time 1.76 seconds
Started Jul 15 06:06:47 PM PDT 24
Finished Jul 15 06:06:49 PM PDT 24
Peak memory 201404 kb
Host smart-ba6daf8c-7a85-4968-86c3-5b4e610f96e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471486852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1471486852
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3180432163
Short name T842
Test name
Test status
Simulation time 413611614 ps
CPU time 0.95 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201340 kb
Host smart-3fe483b7-b176-49e4-9ed2-07e80e9fbfb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180432163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3180432163
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2598892916
Short name T854
Test name
Test status
Simulation time 458691105 ps
CPU time 1.64 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:50 PM PDT 24
Peak memory 201380 kb
Host smart-8069ba6e-5815-4d85-9fde-898b54a00b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598892916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2598892916
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3237267249
Short name T801
Test name
Test status
Simulation time 453822596 ps
CPU time 1.7 seconds
Started Jul 15 06:06:50 PM PDT 24
Finished Jul 15 06:06:53 PM PDT 24
Peak memory 201392 kb
Host smart-ff4942da-799c-4263-87ca-4f03a068da01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237267249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3237267249
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.919135942
Short name T864
Test name
Test status
Simulation time 326534594 ps
CPU time 1.38 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:52 PM PDT 24
Peak memory 201460 kb
Host smart-e2984970-c488-4030-a863-ddd8a5bcec31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919135942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.919135942
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1251001025
Short name T894
Test name
Test status
Simulation time 372138564 ps
CPU time 0.86 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:49 PM PDT 24
Peak memory 201416 kb
Host smart-e84dc531-da13-4231-aaef-ea9e9578a7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251001025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1251001025
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.776405369
Short name T104
Test name
Test status
Simulation time 1195641559 ps
CPU time 5.24 seconds
Started Jul 15 06:06:13 PM PDT 24
Finished Jul 15 06:06:19 PM PDT 24
Peak memory 201720 kb
Host smart-0e17d8e2-9188-4b55-b29f-35636bf39919
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776405369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.776405369
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.189276973
Short name T821
Test name
Test status
Simulation time 25711975848 ps
CPU time 56.54 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:07:12 PM PDT 24
Peak memory 201792 kb
Host smart-aff93a07-1507-4c4f-9956-356661d96acb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189276973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.189276973
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4150248719
Short name T833
Test name
Test status
Simulation time 570491885 ps
CPU time 1 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201472 kb
Host smart-9b5f75c4-1df2-4648-946a-ef4f3cb1dcea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150248719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4150248719
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1085322234
Short name T87
Test name
Test status
Simulation time 509334077 ps
CPU time 1.01 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201496 kb
Host smart-b8e1031a-dfe9-4ab6-b253-c3bc91ae2b86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085322234 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1085322234
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.607160413
Short name T103
Test name
Test status
Simulation time 402501419 ps
CPU time 1.8 seconds
Started Jul 15 06:06:17 PM PDT 24
Finished Jul 15 06:06:19 PM PDT 24
Peak memory 201372 kb
Host smart-b033aff8-7641-4553-b9a6-12c6a73a3c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607160413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.607160413
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2163434168
Short name T844
Test name
Test status
Simulation time 389506304 ps
CPU time 1.12 seconds
Started Jul 15 06:06:14 PM PDT 24
Finished Jul 15 06:06:16 PM PDT 24
Peak memory 201408 kb
Host smart-3d2e38ac-7082-4b60-bb0c-428d7be96835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163434168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2163434168
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.204187566
Short name T883
Test name
Test status
Simulation time 2182153533 ps
CPU time 5.46 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:23 PM PDT 24
Peak memory 201504 kb
Host smart-371a2f29-c0db-4a5b-bce1-a8b789339caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204187566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.204187566
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.965919217
Short name T69
Test name
Test status
Simulation time 713935273 ps
CPU time 1.93 seconds
Started Jul 15 06:06:13 PM PDT 24
Finished Jul 15 06:06:16 PM PDT 24
Peak memory 201732 kb
Host smart-3ab0c836-0963-47d2-ac3f-adb0a94a650d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965919217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.965919217
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3341929742
Short name T877
Test name
Test status
Simulation time 8260924762 ps
CPU time 6.91 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:32 PM PDT 24
Peak memory 201812 kb
Host smart-29017ab7-3bcd-4d67-8529-72ae8097fd58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341929742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3341929742
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1230471833
Short name T824
Test name
Test status
Simulation time 422379118 ps
CPU time 1.53 seconds
Started Jul 15 06:06:47 PM PDT 24
Finished Jul 15 06:06:49 PM PDT 24
Peak memory 201380 kb
Host smart-cc90974d-fd54-4329-9b83-6016504d0352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230471833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1230471833
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.403209127
Short name T819
Test name
Test status
Simulation time 541566951 ps
CPU time 0.95 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:07:18 PM PDT 24
Peak memory 201564 kb
Host smart-101520ea-36e8-4e7a-b0b7-c19d6e13d670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403209127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.403209127
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1402119933
Short name T886
Test name
Test status
Simulation time 470897927 ps
CPU time 1.16 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201408 kb
Host smart-d99fdeec-6a71-4c18-bca2-1ce89004935e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402119933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1402119933
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.56175883
Short name T831
Test name
Test status
Simulation time 585226831 ps
CPU time 0.75 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201476 kb
Host smart-68627b28-b023-47bf-87cf-a3d0cd9c0623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56175883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.56175883
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2818326722
Short name T879
Test name
Test status
Simulation time 405667871 ps
CPU time 0.72 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:50 PM PDT 24
Peak memory 201368 kb
Host smart-d6fc96dc-ee25-45dc-a6d0-37ff0608abcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818326722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2818326722
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1281105280
Short name T806
Test name
Test status
Simulation time 313781037 ps
CPU time 0.79 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:49 PM PDT 24
Peak memory 201400 kb
Host smart-9084ecce-fb06-455e-819a-40f4c8968bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281105280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1281105280
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1656277525
Short name T825
Test name
Test status
Simulation time 287979194 ps
CPU time 1 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201336 kb
Host smart-77067c20-66f3-4bfe-84b9-a8fa02021a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656277525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1656277525
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2251544106
Short name T809
Test name
Test status
Simulation time 312585928 ps
CPU time 0.84 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201440 kb
Host smart-f812f374-9f59-4997-b3cf-f2e630b9a1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251544106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2251544106
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3700870721
Short name T836
Test name
Test status
Simulation time 476039724 ps
CPU time 0.91 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:50 PM PDT 24
Peak memory 201360 kb
Host smart-01638afb-5fc5-48d2-8e40-17d68aff2a5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700870721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3700870721
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3843352663
Short name T856
Test name
Test status
Simulation time 440350964 ps
CPU time 0.82 seconds
Started Jul 15 06:06:47 PM PDT 24
Finished Jul 15 06:06:49 PM PDT 24
Peak memory 201436 kb
Host smart-ace08e82-be1d-41e7-8ded-28060d7c2493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843352663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3843352663
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1180995606
Short name T814
Test name
Test status
Simulation time 1482164018 ps
CPU time 3.18 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:28 PM PDT 24
Peak memory 201720 kb
Host smart-b095f38b-5447-4ed5-ab18-54676323133e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180995606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1180995606
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3239591037
Short name T805
Test name
Test status
Simulation time 52721977206 ps
CPU time 160.6 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:09:05 PM PDT 24
Peak memory 201812 kb
Host smart-bd7796a0-ea27-48ea-b214-9f40a66a1503
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239591037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3239591037
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3425329928
Short name T852
Test name
Test status
Simulation time 930221524 ps
CPU time 1.23 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:18 PM PDT 24
Peak memory 201484 kb
Host smart-7d0bd775-f4ba-4513-b057-e0171cec461d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425329928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3425329928
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3825224869
Short name T829
Test name
Test status
Simulation time 476636966 ps
CPU time 1.59 seconds
Started Jul 15 06:06:21 PM PDT 24
Finished Jul 15 06:06:24 PM PDT 24
Peak memory 201556 kb
Host smart-ae5b3ab1-4f6e-4115-81f8-0ae234d29861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825224869 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3825224869
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.158824984
Short name T818
Test name
Test status
Simulation time 449294100 ps
CPU time 1.18 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201388 kb
Host smart-eed0e235-398f-42ae-9a7e-5f1af32e904f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158824984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.158824984
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.272951748
Short name T915
Test name
Test status
Simulation time 491600009 ps
CPU time 1.78 seconds
Started Jul 15 06:06:15 PM PDT 24
Finished Jul 15 06:06:17 PM PDT 24
Peak memory 201460 kb
Host smart-c60c3943-7d81-4707-a97b-957281dcb327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272951748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.272951748
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2394494757
Short name T855
Test name
Test status
Simulation time 2429492958 ps
CPU time 3.14 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:28 PM PDT 24
Peak memory 201612 kb
Host smart-68cf487b-8abb-4deb-9c8e-680aa9b593e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394494757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2394494757
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3248555652
Short name T867
Test name
Test status
Simulation time 506795230 ps
CPU time 2.59 seconds
Started Jul 15 06:06:17 PM PDT 24
Finished Jul 15 06:06:20 PM PDT 24
Peak memory 201556 kb
Host smart-ae479c8d-51f4-4af2-ab68-f9e10830c668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248555652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3248555652
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2330813962
Short name T853
Test name
Test status
Simulation time 8543920851 ps
CPU time 12.39 seconds
Started Jul 15 06:06:16 PM PDT 24
Finished Jul 15 06:06:29 PM PDT 24
Peak memory 201800 kb
Host smart-3574eb4e-a9e4-47a2-871b-84bdd9742427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330813962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2330813962
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3737907117
Short name T911
Test name
Test status
Simulation time 528092946 ps
CPU time 1.21 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:50 PM PDT 24
Peak memory 201424 kb
Host smart-00c0d320-85ff-4ff6-91ca-18d971d10e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737907117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3737907117
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1142867023
Short name T875
Test name
Test status
Simulation time 457134141 ps
CPU time 0.92 seconds
Started Jul 15 06:06:52 PM PDT 24
Finished Jul 15 06:06:54 PM PDT 24
Peak memory 201368 kb
Host smart-6d8bd139-58c1-4bd4-989c-df401efa0a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142867023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1142867023
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2094074113
Short name T800
Test name
Test status
Simulation time 380007021 ps
CPU time 0.88 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:50 PM PDT 24
Peak memory 201440 kb
Host smart-71edd71d-6abe-4efe-8400-024f3008fa39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094074113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2094074113
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2103349385
Short name T881
Test name
Test status
Simulation time 475725736 ps
CPU time 0.91 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201384 kb
Host smart-b13e6d84-b4f1-4e02-98cc-ec7aa62234a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103349385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2103349385
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3496383620
Short name T850
Test name
Test status
Simulation time 401023760 ps
CPU time 0.9 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201400 kb
Host smart-4d1ea445-ff31-4976-befa-3162f8e9b9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496383620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3496383620
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.802542148
Short name T838
Test name
Test status
Simulation time 620810781 ps
CPU time 0.79 seconds
Started Jul 15 06:06:50 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201408 kb
Host smart-4b4155b2-dc85-405c-a519-fa3e5d6368e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802542148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.802542148
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4071917070
Short name T871
Test name
Test status
Simulation time 380550567 ps
CPU time 1.09 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201412 kb
Host smart-7caec78d-9091-4314-8e96-7a2077b9fecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071917070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4071917070
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3693804943
Short name T823
Test name
Test status
Simulation time 290431385 ps
CPU time 1.31 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:50 PM PDT 24
Peak memory 201420 kb
Host smart-eb990df9-eaa9-4252-b448-f6f3f34511bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693804943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3693804943
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.206752732
Short name T882
Test name
Test status
Simulation time 493311540 ps
CPU time 0.9 seconds
Started Jul 15 06:06:51 PM PDT 24
Finished Jul 15 06:06:52 PM PDT 24
Peak memory 201376 kb
Host smart-76520a8f-9974-4770-9134-21886c9af407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206752732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.206752732
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1917581818
Short name T826
Test name
Test status
Simulation time 448079308 ps
CPU time 1.65 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201264 kb
Host smart-a1737a75-c1c0-40d6-b281-e06703463d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917581818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1917581818
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2197099789
Short name T71
Test name
Test status
Simulation time 345828813 ps
CPU time 1.67 seconds
Started Jul 15 06:06:25 PM PDT 24
Finished Jul 15 06:06:27 PM PDT 24
Peak memory 201576 kb
Host smart-5c2a926a-9958-4e22-9fb0-b3a6547f88db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197099789 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2197099789
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2711440438
Short name T109
Test name
Test status
Simulation time 436304238 ps
CPU time 0.88 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:33 PM PDT 24
Peak memory 201508 kb
Host smart-93d02a7e-d0ca-452d-a071-36291ae951fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711440438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2711440438
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2125897719
Short name T914
Test name
Test status
Simulation time 393476067 ps
CPU time 0.84 seconds
Started Jul 15 06:06:30 PM PDT 24
Finished Jul 15 06:06:31 PM PDT 24
Peak memory 201436 kb
Host smart-2ac3722c-2a11-443d-b4cd-b55dad12c82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125897719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2125897719
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.430720343
Short name T857
Test name
Test status
Simulation time 3862702293 ps
CPU time 9.89 seconds
Started Jul 15 06:06:25 PM PDT 24
Finished Jul 15 06:06:36 PM PDT 24
Peak memory 201868 kb
Host smart-53539dd5-6875-4661-8ce9-046e4e33cf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430720343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.430720343
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3371025555
Short name T70
Test name
Test status
Simulation time 445938168 ps
CPU time 1.63 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:27 PM PDT 24
Peak memory 201692 kb
Host smart-ee97f7b5-40f9-4cde-8000-a48679c2d60b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371025555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3371025555
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.790970723
Short name T299
Test name
Test status
Simulation time 8394962619 ps
CPU time 19.45 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:44 PM PDT 24
Peak memory 201860 kb
Host smart-079eaec0-cfa9-4f04-a540-c55c34b39374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790970723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.790970723
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2349283669
Short name T62
Test name
Test status
Simulation time 554514507 ps
CPU time 1.34 seconds
Started Jul 15 06:06:22 PM PDT 24
Finished Jul 15 06:06:25 PM PDT 24
Peak memory 201548 kb
Host smart-e10f427d-6338-49d9-a045-a3ae1ea04993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349283669 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2349283669
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2721877672
Short name T118
Test name
Test status
Simulation time 395283562 ps
CPU time 1.76 seconds
Started Jul 15 06:06:22 PM PDT 24
Finished Jul 15 06:06:25 PM PDT 24
Peak memory 201444 kb
Host smart-a56234c6-f72d-4cda-adc4-afa415b443a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721877672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2721877672
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1861154223
Short name T874
Test name
Test status
Simulation time 335857939 ps
CPU time 1.33 seconds
Started Jul 15 06:06:21 PM PDT 24
Finished Jul 15 06:06:23 PM PDT 24
Peak memory 201356 kb
Host smart-36a30e1d-9d3e-4362-8b09-a79eaa647506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861154223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1861154223
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1042526792
Short name T116
Test name
Test status
Simulation time 2373987568 ps
CPU time 5.94 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:31 PM PDT 24
Peak memory 201592 kb
Host smart-b2001596-492f-4670-b97e-ef21a2170898
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042526792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1042526792
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1491116424
Short name T67
Test name
Test status
Simulation time 718962607 ps
CPU time 1.67 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201952 kb
Host smart-de4c9a51-a094-4472-8e61-56c622970fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491116424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1491116424
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2095458388
Short name T860
Test name
Test status
Simulation time 4475604051 ps
CPU time 4.53 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:30 PM PDT 24
Peak memory 201800 kb
Host smart-52a2be10-cf11-450f-93c9-08dff23774bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095458388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2095458388
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1327643209
Short name T98
Test name
Test status
Simulation time 581355945 ps
CPU time 1.4 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:25 PM PDT 24
Peak memory 201528 kb
Host smart-7790bb5f-c1ad-4c84-8d75-6f65d5222d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327643209 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1327643209
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3470047839
Short name T101
Test name
Test status
Simulation time 521320740 ps
CPU time 1.08 seconds
Started Jul 15 06:06:20 PM PDT 24
Finished Jul 15 06:06:21 PM PDT 24
Peak memory 201512 kb
Host smart-72046c74-6ae3-49d7-a8b7-36a20385e7e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470047839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3470047839
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3403307713
Short name T865
Test name
Test status
Simulation time 319646002 ps
CPU time 0.82 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201396 kb
Host smart-b47f4668-aad3-4dd0-82c7-e9a509e7e8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403307713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3403307713
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2336395845
Short name T119
Test name
Test status
Simulation time 3057488079 ps
CPU time 10.14 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201876 kb
Host smart-691f48e4-93da-40e4-b404-cc5c81ecaef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336395845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2336395845
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2344463303
Short name T859
Test name
Test status
Simulation time 372388110 ps
CPU time 2.9 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:28 PM PDT 24
Peak memory 201788 kb
Host smart-158e4e96-879c-4e27-9a55-3788d5f660fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344463303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2344463303
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.806557939
Short name T59
Test name
Test status
Simulation time 4614368546 ps
CPU time 11.5 seconds
Started Jul 15 06:06:30 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 201824 kb
Host smart-dc4e460e-ca5d-43f2-8d4a-9ea2ca0e810c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806557939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.806557939
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3868681111
Short name T843
Test name
Test status
Simulation time 555656243 ps
CPU time 1.15 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201528 kb
Host smart-fd29c35c-10d7-487e-82d4-fb16f9a1909c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868681111 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3868681111
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2528859648
Short name T120
Test name
Test status
Simulation time 387126753 ps
CPU time 1.02 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:27 PM PDT 24
Peak memory 201496 kb
Host smart-793d6977-4b2e-4d05-b64d-21b073191843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528859648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2528859648
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1094763432
Short name T808
Test name
Test status
Simulation time 379551482 ps
CPU time 0.87 seconds
Started Jul 15 06:06:22 PM PDT 24
Finished Jul 15 06:06:23 PM PDT 24
Peak memory 201392 kb
Host smart-d25b0430-c548-4e4c-b440-23ad33d1c355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094763432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1094763432
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1090407405
Short name T55
Test name
Test status
Simulation time 2572416621 ps
CPU time 2.94 seconds
Started Jul 15 06:06:21 PM PDT 24
Finished Jul 15 06:06:25 PM PDT 24
Peak memory 201552 kb
Host smart-bfb9b510-3562-46a6-8605-5c6cdfa8ae19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090407405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1090407405
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3072092629
Short name T863
Test name
Test status
Simulation time 533209460 ps
CPU time 2.04 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:27 PM PDT 24
Peak memory 201772 kb
Host smart-4c41368d-4007-471c-8665-baa90868c85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072092629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3072092629
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2059123209
Short name T895
Test name
Test status
Simulation time 8205810887 ps
CPU time 12.54 seconds
Started Jul 15 06:06:31 PM PDT 24
Finished Jul 15 06:06:44 PM PDT 24
Peak memory 201844 kb
Host smart-b1aae36a-da2a-43e9-945d-bc6d154113bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059123209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2059123209
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1014492313
Short name T876
Test name
Test status
Simulation time 559698400 ps
CPU time 2.07 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:27 PM PDT 24
Peak memory 201548 kb
Host smart-734dc80e-a648-45cc-b7a7-79a8f480f427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014492313 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1014492313
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3098048802
Short name T918
Test name
Test status
Simulation time 491129598 ps
CPU time 1.1 seconds
Started Jul 15 06:06:24 PM PDT 24
Finished Jul 15 06:06:26 PM PDT 24
Peak memory 201476 kb
Host smart-6ab3668b-d3c8-495f-9134-38babafbf84e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098048802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3098048802
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.457498883
Short name T804
Test name
Test status
Simulation time 347599797 ps
CPU time 1.44 seconds
Started Jul 15 06:06:22 PM PDT 24
Finished Jul 15 06:06:24 PM PDT 24
Peak memory 201412 kb
Host smart-1d6be642-0048-46c9-b6f5-1fcc07e8cccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457498883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.457498883
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3719216385
Short name T840
Test name
Test status
Simulation time 2208813815 ps
CPU time 5.75 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:30 PM PDT 24
Peak memory 201592 kb
Host smart-18c06396-529a-4481-bb25-b86e4bfd6a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719216385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3719216385
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4036724933
Short name T899
Test name
Test status
Simulation time 590364433 ps
CPU time 3.31 seconds
Started Jul 15 06:06:23 PM PDT 24
Finished Jul 15 06:06:28 PM PDT 24
Peak memory 201684 kb
Host smart-b8c39559-42c0-41c4-99ed-1d70a6d9010a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036724933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4036724933
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3896853451
Short name T376
Test name
Test status
Simulation time 508316275 ps
CPU time 0.88 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:06:59 PM PDT 24
Peak memory 201660 kb
Host smart-fcbc2ddf-e81b-495d-a59f-6c8dead39c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896853451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3896853451
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.594475913
Short name T204
Test name
Test status
Simulation time 535783767635 ps
CPU time 894.53 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:21:51 PM PDT 24
Peak memory 201884 kb
Host smart-4e2ba713-e36b-4f35-8246-de92b629b664
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594475913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.594475913
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1432707732
Short name T94
Test name
Test status
Simulation time 529027313346 ps
CPU time 1184.14 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 201896 kb
Host smart-11b3d0ad-f27d-43ff-ba2a-3a659b41b4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432707732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1432707732
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2959992929
Short name T350
Test name
Test status
Simulation time 158995659534 ps
CPU time 50.45 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:07:41 PM PDT 24
Peak memory 201676 kb
Host smart-3dc6e5d2-6452-4303-b676-ffa0d4bc5a24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959992929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2959992929
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2636805796
Short name T123
Test name
Test status
Simulation time 169252716885 ps
CPU time 398.07 seconds
Started Jul 15 06:06:49 PM PDT 24
Finished Jul 15 06:13:28 PM PDT 24
Peak memory 201908 kb
Host smart-e96ef0e6-5d5a-4474-bad5-fb566efe3a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636805796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2636805796
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.664202722
Short name T734
Test name
Test status
Simulation time 497327299667 ps
CPU time 1071.15 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:24:40 PM PDT 24
Peak memory 201856 kb
Host smart-471dbb73-bf6c-4639-8cc0-5c0675244d9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=664202722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.664202722
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2669218454
Short name T390
Test name
Test status
Simulation time 197541400855 ps
CPU time 452.21 seconds
Started Jul 15 06:06:54 PM PDT 24
Finished Jul 15 06:14:27 PM PDT 24
Peak memory 201844 kb
Host smart-691bfb48-1b49-4586-b29d-e6eaafad8a00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669218454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2669218454
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2815695687
Short name T404
Test name
Test status
Simulation time 105219789367 ps
CPU time 581.45 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:16:40 PM PDT 24
Peak memory 202176 kb
Host smart-fadc773e-cc97-4803-8fb8-c7d2891204bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815695687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2815695687
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2339263418
Short name T491
Test name
Test status
Simulation time 34492673009 ps
CPU time 75.67 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:08:13 PM PDT 24
Peak memory 201656 kb
Host smart-cc7a745e-d16d-47f6-b355-2241d2547414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339263418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2339263418
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2702655254
Short name T617
Test name
Test status
Simulation time 5093226539 ps
CPU time 6.48 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:07:04 PM PDT 24
Peak memory 201704 kb
Host smart-a7dc1856-339b-4d43-9700-ad0f984ebe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702655254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2702655254
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1067606385
Short name T543
Test name
Test status
Simulation time 6064609714 ps
CPU time 2.87 seconds
Started Jul 15 06:06:48 PM PDT 24
Finished Jul 15 06:06:51 PM PDT 24
Peak memory 201716 kb
Host smart-40bfb9f1-7a46-45af-97de-6529d20045c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067606385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1067606385
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2827175981
Short name T403
Test name
Test status
Simulation time 68073714664 ps
CPU time 160.07 seconds
Started Jul 15 06:07:03 PM PDT 24
Finished Jul 15 06:09:43 PM PDT 24
Peak memory 210596 kb
Host smart-3fced8f5-f950-4ce6-b5a4-374a6c7f6ec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827175981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2827175981
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2070088132
Short name T523
Test name
Test status
Simulation time 342148358 ps
CPU time 1.44 seconds
Started Jul 15 06:06:58 PM PDT 24
Finished Jul 15 06:07:00 PM PDT 24
Peak memory 201636 kb
Host smart-e164f640-73f3-4e93-b6fd-fade51ff3bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070088132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2070088132
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1648391368
Short name T718
Test name
Test status
Simulation time 182087251112 ps
CPU time 36.17 seconds
Started Jul 15 06:06:58 PM PDT 24
Finished Jul 15 06:07:35 PM PDT 24
Peak memory 201928 kb
Host smart-350dbf2b-ccf7-4c98-b828-d4b8d0b3fc5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648391368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1648391368
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.339495926
Short name T84
Test name
Test status
Simulation time 162519998170 ps
CPU time 68.78 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:08:05 PM PDT 24
Peak memory 201956 kb
Host smart-92a51b07-4918-43d5-bd70-51e815b143f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339495926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.339495926
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3672508712
Short name T294
Test name
Test status
Simulation time 491344590052 ps
CPU time 1083.2 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:25:01 PM PDT 24
Peak memory 201836 kb
Host smart-d8e198ed-b661-482a-8d2b-42c9da82c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672508712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3672508712
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1401857461
Short name T259
Test name
Test status
Simulation time 168913849490 ps
CPU time 91.17 seconds
Started Jul 15 06:06:58 PM PDT 24
Finished Jul 15 06:08:30 PM PDT 24
Peak memory 201944 kb
Host smart-43b7bc9f-0056-4632-a524-5cc9c3683e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401857461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1401857461
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.4185414054
Short name T308
Test name
Test status
Simulation time 495087795031 ps
CPU time 688.77 seconds
Started Jul 15 06:06:59 PM PDT 24
Finished Jul 15 06:18:28 PM PDT 24
Peak memory 201960 kb
Host smart-d13d28e8-e93e-41db-8a78-210a8fd573e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185414054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.4185414054
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.429376505
Short name T170
Test name
Test status
Simulation time 518826314551 ps
CPU time 280.41 seconds
Started Jul 15 06:06:59 PM PDT 24
Finished Jul 15 06:11:40 PM PDT 24
Peak memory 201892 kb
Host smart-94bf744d-88fb-4e00-87a4-6614605abc74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429376505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.429376505
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3467231075
Short name T525
Test name
Test status
Simulation time 196192281957 ps
CPU time 192.61 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:10:10 PM PDT 24
Peak memory 201896 kb
Host smart-5a7f71e9-68c5-4524-990d-46b414755cf6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467231075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3467231075
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1966758796
Short name T183
Test name
Test status
Simulation time 136239515359 ps
CPU time 669.91 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:18:06 PM PDT 24
Peak memory 202176 kb
Host smart-c1bc42ee-d69d-47d9-b53a-82eecc0aef9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966758796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1966758796
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2435800993
Short name T455
Test name
Test status
Simulation time 26136134807 ps
CPU time 12.33 seconds
Started Jul 15 06:06:53 PM PDT 24
Finished Jul 15 06:07:06 PM PDT 24
Peak memory 201700 kb
Host smart-3c659c64-ee4b-4437-ae1b-80a565cb25ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435800993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2435800993
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1632077259
Short name T776
Test name
Test status
Simulation time 4944192613 ps
CPU time 6.24 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:07:05 PM PDT 24
Peak memory 201728 kb
Host smart-026ec4dd-8013-4070-81fc-5988324f3df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632077259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1632077259
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.558266589
Short name T65
Test name
Test status
Simulation time 3937662330 ps
CPU time 3.69 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:07:01 PM PDT 24
Peak memory 217104 kb
Host smart-4dd52e6f-562f-46ac-b36a-31338d0fab5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558266589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.558266589
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1219058734
Short name T537
Test name
Test status
Simulation time 5702166131 ps
CPU time 6.72 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:07:02 PM PDT 24
Peak memory 201712 kb
Host smart-ba587517-37a0-4ad2-a271-c71eb649a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219058734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1219058734
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1484812157
Short name T434
Test name
Test status
Simulation time 536956762 ps
CPU time 0.91 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:07:23 PM PDT 24
Peak memory 201632 kb
Host smart-cb0f4a16-652e-44ce-aeab-f7fc356f3c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484812157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1484812157
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4067825294
Short name T277
Test name
Test status
Simulation time 517461033511 ps
CPU time 576.93 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:17:00 PM PDT 24
Peak memory 201984 kb
Host smart-4e84c9bb-52b8-430d-9ac8-b844b4bf54ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067825294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4067825294
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3372534432
Short name T655
Test name
Test status
Simulation time 163029253491 ps
CPU time 157.04 seconds
Started Jul 15 06:07:27 PM PDT 24
Finished Jul 15 06:10:04 PM PDT 24
Peak memory 201880 kb
Host smart-936993cb-9b3e-456f-bac8-fd2bec7748f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372534432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3372534432
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.59013860
Short name T124
Test name
Test status
Simulation time 501401396263 ps
CPU time 566.03 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:16:50 PM PDT 24
Peak memory 201860 kb
Host smart-5760c1dc-96dc-476a-b4e8-4a9edf5fbb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59013860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.59013860
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2898377950
Short name T417
Test name
Test status
Simulation time 163713508331 ps
CPU time 95.53 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:08:58 PM PDT 24
Peak memory 201908 kb
Host smart-445728a0-91dc-482d-88d7-1d6ef73b9284
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898377950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2898377950
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1555465399
Short name T218
Test name
Test status
Simulation time 360648935736 ps
CPU time 198.97 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:10:44 PM PDT 24
Peak memory 201936 kb
Host smart-04ac38c4-e441-4476-a2fd-08eeb79b9d2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555465399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1555465399
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.900330881
Short name T572
Test name
Test status
Simulation time 581745871899 ps
CPU time 417.92 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:14:22 PM PDT 24
Peak memory 201884 kb
Host smart-e35ebed1-5707-4de4-a95b-6e615166024d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900330881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.900330881
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1913363417
Short name T506
Test name
Test status
Simulation time 81276085602 ps
CPU time 367.72 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:13:31 PM PDT 24
Peak memory 202216 kb
Host smart-e9d0ca9b-00e9-42d3-9bf7-a6ceff5c94a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913363417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1913363417
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1678911469
Short name T377
Test name
Test status
Simulation time 37434065784 ps
CPU time 83.34 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:08:45 PM PDT 24
Peak memory 201716 kb
Host smart-29601724-45de-4fba-8d2f-927bdbe99ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678911469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1678911469
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2902497872
Short name T513
Test name
Test status
Simulation time 3692490735 ps
CPU time 2.78 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:07:27 PM PDT 24
Peak memory 201736 kb
Host smart-4fde746e-6abf-41d7-a1e9-a549d7d67e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902497872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2902497872
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.95723175
Short name T441
Test name
Test status
Simulation time 5963366655 ps
CPU time 6.74 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:07:30 PM PDT 24
Peak memory 201704 kb
Host smart-295bbc64-3a1d-43ce-bf0d-640e5d7dee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95723175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.95723175
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1056454034
Short name T270
Test name
Test status
Simulation time 517475082644 ps
CPU time 1175.7 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:27:01 PM PDT 24
Peak memory 201932 kb
Host smart-26391964-d8ee-4e78-8a68-0405c5286f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056454034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1056454034
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2710406465
Short name T524
Test name
Test status
Simulation time 31406672111 ps
CPU time 37.25 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:08:00 PM PDT 24
Peak memory 210264 kb
Host smart-6eca039a-0fd9-4db3-a167-65358d544f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710406465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2710406465
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1274906938
Short name T489
Test name
Test status
Simulation time 629901560 ps
CPU time 0.81 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:07:25 PM PDT 24
Peak memory 201592 kb
Host smart-f94472f7-58e8-41d9-8291-468042eb067b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274906938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1274906938
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2202439557
Short name T250
Test name
Test status
Simulation time 489017291936 ps
CPU time 564.93 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:16:49 PM PDT 24
Peak memory 201884 kb
Host smart-38451c37-c8a3-46e1-a628-a50a39982f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202439557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2202439557
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1747909910
Short name T421
Test name
Test status
Simulation time 324985064144 ps
CPU time 679.23 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:18:44 PM PDT 24
Peak memory 201900 kb
Host smart-5b8da2b6-599d-4a2e-87ea-2add2b2ef453
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747909910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1747909910
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2675110004
Short name T691
Test name
Test status
Simulation time 159233209126 ps
CPU time 184.27 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:10:26 PM PDT 24
Peak memory 201904 kb
Host smart-b5bd7041-d2ec-4a86-8d58-66c50d22d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675110004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2675110004
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1132001912
Short name T439
Test name
Test status
Simulation time 322455310649 ps
CPU time 62.93 seconds
Started Jul 15 06:07:23 PM PDT 24
Finished Jul 15 06:08:27 PM PDT 24
Peak memory 201860 kb
Host smart-bdef606f-6e08-4657-9e5e-01add6590d09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132001912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1132001912
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.884660540
Short name T217
Test name
Test status
Simulation time 358668351866 ps
CPU time 423.02 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 201884 kb
Host smart-44382902-d956-4371-b6db-82890b062065
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884660540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.884660540
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1421752181
Short name T520
Test name
Test status
Simulation time 191008264952 ps
CPU time 413.71 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:14:16 PM PDT 24
Peak memory 201884 kb
Host smart-be29fae1-af28-4340-bd34-eb8ddcd0d650
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421752181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1421752181
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3226582454
Short name T559
Test name
Test status
Simulation time 132284164270 ps
CPU time 459.07 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:15:08 PM PDT 24
Peak memory 202192 kb
Host smart-0bc3a068-abed-4b2d-9188-d4ee46c54866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226582454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3226582454
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3929055783
Short name T754
Test name
Test status
Simulation time 30901512013 ps
CPU time 18.04 seconds
Started Jul 15 06:07:25 PM PDT 24
Finished Jul 15 06:07:43 PM PDT 24
Peak memory 201680 kb
Host smart-6c4eb285-9fdc-45e2-94cb-11ab5af77fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929055783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3929055783
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4204530045
Short name T795
Test name
Test status
Simulation time 3134451264 ps
CPU time 2.41 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:07:24 PM PDT 24
Peak memory 201716 kb
Host smart-bf620473-537a-4c58-938c-2e859f487c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204530045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4204530045
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3446454846
Short name T744
Test name
Test status
Simulation time 5913966591 ps
CPU time 8.29 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:07:30 PM PDT 24
Peak memory 201752 kb
Host smart-0d7d7934-f82c-4956-a030-11dba31181d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446454846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3446454846
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3999345416
Short name T82
Test name
Test status
Simulation time 407090547411 ps
CPU time 180.14 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:10:29 PM PDT 24
Peak memory 201892 kb
Host smart-9d431386-a851-45f1-a640-c8ef6ad16965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999345416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3999345416
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.78544254
Short name T575
Test name
Test status
Simulation time 544152948 ps
CPU time 0.78 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:07:31 PM PDT 24
Peak memory 201652 kb
Host smart-db021410-9f83-4f01-a8e8-f1afdd3f45c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78544254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.78544254
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1452100700
Short name T728
Test name
Test status
Simulation time 534205123755 ps
CPU time 1132.82 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:26:24 PM PDT 24
Peak memory 201856 kb
Host smart-e248ca69-0997-4de6-8709-9b0e060038a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452100700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1452100700
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.820768284
Short name T295
Test name
Test status
Simulation time 158474532120 ps
CPU time 354.66 seconds
Started Jul 15 06:07:27 PM PDT 24
Finished Jul 15 06:13:23 PM PDT 24
Peak memory 201900 kb
Host smart-74a3f449-fced-4016-9dc4-6d3dd85537aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820768284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.820768284
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.378453507
Short name T593
Test name
Test status
Simulation time 497081548948 ps
CPU time 324.36 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:12:48 PM PDT 24
Peak memory 201888 kb
Host smart-331a5a8d-7330-4c49-b45c-4d8d7acf36aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=378453507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.378453507
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1454360799
Short name T416
Test name
Test status
Simulation time 324937774594 ps
CPU time 710.24 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:19:15 PM PDT 24
Peak memory 201948 kb
Host smart-71773250-eacb-45ec-a6b3-ce1e48ff4f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454360799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1454360799
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.541673651
Short name T173
Test name
Test status
Simulation time 500260565134 ps
CPU time 159.86 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:10:05 PM PDT 24
Peak memory 201868 kb
Host smart-2e5a7dda-78bb-4ada-94df-4a060d4e3565
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=541673651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.541673651
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2733628031
Short name T784
Test name
Test status
Simulation time 358394556394 ps
CPU time 812.3 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:21:05 PM PDT 24
Peak memory 201964 kb
Host smart-7a866a12-8d62-4550-a427-babeec7a2272
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733628031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2733628031
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4090744992
Short name T451
Test name
Test status
Simulation time 402378256432 ps
CPU time 886.77 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:22:18 PM PDT 24
Peak memory 201892 kb
Host smart-7c540e6d-6577-47d6-8d25-42a0db022344
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090744992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4090744992
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.895655249
Short name T186
Test name
Test status
Simulation time 76277417228 ps
CPU time 271.5 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:12:03 PM PDT 24
Peak memory 202216 kb
Host smart-26d9ac25-ced8-41ed-a7a4-8d3e048ad40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895655249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.895655249
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1955341679
Short name T529
Test name
Test status
Simulation time 32516708241 ps
CPU time 69.87 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:08:42 PM PDT 24
Peak memory 201736 kb
Host smart-e96c8c39-368a-4cef-b5fd-533f99d80ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955341679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1955341679
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3507048283
Short name T477
Test name
Test status
Simulation time 3752445016 ps
CPU time 3.01 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:07:37 PM PDT 24
Peak memory 201692 kb
Host smart-4dcbe72a-adfe-4b7f-b0f9-f208f1c57c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507048283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3507048283
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.115800405
Short name T23
Test name
Test status
Simulation time 5682029989 ps
CPU time 12.75 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:07:41 PM PDT 24
Peak memory 201716 kb
Host smart-e0090f3d-736a-48dc-bdb2-50347f66b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115800405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.115800405
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3908234813
Short name T182
Test name
Test status
Simulation time 338785833333 ps
CPU time 519.63 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:16:10 PM PDT 24
Peak memory 210436 kb
Host smart-efa55e0e-ba37-4c53-b0c1-784bbf7e9463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908234813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3908234813
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.145277260
Short name T245
Test name
Test status
Simulation time 74119931458 ps
CPU time 127.9 seconds
Started Jul 15 06:07:34 PM PDT 24
Finished Jul 15 06:09:43 PM PDT 24
Peak memory 218188 kb
Host smart-4e6d5b4e-c367-4fe0-8f9d-ba165664a285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145277260 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.145277260
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2159492506
Short name T452
Test name
Test status
Simulation time 489513084 ps
CPU time 1.02 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:07:34 PM PDT 24
Peak memory 201584 kb
Host smart-e30238fd-e70c-4128-bb0d-466f28450509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159492506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2159492506
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3848122852
Short name T561
Test name
Test status
Simulation time 497445222502 ps
CPU time 1172.01 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:27:01 PM PDT 24
Peak memory 201880 kb
Host smart-6432dd43-bb89-448f-9c60-43a8a8522f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848122852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3848122852
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3688878938
Short name T515
Test name
Test status
Simulation time 491122194067 ps
CPU time 400.85 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:14:15 PM PDT 24
Peak memory 201868 kb
Host smart-e449456c-2438-4658-8f13-8c1d413579f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688878938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3688878938
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2164658367
Short name T134
Test name
Test status
Simulation time 334454658570 ps
CPU time 748.54 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:20:03 PM PDT 24
Peak memory 201912 kb
Host smart-dafae6fd-c77c-41dd-947a-122df77c7006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164658367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2164658367
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2513138100
Short name T504
Test name
Test status
Simulation time 327898651483 ps
CPU time 118.43 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:09:27 PM PDT 24
Peak memory 201880 kb
Host smart-11ed3698-dcec-4326-9d81-1dfc735a826c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513138100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2513138100
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2151742570
Short name T127
Test name
Test status
Simulation time 365986962045 ps
CPU time 91.86 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:09:06 PM PDT 24
Peak memory 201948 kb
Host smart-d36641be-b7b3-4407-93b5-1bffff920716
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151742570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2151742570
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2537355040
Short name T326
Test name
Test status
Simulation time 202251951907 ps
CPU time 120.24 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:09:30 PM PDT 24
Peak memory 201792 kb
Host smart-49416100-bd1f-439f-90d7-ed05b6069ec6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537355040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2537355040
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.730640705
Short name T681
Test name
Test status
Simulation time 82768991991 ps
CPU time 289.43 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:12:23 PM PDT 24
Peak memory 202224 kb
Host smart-f9d8d41f-4c34-415f-b8c9-21fd768c919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730640705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.730640705
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2046969989
Short name T601
Test name
Test status
Simulation time 30753757468 ps
CPU time 67.03 seconds
Started Jul 15 06:07:34 PM PDT 24
Finished Jul 15 06:08:42 PM PDT 24
Peak memory 201672 kb
Host smart-3246aee5-f2a4-4866-9102-82a87d6abcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046969989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2046969989
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.805934529
Short name T779
Test name
Test status
Simulation time 4697925639 ps
CPU time 6.21 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:07:39 PM PDT 24
Peak memory 201660 kb
Host smart-ecb73f1d-f6d4-4a43-9e84-fa24ea1620b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805934529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.805934529
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.791274587
Short name T511
Test name
Test status
Simulation time 5762470962 ps
CPU time 14.01 seconds
Started Jul 15 06:07:34 PM PDT 24
Finished Jul 15 06:07:48 PM PDT 24
Peak memory 201716 kb
Host smart-322a5f58-ad16-4d42-a349-b089e79ec39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791274587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.791274587
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4005524017
Short name T222
Test name
Test status
Simulation time 724567169825 ps
CPU time 1201.91 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:27:35 PM PDT 24
Peak memory 201784 kb
Host smart-037d5ed0-16b2-44e2-a544-765da4439e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005524017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4005524017
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1248893863
Short name T38
Test name
Test status
Simulation time 18502048424 ps
CPU time 41.45 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:08:12 PM PDT 24
Peak memory 202020 kb
Host smart-961bb31f-403d-41b7-9bba-dce87c707777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248893863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1248893863
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2574485617
Short name T425
Test name
Test status
Simulation time 422254135 ps
CPU time 1.54 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:07:34 PM PDT 24
Peak memory 201656 kb
Host smart-f6951491-2b75-4eb8-8e97-57e61910d3b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574485617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2574485617
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1317480415
Short name T212
Test name
Test status
Simulation time 161764091077 ps
CPU time 177.66 seconds
Started Jul 15 06:07:33 PM PDT 24
Finished Jul 15 06:10:32 PM PDT 24
Peak memory 201920 kb
Host smart-36f30740-dd07-41e4-99e0-5403e18ff727
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317480415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1317480415
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.991201518
Short name T133
Test name
Test status
Simulation time 169113135818 ps
CPU time 193.84 seconds
Started Jul 15 06:07:27 PM PDT 24
Finished Jul 15 06:10:41 PM PDT 24
Peak memory 201748 kb
Host smart-66801275-5eba-4aa6-900b-e76919dde144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991201518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.991201518
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.164296668
Short name T565
Test name
Test status
Simulation time 495276914563 ps
CPU time 375.43 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:13:45 PM PDT 24
Peak memory 201880 kb
Host smart-38219d98-6ee3-470e-ac8b-4c2e6b7497f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164296668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.164296668
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1651364496
Short name T95
Test name
Test status
Simulation time 497856832479 ps
CPU time 301.02 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:12:30 PM PDT 24
Peak memory 201804 kb
Host smart-da2f2d03-5b4e-4658-ab8a-201342d04aa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651364496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1651364496
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.4170006269
Short name T709
Test name
Test status
Simulation time 328421080146 ps
CPU time 102.79 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:09:14 PM PDT 24
Peak memory 201920 kb
Host smart-744fba7d-ba51-409b-9280-79bb398a3408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170006269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4170006269
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3189608757
Short name T540
Test name
Test status
Simulation time 491345843440 ps
CPU time 187.72 seconds
Started Jul 15 06:07:32 PM PDT 24
Finished Jul 15 06:10:41 PM PDT 24
Peak memory 201884 kb
Host smart-9fe08497-b59b-4d10-84db-99325ebf7c28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189608757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3189608757
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2645748917
Short name T770
Test name
Test status
Simulation time 356019569773 ps
CPU time 204.37 seconds
Started Jul 15 06:07:34 PM PDT 24
Finished Jul 15 06:11:00 PM PDT 24
Peak memory 201872 kb
Host smart-5eee5655-812b-49f5-b5e0-e65e9ffaa3f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645748917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2645748917
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.100742177
Short name T331
Test name
Test status
Simulation time 210025640199 ps
CPU time 118.65 seconds
Started Jul 15 06:07:31 PM PDT 24
Finished Jul 15 06:09:30 PM PDT 24
Peak memory 201872 kb
Host smart-b7cf71c4-9cce-413e-ad5a-ab85e20f1ba3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100742177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.100742177
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3005810268
Short name T710
Test name
Test status
Simulation time 73304849722 ps
CPU time 332.96 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:13:04 PM PDT 24
Peak memory 202216 kb
Host smart-78fb5b09-30a4-432b-86af-0c0b8821a69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005810268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3005810268
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2447042157
Short name T407
Test name
Test status
Simulation time 36162383145 ps
CPU time 84.93 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:08:56 PM PDT 24
Peak memory 201688 kb
Host smart-29a48e60-4bcc-4de2-9066-1a93c85e8b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447042157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2447042157
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1526027295
Short name T400
Test name
Test status
Simulation time 5779159733 ps
CPU time 14.24 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:07:45 PM PDT 24
Peak memory 201640 kb
Host smart-a78a671e-9dc0-4734-aa2a-2bcabd851621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526027295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1526027295
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.236964875
Short name T343
Test name
Test status
Simulation time 6100403183 ps
CPU time 4.03 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:07:33 PM PDT 24
Peak memory 201712 kb
Host smart-8e37641c-022d-41f5-8783-bddbdf03d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236964875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.236964875
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3079348432
Short name T468
Test name
Test status
Simulation time 92299288136 ps
CPU time 300.11 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:12:32 PM PDT 24
Peak memory 218676 kb
Host smart-cd7a52ab-d30e-4fc8-b918-7d787e251f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079348432 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3079348432
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1701486899
Short name T732
Test name
Test status
Simulation time 295315401 ps
CPU time 1.3 seconds
Started Jul 15 06:07:37 PM PDT 24
Finished Jul 15 06:07:39 PM PDT 24
Peak memory 201664 kb
Host smart-467c2b19-4a9d-4a90-afd5-d500955fa538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701486899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1701486899
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1339819027
Short name T666
Test name
Test status
Simulation time 324271278053 ps
CPU time 610.85 seconds
Started Jul 15 06:07:40 PM PDT 24
Finished Jul 15 06:17:51 PM PDT 24
Peak memory 201844 kb
Host smart-44bf57ac-bd3b-46bb-9b61-e532c3ef7e12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339819027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1339819027
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1124554600
Short name T92
Test name
Test status
Simulation time 187018959306 ps
CPU time 393.96 seconds
Started Jul 15 06:07:42 PM PDT 24
Finished Jul 15 06:14:16 PM PDT 24
Peak memory 201916 kb
Host smart-d0aa502e-059c-463a-9833-96eca788496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124554600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1124554600
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1992508164
Short name T93
Test name
Test status
Simulation time 495137409739 ps
CPU time 1141.83 seconds
Started Jul 15 06:07:31 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 201904 kb
Host smart-d77430fa-06aa-46f1-ba26-39e59df9a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992508164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1992508164
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1555489351
Short name T309
Test name
Test status
Simulation time 165790081072 ps
CPU time 382.17 seconds
Started Jul 15 06:07:38 PM PDT 24
Finished Jul 15 06:14:01 PM PDT 24
Peak memory 201868 kb
Host smart-9dff716e-e128-47f2-bd97-1a8ae2f7d38b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555489351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1555489351
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2866152074
Short name T10
Test name
Test status
Simulation time 326123813809 ps
CPU time 735.93 seconds
Started Jul 15 06:07:29 PM PDT 24
Finished Jul 15 06:19:46 PM PDT 24
Peak memory 201936 kb
Host smart-8b3f71de-c999-4855-bc21-f9263b3c5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866152074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2866152074
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2904951335
Short name T743
Test name
Test status
Simulation time 158365583247 ps
CPU time 368.44 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:13:39 PM PDT 24
Peak memory 201868 kb
Host smart-8706db5e-5dc1-4967-8e6e-3d210e6fb870
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904951335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2904951335
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2732050921
Short name T706
Test name
Test status
Simulation time 356339107395 ps
CPU time 390.94 seconds
Started Jul 15 06:07:39 PM PDT 24
Finished Jul 15 06:14:10 PM PDT 24
Peak memory 201888 kb
Host smart-942b0980-cb73-41a2-bde5-1772cee6ef6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732050921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2732050921
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1982673071
Short name T588
Test name
Test status
Simulation time 194944361700 ps
CPU time 202.34 seconds
Started Jul 15 06:07:35 PM PDT 24
Finished Jul 15 06:10:58 PM PDT 24
Peak memory 201856 kb
Host smart-b35c7aa5-2ece-4cd6-be0f-db8489dcee2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982673071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1982673071
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.414029041
Short name T701
Test name
Test status
Simulation time 83394246224 ps
CPU time 475.4 seconds
Started Jul 15 06:07:38 PM PDT 24
Finished Jul 15 06:15:34 PM PDT 24
Peak memory 202296 kb
Host smart-798a3871-7e23-421e-94d3-87260be43745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414029041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.414029041
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2751218073
Short name T501
Test name
Test status
Simulation time 45574765388 ps
CPU time 6.09 seconds
Started Jul 15 06:07:36 PM PDT 24
Finished Jul 15 06:07:42 PM PDT 24
Peak memory 201688 kb
Host smart-28fa972f-bfd0-4d22-a1d9-ae40c26ab45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751218073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2751218073
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1066644154
Short name T465
Test name
Test status
Simulation time 3151699932 ps
CPU time 7.06 seconds
Started Jul 15 06:07:37 PM PDT 24
Finished Jul 15 06:07:44 PM PDT 24
Peak memory 201620 kb
Host smart-5d4b7544-b0fd-4f33-90fd-254884385f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066644154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1066644154
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1598824097
Short name T482
Test name
Test status
Simulation time 5863567524 ps
CPU time 6.89 seconds
Started Jul 15 06:07:30 PM PDT 24
Finished Jul 15 06:07:38 PM PDT 24
Peak memory 201680 kb
Host smart-769c9520-d496-42b1-beee-3997833ea811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598824097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1598824097
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3175202670
Short name T209
Test name
Test status
Simulation time 330936130653 ps
CPU time 701.24 seconds
Started Jul 15 06:07:43 PM PDT 24
Finished Jul 15 06:19:25 PM PDT 24
Peak memory 201800 kb
Host smart-f4e198be-935a-4100-8d34-67343221f64d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175202670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3175202670
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2074366486
Short name T96
Test name
Test status
Simulation time 558225789 ps
CPU time 0.72 seconds
Started Jul 15 06:07:48 PM PDT 24
Finished Jul 15 06:07:49 PM PDT 24
Peak memory 201644 kb
Host smart-3fd2574f-2eb6-422a-82be-966c95a8269a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074366486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2074366486
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.822326630
Short name T264
Test name
Test status
Simulation time 363854120872 ps
CPU time 795.54 seconds
Started Jul 15 06:07:43 PM PDT 24
Finished Jul 15 06:20:59 PM PDT 24
Peak memory 201792 kb
Host smart-98e78737-d0c3-4d8f-be1a-78b1dd3552ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822326630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.822326630
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1543493382
Short name T261
Test name
Test status
Simulation time 484386491987 ps
CPU time 594.51 seconds
Started Jul 15 06:07:36 PM PDT 24
Finished Jul 15 06:17:31 PM PDT 24
Peak memory 201880 kb
Host smart-a3fc16c7-b758-467d-aa72-3039a922a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543493382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1543493382
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1246844734
Short name T457
Test name
Test status
Simulation time 333281203469 ps
CPU time 211.15 seconds
Started Jul 15 06:07:36 PM PDT 24
Finished Jul 15 06:11:08 PM PDT 24
Peak memory 201844 kb
Host smart-c9f1d36d-5e35-4633-bf71-cb9020fe408a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246844734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1246844734
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2934770338
Short name T389
Test name
Test status
Simulation time 163687350777 ps
CPU time 97.25 seconds
Started Jul 15 06:07:38 PM PDT 24
Finished Jul 15 06:09:16 PM PDT 24
Peak memory 201940 kb
Host smart-98aa9749-4667-43a4-bff5-c4b24425355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934770338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2934770338
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2479753612
Short name T649
Test name
Test status
Simulation time 489026298808 ps
CPU time 1065.39 seconds
Started Jul 15 06:07:40 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 201928 kb
Host smart-9c9a610b-2e29-4c4b-b426-cff469e90ea1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479753612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2479753612
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3967550771
Short name T571
Test name
Test status
Simulation time 391792345705 ps
CPU time 437.5 seconds
Started Jul 15 06:07:38 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 201864 kb
Host smart-315c814f-44a4-4566-a787-e347dc4af370
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967550771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3967550771
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2192496959
Short name T467
Test name
Test status
Simulation time 128550733902 ps
CPU time 502.02 seconds
Started Jul 15 06:07:45 PM PDT 24
Finished Jul 15 06:16:07 PM PDT 24
Peak memory 202240 kb
Host smart-362252e5-2d41-4cc7-a88b-42ba183ef158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192496959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2192496959
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1669582582
Short name T567
Test name
Test status
Simulation time 27471015314 ps
CPU time 62.72 seconds
Started Jul 15 06:07:40 PM PDT 24
Finished Jul 15 06:08:43 PM PDT 24
Peak memory 201740 kb
Host smart-4fe925ec-f7ee-4264-b093-c587ee4242da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669582582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1669582582
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1765161507
Short name T608
Test name
Test status
Simulation time 3050028991 ps
CPU time 4.17 seconds
Started Jul 15 06:07:37 PM PDT 24
Finished Jul 15 06:07:42 PM PDT 24
Peak memory 201688 kb
Host smart-f9116c02-a097-4712-8be3-907b1428d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765161507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1765161507
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3312774172
Short name T483
Test name
Test status
Simulation time 5699477530 ps
CPU time 7.04 seconds
Started Jul 15 06:07:37 PM PDT 24
Finished Jul 15 06:07:45 PM PDT 24
Peak memory 201708 kb
Host smart-a410e529-47d8-4828-85c3-2ce0dde41432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312774172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3312774172
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.768975262
Short name T760
Test name
Test status
Simulation time 24842954350 ps
CPU time 47.64 seconds
Started Jul 15 06:07:49 PM PDT 24
Finished Jul 15 06:08:37 PM PDT 24
Peak memory 210512 kb
Host smart-36003a8c-4800-4c68-8c41-16e5b03b6d36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768975262 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.768975262
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.115326306
Short name T438
Test name
Test status
Simulation time 334601889 ps
CPU time 1.33 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:07:56 PM PDT 24
Peak memory 201612 kb
Host smart-c90a7fec-2da5-4c42-a24b-7b4a0d34436f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115326306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.115326306
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4056773361
Short name T643
Test name
Test status
Simulation time 671753825824 ps
CPU time 364.38 seconds
Started Jul 15 06:07:48 PM PDT 24
Finished Jul 15 06:13:53 PM PDT 24
Peak memory 201888 kb
Host smart-05f1cf62-5908-4b30-9d3e-ec1ad72dddef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056773361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4056773361
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1117648399
Short name T774
Test name
Test status
Simulation time 345468643465 ps
CPU time 380.55 seconds
Started Jul 15 06:07:45 PM PDT 24
Finished Jul 15 06:14:06 PM PDT 24
Peak memory 201912 kb
Host smart-656220a5-06f1-4c1f-9a3c-2599401e682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117648399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1117648399
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2731794742
Short name T700
Test name
Test status
Simulation time 491205830676 ps
CPU time 305.21 seconds
Started Jul 15 06:07:47 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 201908 kb
Host smart-c9d2d8af-cb13-4627-91a2-c64f552e6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731794742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2731794742
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.263494217
Short name T798
Test name
Test status
Simulation time 499715406824 ps
CPU time 530.38 seconds
Started Jul 15 06:07:45 PM PDT 24
Finished Jul 15 06:16:36 PM PDT 24
Peak memory 201852 kb
Host smart-c3ef04a7-6274-4a8d-822a-227caf002414
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=263494217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.263494217
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.768109817
Short name T590
Test name
Test status
Simulation time 166912921522 ps
CPU time 182 seconds
Started Jul 15 06:07:44 PM PDT 24
Finished Jul 15 06:10:47 PM PDT 24
Peak memory 201856 kb
Host smart-a9bd44cb-3c48-4894-bee2-d8098d555d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768109817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.768109817
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.179116020
Short name T171
Test name
Test status
Simulation time 325191780039 ps
CPU time 698.3 seconds
Started Jul 15 06:07:43 PM PDT 24
Finished Jul 15 06:19:22 PM PDT 24
Peak memory 201916 kb
Host smart-e9c36c0d-d358-4e14-b0a0-3ac2ca22a05c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=179116020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.179116020
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3265132183
Short name T135
Test name
Test status
Simulation time 168209907471 ps
CPU time 104.1 seconds
Started Jul 15 06:07:45 PM PDT 24
Finished Jul 15 06:09:30 PM PDT 24
Peak memory 201916 kb
Host smart-15b47d72-0f1a-4229-857b-66a1777c110a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265132183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3265132183
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.979678043
Short name T234
Test name
Test status
Simulation time 198099835339 ps
CPU time 107.92 seconds
Started Jul 15 06:07:43 PM PDT 24
Finished Jul 15 06:09:32 PM PDT 24
Peak memory 201836 kb
Host smart-96c3a354-3802-48f9-9521-86f70ed0dd29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979678043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.979678043
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2688870606
Short name T746
Test name
Test status
Simulation time 108709894414 ps
CPU time 322.85 seconds
Started Jul 15 06:07:47 PM PDT 24
Finished Jul 15 06:13:10 PM PDT 24
Peak memory 202116 kb
Host smart-afaa9786-14a6-42d3-b4cd-cb406d0e883f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688870606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2688870606
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3282979163
Short name T729
Test name
Test status
Simulation time 25453575530 ps
CPU time 18.35 seconds
Started Jul 15 06:07:45 PM PDT 24
Finished Jul 15 06:08:04 PM PDT 24
Peak memory 201700 kb
Host smart-f9f2b43a-47a4-4ed5-a4e6-5791b1f6c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282979163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3282979163
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1155569245
Short name T679
Test name
Test status
Simulation time 4725673122 ps
CPU time 3.87 seconds
Started Jul 15 06:07:46 PM PDT 24
Finished Jul 15 06:07:50 PM PDT 24
Peak memory 201700 kb
Host smart-9603ee88-f33b-476e-a9b6-80815e1b5adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155569245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1155569245
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3377858594
Short name T683
Test name
Test status
Simulation time 5616720891 ps
CPU time 3.85 seconds
Started Jul 15 06:07:46 PM PDT 24
Finished Jul 15 06:07:50 PM PDT 24
Peak memory 201696 kb
Host smart-64727fd5-68f5-42bd-b918-0c4554e1de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377858594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3377858594
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.893846654
Short name T286
Test name
Test status
Simulation time 457204187729 ps
CPU time 269.07 seconds
Started Jul 15 06:07:58 PM PDT 24
Finished Jul 15 06:12:27 PM PDT 24
Peak memory 201940 kb
Host smart-01deb32a-0cdf-4d64-9684-60e481543d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893846654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
893846654
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2614602838
Short name T692
Test name
Test status
Simulation time 24511857122 ps
CPU time 54.37 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:08:49 PM PDT 24
Peak memory 210532 kb
Host smart-2ac61583-bb0b-423f-9e5f-14c38797b3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614602838 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2614602838
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3574680202
Short name T151
Test name
Test status
Simulation time 329541556090 ps
CPU time 107.92 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:09:42 PM PDT 24
Peak memory 201900 kb
Host smart-e30edd27-dc54-46b0-a41f-1cef8def830f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574680202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3574680202
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1948320332
Short name T197
Test name
Test status
Simulation time 540209676862 ps
CPU time 322.18 seconds
Started Jul 15 06:07:56 PM PDT 24
Finished Jul 15 06:13:18 PM PDT 24
Peak memory 201952 kb
Host smart-5ba72fc9-e2c9-40b6-ad9f-b27f399c3d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948320332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1948320332
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.121309794
Short name T131
Test name
Test status
Simulation time 333838405338 ps
CPU time 350.2 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:13:45 PM PDT 24
Peak memory 201980 kb
Host smart-3cbfbf0f-e705-4fb9-8aad-670f349329b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121309794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.121309794
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2120010060
Short name T697
Test name
Test status
Simulation time 492945492733 ps
CPU time 579.77 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:17:34 PM PDT 24
Peak memory 201856 kb
Host smart-6cc2dce4-4ab1-43e3-8005-787ebcdc8345
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120010060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2120010060
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1718740475
Short name T292
Test name
Test status
Simulation time 169513213534 ps
CPU time 153.3 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:10:27 PM PDT 24
Peak memory 201976 kb
Host smart-ab970eae-92fe-432e-ab2a-54ad2489cc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718740475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1718740475
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3585045739
Short name T634
Test name
Test status
Simulation time 489247554101 ps
CPU time 563.94 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:17:18 PM PDT 24
Peak memory 201928 kb
Host smart-3067dc33-4f7c-4a37-8ac6-603e71973b5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585045739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3585045739
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2155498103
Short name T220
Test name
Test status
Simulation time 519114918073 ps
CPU time 563.5 seconds
Started Jul 15 06:07:52 PM PDT 24
Finished Jul 15 06:17:16 PM PDT 24
Peak memory 201920 kb
Host smart-a759b8c4-6f19-4487-aef6-20d2f1533979
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155498103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2155498103
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1289321106
Short name T392
Test name
Test status
Simulation time 395506557977 ps
CPU time 900.05 seconds
Started Jul 15 06:07:52 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 201900 kb
Host smart-3e82ce71-4af6-4e77-9232-039040171e7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289321106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1289321106
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3267595681
Short name T450
Test name
Test status
Simulation time 105708001293 ps
CPU time 368.97 seconds
Started Jul 15 06:07:57 PM PDT 24
Finished Jul 15 06:14:06 PM PDT 24
Peak memory 202216 kb
Host smart-f6fcbde7-9656-43be-8205-f2044582afbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267595681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3267595681
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1363195515
Short name T705
Test name
Test status
Simulation time 36926353965 ps
CPU time 22.31 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:08:16 PM PDT 24
Peak memory 201716 kb
Host smart-50706481-134b-486b-aa67-4ce725c2a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363195515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1363195515
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2293977678
Short name T317
Test name
Test status
Simulation time 4819433417 ps
CPU time 4.96 seconds
Started Jul 15 06:07:52 PM PDT 24
Finished Jul 15 06:07:58 PM PDT 24
Peak memory 201660 kb
Host smart-8ebdade5-dc68-4730-a47f-058f5635002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293977678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2293977678
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4056664823
Short name T594
Test name
Test status
Simulation time 6126157730 ps
CPU time 12.11 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:08:05 PM PDT 24
Peak memory 201688 kb
Host smart-7bbda630-f01a-457e-9609-2cfc07f1ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056664823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4056664823
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1886540481
Short name T21
Test name
Test status
Simulation time 387994276347 ps
CPU time 141.74 seconds
Started Jul 15 06:07:52 PM PDT 24
Finished Jul 15 06:10:14 PM PDT 24
Peak memory 210544 kb
Host smart-bb2c9bf3-ef4a-4bc0-9374-bf6d5653f68f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886540481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1886540481
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.737897259
Short name T12
Test name
Test status
Simulation time 392776330 ps
CPU time 1.06 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:08:05 PM PDT 24
Peak memory 201616 kb
Host smart-12b02c01-6557-45b3-aa11-fc830780b873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737897259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.737897259
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3206772239
Short name T447
Test name
Test status
Simulation time 168892870253 ps
CPU time 247.46 seconds
Started Jul 15 06:07:53 PM PDT 24
Finished Jul 15 06:12:01 PM PDT 24
Peak memory 201908 kb
Host smart-340486b6-bb59-43bc-bbe1-8a1eaf66f96a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206772239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3206772239
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1388727969
Short name T334
Test name
Test status
Simulation time 487785635278 ps
CPU time 964.28 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:23:59 PM PDT 24
Peak memory 201836 kb
Host smart-fe3f28e7-7d94-4be1-938f-a67bd9ae1da0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388727969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1388727969
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2783895052
Short name T615
Test name
Test status
Simulation time 161694256832 ps
CPU time 337.9 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:13:32 PM PDT 24
Peak memory 202004 kb
Host smart-274e284b-0a24-47e8-b895-27eec1efdbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783895052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2783895052
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2095378772
Short name T443
Test name
Test status
Simulation time 332326925188 ps
CPU time 770.61 seconds
Started Jul 15 06:07:52 PM PDT 24
Finished Jul 15 06:20:43 PM PDT 24
Peak memory 201904 kb
Host smart-8ecd86ad-162a-4581-8552-eda0047487c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095378772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2095378772
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1565114460
Short name T639
Test name
Test status
Simulation time 400557547967 ps
CPU time 442.29 seconds
Started Jul 15 06:07:58 PM PDT 24
Finished Jul 15 06:15:21 PM PDT 24
Peak memory 201828 kb
Host smart-0f15f8d6-062f-4bbd-9912-f63d0c9bc0a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565114460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1565114460
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2409041329
Short name T658
Test name
Test status
Simulation time 102187962864 ps
CPU time 354.59 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:13:58 PM PDT 24
Peak memory 202236 kb
Host smart-d18b1241-d9d0-49e3-bd77-7a8e3bc993db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409041329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2409041329
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3457207451
Short name T785
Test name
Test status
Simulation time 41058685242 ps
CPU time 90.62 seconds
Started Jul 15 06:07:54 PM PDT 24
Finished Jul 15 06:09:25 PM PDT 24
Peak memory 201696 kb
Host smart-c3da4580-264d-43a6-a2d9-a4ffaee66ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457207451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3457207451
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3595766628
Short name T733
Test name
Test status
Simulation time 3301257801 ps
CPU time 2.66 seconds
Started Jul 15 06:07:51 PM PDT 24
Finished Jul 15 06:07:54 PM PDT 24
Peak memory 201684 kb
Host smart-b58109e8-bcc1-4453-8ecc-2c58959e7571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595766628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3595766628
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4131161185
Short name T466
Test name
Test status
Simulation time 6131234336 ps
CPU time 4.47 seconds
Started Jul 15 06:07:56 PM PDT 24
Finished Jul 15 06:08:01 PM PDT 24
Peak memory 201692 kb
Host smart-c63d5e25-c118-4c24-85e2-6e95f29dd844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131161185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4131161185
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2247575747
Short name T626
Test name
Test status
Simulation time 17744287349 ps
CPU time 48.07 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:08:52 PM PDT 24
Peak memory 210516 kb
Host smart-126597a4-92c5-42e7-aec7-14478c8a22e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247575747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2247575747
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2036816074
Short name T738
Test name
Test status
Simulation time 360399661 ps
CPU time 1.4 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:07:08 PM PDT 24
Peak memory 201664 kb
Host smart-9a4292fa-6fa3-44f6-8a4c-5cc1dbf3808c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036816074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2036816074
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2168915223
Short name T414
Test name
Test status
Simulation time 331638555374 ps
CPU time 207.85 seconds
Started Jul 15 06:07:05 PM PDT 24
Finished Jul 15 06:10:34 PM PDT 24
Peak memory 201844 kb
Host smart-2cf62002-8e6e-4b0e-8313-5f454c5bc2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168915223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2168915223
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3043319208
Short name T237
Test name
Test status
Simulation time 166184166224 ps
CPU time 357.06 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:12:54 PM PDT 24
Peak memory 201928 kb
Host smart-a242215e-c7b8-463f-817d-fb27478ccb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043319208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3043319208
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1335448201
Short name T388
Test name
Test status
Simulation time 490688830425 ps
CPU time 441.3 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:14:17 PM PDT 24
Peak memory 201960 kb
Host smart-23441160-85fc-4481-9e63-972070af40f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335448201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1335448201
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2261561719
Short name T30
Test name
Test status
Simulation time 162203791234 ps
CPU time 383.92 seconds
Started Jul 15 06:06:55 PM PDT 24
Finished Jul 15 06:13:20 PM PDT 24
Peak memory 201924 kb
Host smart-6a7ebc41-ce7d-417e-b6c4-23d104fc12ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261561719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2261561719
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1643527603
Short name T644
Test name
Test status
Simulation time 325309276345 ps
CPU time 190.57 seconds
Started Jul 15 06:06:57 PM PDT 24
Finished Jul 15 06:10:09 PM PDT 24
Peak memory 201900 kb
Host smart-fd081e8a-c967-4be4-9dbe-f956eb7b3fc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643527603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1643527603
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2539688404
Short name T215
Test name
Test status
Simulation time 351733956332 ps
CPU time 812.56 seconds
Started Jul 15 06:06:58 PM PDT 24
Finished Jul 15 06:20:32 PM PDT 24
Peak memory 201900 kb
Host smart-f3324feb-1dae-42b4-9ea8-9211575d7c36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539688404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2539688404
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1642228226
Short name T714
Test name
Test status
Simulation time 205948901615 ps
CPU time 146.29 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:09:31 PM PDT 24
Peak memory 201844 kb
Host smart-5cc25398-0cda-4014-93cd-f0df5adf25bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642228226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1642228226
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1334595752
Short name T651
Test name
Test status
Simulation time 109395236257 ps
CPU time 426.01 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:14:14 PM PDT 24
Peak memory 202164 kb
Host smart-183d6da5-70d9-4ddc-a65f-2dccd9d5cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334595752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1334595752
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.574805510
Short name T786
Test name
Test status
Simulation time 40344483642 ps
CPU time 87.34 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:08:39 PM PDT 24
Peak memory 201656 kb
Host smart-0b7bdbca-0d34-4c7d-92b2-8bcd7ceebc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574805510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.574805510
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1785048703
Short name T444
Test name
Test status
Simulation time 4755053373 ps
CPU time 1.87 seconds
Started Jul 15 06:07:08 PM PDT 24
Finished Jul 15 06:07:11 PM PDT 24
Peak memory 201708 kb
Host smart-c149112c-5a31-453d-9f95-6c2f8aff792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785048703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1785048703
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2220042065
Short name T63
Test name
Test status
Simulation time 7759084754 ps
CPU time 8.94 seconds
Started Jul 15 06:07:10 PM PDT 24
Finished Jul 15 06:07:20 PM PDT 24
Peak memory 218200 kb
Host smart-5d4c36f8-1eda-4f54-bd05-2e721e8428d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220042065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2220042065
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3695982494
Short name T671
Test name
Test status
Simulation time 5741374746 ps
CPU time 4.03 seconds
Started Jul 15 06:06:56 PM PDT 24
Finished Jul 15 06:07:01 PM PDT 24
Peak memory 201708 kb
Host smart-f3004545-a7b7-4615-8ae1-01996771f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695982494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3695982494
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3570240582
Short name T17
Test name
Test status
Simulation time 328235181620 ps
CPU time 448.23 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 210464 kb
Host smart-5867904f-5216-4f74-9f61-fda0cac89872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570240582 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3570240582
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2491099011
Short name T362
Test name
Test status
Simulation time 373353584 ps
CPU time 0.8 seconds
Started Jul 15 06:08:04 PM PDT 24
Finished Jul 15 06:08:06 PM PDT 24
Peak memory 201636 kb
Host smart-7c07ba55-1973-44c2-a075-d7e079cfbff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491099011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2491099011
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2619002166
Short name T48
Test name
Test status
Simulation time 361867916652 ps
CPU time 393.85 seconds
Started Jul 15 06:07:59 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 201812 kb
Host smart-bbdebcd8-4346-4f3b-9146-1c8542b816c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619002166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2619002166
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2593051762
Short name T637
Test name
Test status
Simulation time 162408517537 ps
CPU time 48.37 seconds
Started Jul 15 06:08:03 PM PDT 24
Finished Jul 15 06:08:52 PM PDT 24
Peak memory 201880 kb
Host smart-31d03817-4530-48e1-8c80-c9b412cdef66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593051762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2593051762
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2890311586
Short name T563
Test name
Test status
Simulation time 329402039695 ps
CPU time 123.65 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:10:06 PM PDT 24
Peak memory 201984 kb
Host smart-53f63f3d-4e37-41f5-b94a-177f5db1e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890311586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2890311586
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2332996029
Short name T739
Test name
Test status
Simulation time 167949207331 ps
CPU time 92.29 seconds
Started Jul 15 06:08:05 PM PDT 24
Finished Jul 15 06:09:38 PM PDT 24
Peak memory 201872 kb
Host smart-8bab217f-f88c-4ceb-bbf7-d9ed86f099e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332996029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2332996029
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4123909392
Short name T180
Test name
Test status
Simulation time 354988747352 ps
CPU time 207.47 seconds
Started Jul 15 06:08:01 PM PDT 24
Finished Jul 15 06:11:29 PM PDT 24
Peak memory 201820 kb
Host smart-bca370a1-fe0d-48d8-a861-8fe9b48a4b73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123909392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4123909392
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2143302380
Short name T624
Test name
Test status
Simulation time 196752293856 ps
CPU time 427.2 seconds
Started Jul 15 06:08:04 PM PDT 24
Finished Jul 15 06:15:12 PM PDT 24
Peak memory 201880 kb
Host smart-89b8f4f4-3a05-4acc-bfc1-076197afa484
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143302380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2143302380
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1683484218
Short name T393
Test name
Test status
Simulation time 126909308114 ps
CPU time 395.48 seconds
Started Jul 15 06:08:10 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 202348 kb
Host smart-980cb7dd-04c6-4be7-b5f9-70475db25ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683484218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1683484218
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.295236328
Short name T473
Test name
Test status
Simulation time 23934811090 ps
CPU time 13.88 seconds
Started Jul 15 06:08:05 PM PDT 24
Finished Jul 15 06:08:19 PM PDT 24
Peak memory 201688 kb
Host smart-eeee1112-675d-4321-8114-e5768bf090fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295236328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.295236328
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.104639663
Short name T530
Test name
Test status
Simulation time 4219925701 ps
CPU time 11.28 seconds
Started Jul 15 06:08:03 PM PDT 24
Finished Jul 15 06:08:15 PM PDT 24
Peak memory 201712 kb
Host smart-90ff2d5c-44f6-4ee0-9334-27763f21bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104639663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.104639663
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.163643747
Short name T488
Test name
Test status
Simulation time 6030085610 ps
CPU time 4.62 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:08:07 PM PDT 24
Peak memory 201536 kb
Host smart-3d87ffd4-8480-463d-84ab-c0342f53cb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163643747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.163643747
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.911315151
Short name T476
Test name
Test status
Simulation time 163897266285 ps
CPU time 345.38 seconds
Started Jul 15 06:08:03 PM PDT 24
Finished Jul 15 06:13:49 PM PDT 24
Peak memory 201940 kb
Host smart-42fd2964-5f38-484d-bc6a-e3cddff69c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911315151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
911315151
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2383382033
Short name T586
Test name
Test status
Simulation time 496452418 ps
CPU time 1.8 seconds
Started Jul 15 06:08:12 PM PDT 24
Finished Jul 15 06:08:14 PM PDT 24
Peak memory 201644 kb
Host smart-8bf3ee88-fe84-4647-8d72-bb6d374963eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383382033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2383382033
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3100986055
Short name T780
Test name
Test status
Simulation time 328590092111 ps
CPU time 229.16 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:11:53 PM PDT 24
Peak memory 201844 kb
Host smart-209e4a01-914d-4177-b43f-83d409ff3087
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100986055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3100986055
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1289408882
Short name T410
Test name
Test status
Simulation time 172223291750 ps
CPU time 201.42 seconds
Started Jul 15 06:08:04 PM PDT 24
Finished Jul 15 06:11:26 PM PDT 24
Peak memory 201908 kb
Host smart-5b084005-b2a1-4411-aa0f-b3857ad1ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289408882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1289408882
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3201005161
Short name T500
Test name
Test status
Simulation time 485475725555 ps
CPU time 531.66 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:16:55 PM PDT 24
Peak memory 201984 kb
Host smart-9eb1ff85-9f2f-4918-962a-c8918cf6c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201005161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3201005161
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.264225988
Short name T464
Test name
Test status
Simulation time 166452152445 ps
CPU time 96.02 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:09:40 PM PDT 24
Peak memory 201916 kb
Host smart-722d50c0-31a2-4e82-a683-bfdbe0a876e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=264225988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.264225988
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1320541237
Short name T367
Test name
Test status
Simulation time 492427403955 ps
CPU time 1042.27 seconds
Started Jul 15 06:08:03 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 201892 kb
Host smart-2c7e3408-8895-4d3e-b92d-9ac698083a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320541237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1320541237
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2961382435
Short name T338
Test name
Test status
Simulation time 498002873932 ps
CPU time 254.71 seconds
Started Jul 15 06:08:04 PM PDT 24
Finished Jul 15 06:12:19 PM PDT 24
Peak memory 201844 kb
Host smart-f02928c4-3387-49a2-9aa6-ab03a6b24021
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961382435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2961382435
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.84841420
Short name T1
Test name
Test status
Simulation time 389771370066 ps
CPU time 202.47 seconds
Started Jul 15 06:08:05 PM PDT 24
Finished Jul 15 06:11:28 PM PDT 24
Peak memory 201904 kb
Host smart-c8188189-83ff-4236-b9d8-0c037be717a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84841420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_w
akeup.84841420
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3057836512
Short name T557
Test name
Test status
Simulation time 617621050725 ps
CPU time 427.99 seconds
Started Jul 15 06:08:03 PM PDT 24
Finished Jul 15 06:15:12 PM PDT 24
Peak memory 201844 kb
Host smart-585ce5df-0fe1-4037-a8ad-e1306d4e2c38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057836512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3057836512
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2936569877
Short name T323
Test name
Test status
Simulation time 26910834141 ps
CPU time 22.16 seconds
Started Jul 15 06:08:01 PM PDT 24
Finished Jul 15 06:08:24 PM PDT 24
Peak memory 201708 kb
Host smart-b66e2cd3-3d8c-4b4c-b652-1668ffc6efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936569877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2936569877
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4238135379
Short name T574
Test name
Test status
Simulation time 4131393154 ps
CPU time 3.31 seconds
Started Jul 15 06:08:04 PM PDT 24
Finished Jul 15 06:08:08 PM PDT 24
Peak memory 201668 kb
Host smart-046745c7-4fc2-43c9-9250-743b2fcfbc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238135379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4238135379
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.207636462
Short name T713
Test name
Test status
Simulation time 6118849866 ps
CPU time 14.31 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:08:18 PM PDT 24
Peak memory 201688 kb
Host smart-c6f8341f-61bf-4534-9f0c-b4e8780c1ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207636462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.207636462
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.413635493
Short name T7
Test name
Test status
Simulation time 287024325032 ps
CPU time 396.45 seconds
Started Jul 15 06:08:12 PM PDT 24
Finished Jul 15 06:14:49 PM PDT 24
Peak memory 210440 kb
Host smart-13bc77c9-baf3-4fc7-b500-57fc6f32bb75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413635493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
413635493
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3923735699
Short name T85
Test name
Test status
Simulation time 51099717424 ps
CPU time 97.47 seconds
Started Jul 15 06:08:02 PM PDT 24
Finished Jul 15 06:09:41 PM PDT 24
Peak memory 210604 kb
Host smart-ce46cbbe-36c1-458c-9730-777a2d638cf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923735699 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3923735699
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3731980395
Short name T577
Test name
Test status
Simulation time 487592096 ps
CPU time 1.23 seconds
Started Jul 15 06:08:09 PM PDT 24
Finished Jul 15 06:08:11 PM PDT 24
Peak memory 201656 kb
Host smart-29e70cbd-3ccb-4c4b-8c80-1693b9a514e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731980395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3731980395
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.205211901
Short name T553
Test name
Test status
Simulation time 160753059793 ps
CPU time 319.19 seconds
Started Jul 15 06:08:12 PM PDT 24
Finished Jul 15 06:13:32 PM PDT 24
Peak memory 201892 kb
Host smart-7dd04ffa-93cd-4f1d-ab29-7e9bb017efb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205211901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.205211901
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3868509130
Short name T263
Test name
Test status
Simulation time 494428180247 ps
CPU time 517.1 seconds
Started Jul 15 06:08:11 PM PDT 24
Finished Jul 15 06:16:49 PM PDT 24
Peak memory 201912 kb
Host smart-de0d9d5b-4eb2-4242-b124-21e644dd1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868509130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3868509130
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3082697691
Short name T232
Test name
Test status
Simulation time 165734787284 ps
CPU time 95.78 seconds
Started Jul 15 06:08:12 PM PDT 24
Finished Jul 15 06:09:48 PM PDT 24
Peak memory 201936 kb
Host smart-520241d9-d041-4f4b-b7d9-7ce2dde22973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082697691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3082697691
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2517845991
Short name T539
Test name
Test status
Simulation time 493979325988 ps
CPU time 208.68 seconds
Started Jul 15 06:08:13 PM PDT 24
Finished Jul 15 06:11:42 PM PDT 24
Peak memory 201880 kb
Host smart-334da232-89a2-44a2-8b6b-6f91cbc5dd62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517845991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2517845991
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.979261878
Short name T158
Test name
Test status
Simulation time 493369652655 ps
CPU time 131.52 seconds
Started Jul 15 06:08:10 PM PDT 24
Finished Jul 15 06:10:22 PM PDT 24
Peak memory 201936 kb
Host smart-f1a74d71-be31-4a07-9f7a-be5792b883b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979261878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.979261878
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3771957791
Short name T562
Test name
Test status
Simulation time 168216250871 ps
CPU time 366.8 seconds
Started Jul 15 06:08:14 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 201884 kb
Host smart-1b5f44be-1223-4370-b18d-98208a73d02a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771957791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3771957791
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1024636513
Short name T554
Test name
Test status
Simulation time 214944145955 ps
CPU time 146.87 seconds
Started Jul 15 06:08:10 PM PDT 24
Finished Jul 15 06:10:38 PM PDT 24
Peak memory 201900 kb
Host smart-22056d67-184d-4bba-b6f1-61df6c13c4de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024636513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1024636513
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.346843357
Short name T189
Test name
Test status
Simulation time 77659801937 ps
CPU time 308.12 seconds
Started Jul 15 06:08:11 PM PDT 24
Finished Jul 15 06:13:19 PM PDT 24
Peak memory 202212 kb
Host smart-9c2d0cb5-7c96-4f11-8fdc-d8405c342f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346843357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.346843357
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2820540152
Short name T383
Test name
Test status
Simulation time 30859771211 ps
CPU time 11.87 seconds
Started Jul 15 06:08:11 PM PDT 24
Finished Jul 15 06:08:24 PM PDT 24
Peak memory 201708 kb
Host smart-38bd293d-8caf-4eb4-8980-4ac4e2c7bc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820540152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2820540152
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.614335362
Short name T775
Test name
Test status
Simulation time 4116561901 ps
CPU time 10.49 seconds
Started Jul 15 06:08:11 PM PDT 24
Finished Jul 15 06:08:22 PM PDT 24
Peak memory 201740 kb
Host smart-18f2b00c-38f9-4f10-b819-8d77bd1eddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614335362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.614335362
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.616973270
Short name T90
Test name
Test status
Simulation time 5964687070 ps
CPU time 14.01 seconds
Started Jul 15 06:08:11 PM PDT 24
Finished Jul 15 06:08:26 PM PDT 24
Peak memory 201712 kb
Host smart-99dab885-3cab-4d40-b5db-c2e2d38ff1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616973270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.616973270
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4069744680
Short name T239
Test name
Test status
Simulation time 338437925191 ps
CPU time 184.5 seconds
Started Jul 15 06:08:14 PM PDT 24
Finished Jul 15 06:11:18 PM PDT 24
Peak memory 201836 kb
Host smart-d8f752e9-d62c-47a9-bc05-19d6d76579c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069744680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4069744680
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3192721933
Short name T311
Test name
Test status
Simulation time 535583147 ps
CPU time 0.82 seconds
Started Jul 15 06:08:39 PM PDT 24
Finished Jul 15 06:08:40 PM PDT 24
Peak memory 201624 kb
Host smart-5d19b033-271d-4626-97e8-934761973672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192721933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3192721933
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1050664161
Short name T612
Test name
Test status
Simulation time 165645538204 ps
CPU time 315.73 seconds
Started Jul 15 06:08:20 PM PDT 24
Finished Jul 15 06:13:36 PM PDT 24
Peak memory 201880 kb
Host smart-e7a57af3-4ff6-435e-8211-33dd9331cc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050664161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1050664161
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.373171028
Short name T787
Test name
Test status
Simulation time 326646281718 ps
CPU time 363.69 seconds
Started Jul 15 06:08:20 PM PDT 24
Finished Jul 15 06:14:24 PM PDT 24
Peak memory 201928 kb
Host smart-8b692eba-db00-4830-a783-49e0473a04d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373171028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.373171028
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1886585154
Short name T355
Test name
Test status
Simulation time 168949249749 ps
CPU time 194.99 seconds
Started Jul 15 06:08:28 PM PDT 24
Finished Jul 15 06:11:44 PM PDT 24
Peak memory 201856 kb
Host smart-4ca81642-4625-49c8-bcf2-a3f6d4ac433a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886585154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1886585154
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2474238497
Short name T735
Test name
Test status
Simulation time 328351913498 ps
CPU time 586.25 seconds
Started Jul 15 06:08:21 PM PDT 24
Finished Jul 15 06:18:08 PM PDT 24
Peak memory 201916 kb
Host smart-a90e27e8-7e12-454f-9bfe-70bbee57d2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474238497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2474238497
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.270340786
Short name T89
Test name
Test status
Simulation time 164774485102 ps
CPU time 126.16 seconds
Started Jul 15 06:08:22 PM PDT 24
Finished Jul 15 06:10:29 PM PDT 24
Peak memory 201828 kb
Host smart-3dc0d2c3-6026-4f21-ba40-47b6c415e4ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=270340786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.270340786
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2973171605
Short name T184
Test name
Test status
Simulation time 117121679464 ps
CPU time 633.66 seconds
Started Jul 15 06:08:20 PM PDT 24
Finished Jul 15 06:18:54 PM PDT 24
Peak memory 202200 kb
Host smart-96020c33-879d-4fe0-95c4-8233e89ec068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973171605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2973171605
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2999945101
Short name T725
Test name
Test status
Simulation time 34799638326 ps
CPU time 17.88 seconds
Started Jul 15 06:08:21 PM PDT 24
Finished Jul 15 06:08:39 PM PDT 24
Peak memory 201716 kb
Host smart-f11b996c-b24e-4332-8bc9-8092732eb28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999945101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2999945101
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1896638849
Short name T437
Test name
Test status
Simulation time 5252262705 ps
CPU time 7.03 seconds
Started Jul 15 06:08:22 PM PDT 24
Finished Jul 15 06:08:29 PM PDT 24
Peak memory 201620 kb
Host smart-5f12e583-deec-402b-8294-faf9a07f23e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896638849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1896638849
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2797737841
Short name T603
Test name
Test status
Simulation time 5948791341 ps
CPU time 14.74 seconds
Started Jul 15 06:08:13 PM PDT 24
Finished Jul 15 06:08:29 PM PDT 24
Peak memory 201708 kb
Host smart-e46d9507-5d53-45ca-a261-01ef95392505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797737841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2797737841
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3036442660
Short name T597
Test name
Test status
Simulation time 196270729683 ps
CPU time 129.33 seconds
Started Jul 15 06:08:21 PM PDT 24
Finished Jul 15 06:10:30 PM PDT 24
Peak memory 201872 kb
Host smart-00963a7e-bc3d-4370-a9f9-6d269a4319c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036442660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3036442660
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2077034142
Short name T229
Test name
Test status
Simulation time 142738219833 ps
CPU time 87.35 seconds
Started Jul 15 06:08:20 PM PDT 24
Finished Jul 15 06:09:48 PM PDT 24
Peak memory 210368 kb
Host smart-2e77e732-86ea-4f68-95af-0b426677d32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077034142 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2077034142
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2764687641
Short name T481
Test name
Test status
Simulation time 482544693 ps
CPU time 1.7 seconds
Started Jul 15 06:08:31 PM PDT 24
Finished Jul 15 06:08:33 PM PDT 24
Peak memory 201660 kb
Host smart-8bd2a09e-c745-40eb-970a-32e9592444c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764687641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2764687641
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2740277955
Short name T213
Test name
Test status
Simulation time 167129423908 ps
CPU time 365.93 seconds
Started Jul 15 06:08:27 PM PDT 24
Finished Jul 15 06:14:33 PM PDT 24
Peak memory 201904 kb
Host smart-37a35094-f8ef-4214-87c7-c9692e5119ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740277955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2740277955
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2151540615
Short name T145
Test name
Test status
Simulation time 492792867070 ps
CPU time 602.36 seconds
Started Jul 15 06:08:33 PM PDT 24
Finished Jul 15 06:18:36 PM PDT 24
Peak memory 201984 kb
Host smart-ac315e10-878f-4b0c-8937-2eedaf0696c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151540615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2151540615
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1278048267
Short name T551
Test name
Test status
Simulation time 166166924063 ps
CPU time 294.69 seconds
Started Jul 15 06:08:29 PM PDT 24
Finished Jul 15 06:13:24 PM PDT 24
Peak memory 201704 kb
Host smart-705fbbee-7162-4037-96e6-351ca07f80f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278048267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1278048267
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.213746045
Short name T716
Test name
Test status
Simulation time 490343548405 ps
CPU time 1162.68 seconds
Started Jul 15 06:08:30 PM PDT 24
Finished Jul 15 06:27:53 PM PDT 24
Peak memory 201964 kb
Host smart-df11f486-cdad-464d-8d76-4ac36749377f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213746045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.213746045
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.558695435
Short name T678
Test name
Test status
Simulation time 167354712960 ps
CPU time 191.92 seconds
Started Jul 15 06:08:29 PM PDT 24
Finished Jul 15 06:11:41 PM PDT 24
Peak memory 201928 kb
Host smart-23dcb837-8e65-4e97-bc50-8a7040345450
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=558695435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.558695435
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2819028062
Short name T163
Test name
Test status
Simulation time 384364140960 ps
CPU time 594.7 seconds
Started Jul 15 06:08:29 PM PDT 24
Finished Jul 15 06:18:24 PM PDT 24
Peak memory 201940 kb
Host smart-5d336047-aa86-474a-8025-9ba87862f739
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819028062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2819028062
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1640594494
Short name T386
Test name
Test status
Simulation time 199206332554 ps
CPU time 108.61 seconds
Started Jul 15 06:08:28 PM PDT 24
Finished Jul 15 06:10:17 PM PDT 24
Peak memory 201844 kb
Host smart-61730511-2c16-4448-8817-9c838447917b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640594494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1640594494
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.71244666
Short name T497
Test name
Test status
Simulation time 71862636276 ps
CPU time 307.39 seconds
Started Jul 15 06:08:29 PM PDT 24
Finished Jul 15 06:13:37 PM PDT 24
Peak memory 202276 kb
Host smart-d9556ae1-e54b-4a0d-b6ef-d6e2692ffae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71244666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.71244666
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4071020763
Short name T490
Test name
Test status
Simulation time 43572325126 ps
CPU time 18.22 seconds
Started Jul 15 06:08:39 PM PDT 24
Finished Jul 15 06:08:58 PM PDT 24
Peak memory 201680 kb
Host smart-98734669-2b28-403f-9b38-c6a82d04ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071020763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4071020763
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.708921308
Short name T121
Test name
Test status
Simulation time 5002471197 ps
CPU time 3.61 seconds
Started Jul 15 06:08:30 PM PDT 24
Finished Jul 15 06:08:34 PM PDT 24
Peak memory 201704 kb
Host smart-ff4f5681-b1d5-4749-a844-376ed9305b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708921308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.708921308
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.162542740
Short name T387
Test name
Test status
Simulation time 5570923339 ps
CPU time 12.21 seconds
Started Jul 15 06:08:27 PM PDT 24
Finished Jul 15 06:08:40 PM PDT 24
Peak memory 201672 kb
Host smart-b8c3b077-a821-44c6-a510-e7ca9e76e435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162542740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.162542740
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4019329347
Short name T88
Test name
Test status
Simulation time 56378269614 ps
CPU time 102.39 seconds
Started Jul 15 06:08:34 PM PDT 24
Finished Jul 15 06:10:16 PM PDT 24
Peak memory 210220 kb
Host smart-7402b1a0-8968-40b2-8e47-dfc4eb536724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019329347 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4019329347
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1005050382
Short name T319
Test name
Test status
Simulation time 429730437 ps
CPU time 1.07 seconds
Started Jul 15 06:08:39 PM PDT 24
Finished Jul 15 06:08:40 PM PDT 24
Peak memory 201652 kb
Host smart-00de7fc6-a506-4cea-a22d-939eaec535fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005050382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1005050382
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3225749315
Short name T727
Test name
Test status
Simulation time 161111520300 ps
CPU time 260 seconds
Started Jul 15 06:08:38 PM PDT 24
Finished Jul 15 06:12:58 PM PDT 24
Peak memory 201960 kb
Host smart-451b2228-2795-4f2c-8fe7-cfa09c99f83e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225749315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3225749315
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2880381260
Short name T769
Test name
Test status
Simulation time 167865654966 ps
CPU time 97.25 seconds
Started Jul 15 06:08:36 PM PDT 24
Finished Jul 15 06:10:14 PM PDT 24
Peak memory 201904 kb
Host smart-529a2530-2cb6-4461-b1b4-fe9f16ce2a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880381260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2880381260
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2973468395
Short name T282
Test name
Test status
Simulation time 169315694576 ps
CPU time 26.3 seconds
Started Jul 15 06:08:28 PM PDT 24
Finished Jul 15 06:08:55 PM PDT 24
Peak memory 201904 kb
Host smart-41f6c719-ea69-4de4-b90b-c1334bd62b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973468395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2973468395
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3327118531
Short name T487
Test name
Test status
Simulation time 165029404240 ps
CPU time 92.15 seconds
Started Jul 15 06:08:28 PM PDT 24
Finished Jul 15 06:10:01 PM PDT 24
Peak memory 201896 kb
Host smart-b135a360-efa4-42ce-b3a5-b90745b1f872
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327118531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3327118531
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1712025920
Short name T740
Test name
Test status
Simulation time 166817578936 ps
CPU time 53.89 seconds
Started Jul 15 06:08:31 PM PDT 24
Finished Jul 15 06:09:25 PM PDT 24
Peak memory 201948 kb
Host smart-31e7dc6e-2e7b-4bb7-ba2c-eab11a5549b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712025920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1712025920
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.820500458
Short name T538
Test name
Test status
Simulation time 164937771850 ps
CPU time 87.48 seconds
Started Jul 15 06:08:40 PM PDT 24
Finished Jul 15 06:10:08 PM PDT 24
Peak memory 201872 kb
Host smart-bb957885-97c7-47fb-9bc8-45a806e063f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820500458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.820500458
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.268178348
Short name T698
Test name
Test status
Simulation time 353971888178 ps
CPU time 217.29 seconds
Started Jul 15 06:08:34 PM PDT 24
Finished Jul 15 06:12:11 PM PDT 24
Peak memory 201904 kb
Host smart-e85e4639-9177-4936-8495-6487f588514c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268178348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.268178348
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1716140786
Short name T354
Test name
Test status
Simulation time 198914958144 ps
CPU time 112.8 seconds
Started Jul 15 06:08:33 PM PDT 24
Finished Jul 15 06:10:26 PM PDT 24
Peak memory 201880 kb
Host smart-a4dad1b6-be9f-418b-b65f-3a3703162a49
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716140786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1716140786
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.953378837
Short name T300
Test name
Test status
Simulation time 88174359500 ps
CPU time 369.17 seconds
Started Jul 15 06:08:36 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 202292 kb
Host smart-85e9f5f5-85ff-4caa-bffa-dbca25746cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953378837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.953378837
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3388710830
Short name T431
Test name
Test status
Simulation time 31825282210 ps
CPU time 11.89 seconds
Started Jul 15 06:08:36 PM PDT 24
Finished Jul 15 06:08:48 PM PDT 24
Peak memory 201616 kb
Host smart-5de15367-5b2e-4fbc-8bb8-b78690966a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388710830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3388710830
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3622589236
Short name T100
Test name
Test status
Simulation time 3291562345 ps
CPU time 3.1 seconds
Started Jul 15 06:08:42 PM PDT 24
Finished Jul 15 06:08:46 PM PDT 24
Peak memory 201680 kb
Host smart-f860a9e6-8211-48a2-ba3d-1d8896f76710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622589236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3622589236
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.658709543
Short name T384
Test name
Test status
Simulation time 5815508351 ps
CPU time 3.85 seconds
Started Jul 15 06:08:27 PM PDT 24
Finished Jul 15 06:08:31 PM PDT 24
Peak memory 201696 kb
Host smart-6b3608c1-2023-4f05-b420-ca7647288d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658709543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.658709543
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3423364629
Short name T625
Test name
Test status
Simulation time 414900871 ps
CPU time 0.93 seconds
Started Jul 15 06:08:45 PM PDT 24
Finished Jul 15 06:08:46 PM PDT 24
Peak memory 201652 kb
Host smart-320372ce-47f3-4f0f-b143-6f89c9b99cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423364629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3423364629
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2416411958
Short name T240
Test name
Test status
Simulation time 160797077768 ps
CPU time 351.41 seconds
Started Jul 15 06:08:42 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 201920 kb
Host smart-77113915-89ed-497e-be14-19caccc121c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416411958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2416411958
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3469853010
Short name T159
Test name
Test status
Simulation time 330992435397 ps
CPU time 144.86 seconds
Started Jul 15 06:08:39 PM PDT 24
Finished Jul 15 06:11:05 PM PDT 24
Peak memory 201844 kb
Host smart-fcfa0eb1-ea3e-4176-87c5-38ca0b5cfc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469853010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3469853010
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1860376138
Short name T648
Test name
Test status
Simulation time 325369641446 ps
CPU time 391.91 seconds
Started Jul 15 06:08:37 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 201896 kb
Host smart-ed10510a-e3f3-453f-b642-3b819a4f3e66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860376138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1860376138
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.5729181
Short name T379
Test name
Test status
Simulation time 482409958498 ps
CPU time 1051.48 seconds
Started Jul 15 06:08:42 PM PDT 24
Finished Jul 15 06:26:14 PM PDT 24
Peak memory 201880 kb
Host smart-6a70139b-31ba-4f78-8934-68689e2f7d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5729181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.5729181
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1535637652
Short name T330
Test name
Test status
Simulation time 165305164064 ps
CPU time 95.27 seconds
Started Jul 15 06:08:37 PM PDT 24
Finished Jul 15 06:10:13 PM PDT 24
Peak memory 201876 kb
Host smart-90b46e5f-14c4-4f70-9c08-f88c35e490fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535637652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1535637652
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.736588625
Short name T256
Test name
Test status
Simulation time 523911535941 ps
CPU time 137.9 seconds
Started Jul 15 06:08:37 PM PDT 24
Finished Jul 15 06:10:55 PM PDT 24
Peak memory 201864 kb
Host smart-6c56acdb-4a8d-49d9-872c-b7e6dfb665f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736588625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.736588625
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2083054190
Short name T552
Test name
Test status
Simulation time 600416371488 ps
CPU time 234.97 seconds
Started Jul 15 06:08:38 PM PDT 24
Finished Jul 15 06:12:34 PM PDT 24
Peak memory 201888 kb
Host smart-cc4eb517-dc5d-4cad-bb9f-1baf77c9c0d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083054190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2083054190
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.733439652
Short name T694
Test name
Test status
Simulation time 94181072328 ps
CPU time 472.11 seconds
Started Jul 15 06:08:35 PM PDT 24
Finished Jul 15 06:16:28 PM PDT 24
Peak memory 202152 kb
Host smart-076bbb24-58b1-428a-abdc-ca01fee1112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733439652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.733439652
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1762032263
Short name T502
Test name
Test status
Simulation time 28214042554 ps
CPU time 15.56 seconds
Started Jul 15 06:08:37 PM PDT 24
Finished Jul 15 06:08:52 PM PDT 24
Peak memory 201640 kb
Host smart-04c04fbe-2278-41e0-8590-d6a80f27228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762032263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1762032263
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3595158296
Short name T782
Test name
Test status
Simulation time 4744899332 ps
CPU time 5.44 seconds
Started Jul 15 06:08:39 PM PDT 24
Finished Jul 15 06:08:45 PM PDT 24
Peak memory 201704 kb
Host smart-858b9b1a-d980-4802-95c3-7a4861ff7fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595158296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3595158296
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2536905621
Short name T583
Test name
Test status
Simulation time 5913519236 ps
CPU time 12.78 seconds
Started Jul 15 06:08:36 PM PDT 24
Finished Jul 15 06:08:49 PM PDT 24
Peak memory 201696 kb
Host smart-4f03c5a6-a359-448a-bb20-beb645d6ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536905621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2536905621
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.279720725
Short name T534
Test name
Test status
Simulation time 199003750945 ps
CPU time 81.4 seconds
Started Jul 15 06:08:44 PM PDT 24
Finished Jul 15 06:10:06 PM PDT 24
Peak memory 201876 kb
Host smart-d601d2cd-c836-415a-9879-c6ca243aeb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279720725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
279720725
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1676685024
Short name T660
Test name
Test status
Simulation time 284868541640 ps
CPU time 201.47 seconds
Started Jul 15 06:08:37 PM PDT 24
Finished Jul 15 06:11:59 PM PDT 24
Peak memory 218132 kb
Host smart-0d8556bb-6961-40bb-a6bb-2a25f8ea6463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676685024 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1676685024
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.4020406871
Short name T46
Test name
Test status
Simulation time 458199426 ps
CPU time 0.9 seconds
Started Jul 15 06:08:54 PM PDT 24
Finished Jul 15 06:08:55 PM PDT 24
Peak memory 201588 kb
Host smart-7e8b5a02-efd0-49cd-9320-c0d1612471b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020406871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4020406871
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.223680557
Short name T535
Test name
Test status
Simulation time 340058753251 ps
CPU time 256.81 seconds
Started Jul 15 06:08:45 PM PDT 24
Finished Jul 15 06:13:03 PM PDT 24
Peak memory 201896 kb
Host smart-541caaef-ef20-4eae-b7e4-8314c10cfb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223680557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.223680557
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.669633491
Short name T461
Test name
Test status
Simulation time 164613786317 ps
CPU time 391.79 seconds
Started Jul 15 06:08:46 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 201868 kb
Host smart-4e015366-137d-4c55-b8ad-649cbdf3586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669633491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.669633491
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.394545303
Short name T313
Test name
Test status
Simulation time 481906031065 ps
CPU time 218.93 seconds
Started Jul 15 06:08:47 PM PDT 24
Finished Jul 15 06:12:26 PM PDT 24
Peak memory 201896 kb
Host smart-ee46abe8-f9a5-4bdb-b931-be505f146da9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=394545303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.394545303
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2524315772
Short name T616
Test name
Test status
Simulation time 502629900742 ps
CPU time 570.35 seconds
Started Jul 15 06:08:44 PM PDT 24
Finished Jul 15 06:18:15 PM PDT 24
Peak memory 201884 kb
Host smart-f0b726d8-7622-4fc7-ab03-4796e132f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524315772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2524315772
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.120007913
Short name T381
Test name
Test status
Simulation time 161977344213 ps
CPU time 43.57 seconds
Started Jul 15 06:08:45 PM PDT 24
Finished Jul 15 06:09:29 PM PDT 24
Peak memory 201832 kb
Host smart-eb85bda3-6c41-426b-897c-bb1979cb0165
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=120007913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.120007913
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1142347855
Short name T606
Test name
Test status
Simulation time 356133710050 ps
CPU time 824.81 seconds
Started Jul 15 06:08:43 PM PDT 24
Finished Jul 15 06:22:29 PM PDT 24
Peak memory 201932 kb
Host smart-f54dbcd0-5be1-498b-9a33-8d41c5e527de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142347855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1142347855
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2002151256
Short name T654
Test name
Test status
Simulation time 203048901447 ps
CPU time 454.43 seconds
Started Jul 15 06:08:47 PM PDT 24
Finished Jul 15 06:16:22 PM PDT 24
Peak memory 201924 kb
Host smart-43e8b7d6-c672-429e-87fc-0e8bdc80abeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002151256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2002151256
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2083393041
Short name T611
Test name
Test status
Simulation time 125156546494 ps
CPU time 470.67 seconds
Started Jul 15 06:08:45 PM PDT 24
Finished Jul 15 06:16:36 PM PDT 24
Peak memory 202052 kb
Host smart-a13f24db-391b-469b-853b-5d6043a637b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083393041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2083393041
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2262025115
Short name T673
Test name
Test status
Simulation time 37279400918 ps
CPU time 18.85 seconds
Started Jul 15 06:08:47 PM PDT 24
Finished Jul 15 06:09:06 PM PDT 24
Peak memory 201736 kb
Host smart-3b1b85fd-48df-46a9-be2b-5bf825434cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262025115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2262025115
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2601488028
Short name T498
Test name
Test status
Simulation time 2862612213 ps
CPU time 6.56 seconds
Started Jul 15 06:08:47 PM PDT 24
Finished Jul 15 06:08:54 PM PDT 24
Peak memory 201704 kb
Host smart-874dafd5-037b-4b89-b423-91358a6ede52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601488028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2601488028
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2959380181
Short name T680
Test name
Test status
Simulation time 5871035224 ps
CPU time 13.63 seconds
Started Jul 15 06:08:44 PM PDT 24
Finished Jul 15 06:08:57 PM PDT 24
Peak memory 201696 kb
Host smart-7e9f46a4-147b-43f0-a610-64cd4afca600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959380181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2959380181
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3508189686
Short name T669
Test name
Test status
Simulation time 227570691092 ps
CPU time 699.7 seconds
Started Jul 15 06:08:44 PM PDT 24
Finished Jul 15 06:20:25 PM PDT 24
Peak memory 202184 kb
Host smart-2acfd663-0643-49b1-b5d6-999eb3739331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508189686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3508189686
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1653148713
Short name T356
Test name
Test status
Simulation time 320896423 ps
CPU time 1.51 seconds
Started Jul 15 06:08:53 PM PDT 24
Finished Jul 15 06:08:55 PM PDT 24
Peak memory 201652 kb
Host smart-f00aff46-58a1-42b6-85f9-8543d9f9f1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653148713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1653148713
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2414722880
Short name T717
Test name
Test status
Simulation time 380839642101 ps
CPU time 219.05 seconds
Started Jul 15 06:08:56 PM PDT 24
Finished Jul 15 06:12:35 PM PDT 24
Peak memory 201904 kb
Host smart-5bf9a770-6764-4594-b8b0-91555ea48da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414722880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2414722880
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3339633440
Short name T287
Test name
Test status
Simulation time 164325954695 ps
CPU time 100.07 seconds
Started Jul 15 06:08:56 PM PDT 24
Finished Jul 15 06:10:36 PM PDT 24
Peak memory 202016 kb
Host smart-d63f389e-a4d1-41f2-937a-831f675d1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339633440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3339633440
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2624485917
Short name T83
Test name
Test status
Simulation time 323763971054 ps
CPU time 201.43 seconds
Started Jul 15 06:08:53 PM PDT 24
Finished Jul 15 06:12:15 PM PDT 24
Peak memory 201788 kb
Host smart-4a4abf1e-47c4-48e1-9c3d-f76dfa08cd44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624485917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2624485917
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1350552481
Short name T399
Test name
Test status
Simulation time 326502266620 ps
CPU time 699.89 seconds
Started Jul 15 06:08:52 PM PDT 24
Finished Jul 15 06:20:33 PM PDT 24
Peak memory 201908 kb
Host smart-54bf7201-2055-4bbb-964f-c10fdefb6d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350552481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1350552481
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3112381115
Short name T642
Test name
Test status
Simulation time 493309232209 ps
CPU time 269.3 seconds
Started Jul 15 06:08:53 PM PDT 24
Finished Jul 15 06:13:23 PM PDT 24
Peak memory 201904 kb
Host smart-3e8407f6-192d-4942-b8c9-466c4188870a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112381115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3112381115
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3350838683
Short name T257
Test name
Test status
Simulation time 177170720350 ps
CPU time 116.82 seconds
Started Jul 15 06:08:53 PM PDT 24
Finished Jul 15 06:10:50 PM PDT 24
Peak memory 201740 kb
Host smart-c2464e77-0fce-4a93-8ab1-f4be8f9bdda1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350838683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3350838683
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1649714380
Short name T429
Test name
Test status
Simulation time 415360793415 ps
CPU time 430.13 seconds
Started Jul 15 06:08:53 PM PDT 24
Finished Jul 15 06:16:03 PM PDT 24
Peak memory 201868 kb
Host smart-3a85cfc5-f298-4f81-b2bd-5eb3ad62c903
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649714380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1649714380
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4095499278
Short name T469
Test name
Test status
Simulation time 76032952860 ps
CPU time 410.15 seconds
Started Jul 15 06:08:52 PM PDT 24
Finished Jul 15 06:15:43 PM PDT 24
Peak memory 202256 kb
Host smart-22e39713-fee2-4643-90e7-6790e2a13a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095499278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4095499278
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4130012587
Short name T526
Test name
Test status
Simulation time 41513739107 ps
CPU time 98.74 seconds
Started Jul 15 06:08:52 PM PDT 24
Finished Jul 15 06:10:31 PM PDT 24
Peak memory 201716 kb
Host smart-3b7f4072-4984-4337-8aec-ac3986323d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130012587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4130012587
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3873454680
Short name T370
Test name
Test status
Simulation time 4512457993 ps
CPU time 2.36 seconds
Started Jul 15 06:08:54 PM PDT 24
Finished Jul 15 06:08:56 PM PDT 24
Peak memory 201712 kb
Host smart-0339f852-08ec-45e6-aca0-be6b60cb0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873454680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3873454680
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1168994360
Short name T707
Test name
Test status
Simulation time 5534345043 ps
CPU time 14.69 seconds
Started Jul 15 06:08:51 PM PDT 24
Finished Jul 15 06:09:06 PM PDT 24
Peak memory 201708 kb
Host smart-b8149d69-149e-45e8-88c6-800bf8f3f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168994360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1168994360
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4179498421
Short name T34
Test name
Test status
Simulation time 1086983562 ps
CPU time 2.16 seconds
Started Jul 15 06:08:56 PM PDT 24
Finished Jul 15 06:08:58 PM PDT 24
Peak memory 201636 kb
Host smart-b0a3f89a-93a1-41bb-973c-b27d3e753fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179498421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4179498421
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3540602411
Short name T289
Test name
Test status
Simulation time 93168944891 ps
CPU time 228.44 seconds
Started Jul 15 06:08:52 PM PDT 24
Finished Jul 15 06:12:41 PM PDT 24
Peak memory 210608 kb
Host smart-ff052941-2c26-4cd0-8b37-639961d36342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540602411 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3540602411
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.173464431
Short name T312
Test name
Test status
Simulation time 451293458 ps
CPU time 0.86 seconds
Started Jul 15 06:09:12 PM PDT 24
Finished Jul 15 06:09:14 PM PDT 24
Peak memory 201660 kb
Host smart-13129ddd-21d2-45a3-aba1-7c1d6f95afd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173464431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.173464431
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3747393526
Short name T764
Test name
Test status
Simulation time 499973658758 ps
CPU time 512.47 seconds
Started Jul 15 06:09:01 PM PDT 24
Finished Jul 15 06:17:33 PM PDT 24
Peak memory 201860 kb
Host smart-4481e467-b802-45b8-a720-bd6885f1b5c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747393526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3747393526
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2252634180
Short name T27
Test name
Test status
Simulation time 175748570425 ps
CPU time 382.05 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:15:22 PM PDT 24
Peak memory 201904 kb
Host smart-ddc59baf-48f1-4784-a58b-300f5aa66b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252634180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2252634180
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1710943531
Short name T252
Test name
Test status
Simulation time 487044672127 ps
CPU time 1138.26 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:27:58 PM PDT 24
Peak memory 201864 kb
Host smart-8a7e670c-b7c9-46f7-81f4-ad63cd5f8b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710943531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1710943531
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2588622048
Short name T628
Test name
Test status
Simulation time 333995458579 ps
CPU time 167.69 seconds
Started Jul 15 06:09:08 PM PDT 24
Finished Jul 15 06:11:56 PM PDT 24
Peak memory 201896 kb
Host smart-ed4a47e2-de6a-4a4b-9cb9-88edbb8442d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588622048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2588622048
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1763055577
Short name T248
Test name
Test status
Simulation time 496530104624 ps
CPU time 290.96 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:13:50 PM PDT 24
Peak memory 201892 kb
Host smart-c308319c-0800-463e-b713-e33e1784c12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763055577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1763055577
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3769394244
Short name T533
Test name
Test status
Simulation time 485287601209 ps
CPU time 535.29 seconds
Started Jul 15 06:09:07 PM PDT 24
Finished Jul 15 06:18:03 PM PDT 24
Peak memory 201888 kb
Host smart-089e630f-cfcb-40c5-af08-cae43bf7d7e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769394244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3769394244
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3459799474
Short name T641
Test name
Test status
Simulation time 187968406398 ps
CPU time 425.41 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:16:05 PM PDT 24
Peak memory 201880 kb
Host smart-3828b9e8-5a59-4048-9fb1-3a4f0df5facb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459799474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3459799474
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3270291371
Short name T675
Test name
Test status
Simulation time 411922481715 ps
CPU time 476 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:16:56 PM PDT 24
Peak memory 201892 kb
Host smart-68a196ce-14dd-4f35-815a-83d3c42e9737
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270291371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3270291371
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1984549280
Short name T518
Test name
Test status
Simulation time 87556379048 ps
CPU time 323.93 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:14:24 PM PDT 24
Peak memory 202288 kb
Host smart-84ef531b-de14-4c38-af06-3cf23aeec26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984549280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1984549280
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1694714722
Short name T645
Test name
Test status
Simulation time 40864387421 ps
CPU time 47.4 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:09:47 PM PDT 24
Peak memory 201684 kb
Host smart-3472ab71-c294-42cc-a447-ed30c8bfeda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694714722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1694714722
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1261688489
Short name T731
Test name
Test status
Simulation time 4627208678 ps
CPU time 10.12 seconds
Started Jul 15 06:08:59 PM PDT 24
Finished Jul 15 06:09:10 PM PDT 24
Peak memory 201684 kb
Host smart-fa2bca22-c075-4044-ace3-642f4c55a86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261688489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1261688489
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1635270642
Short name T667
Test name
Test status
Simulation time 5888850737 ps
CPU time 4.33 seconds
Started Jul 15 06:09:08 PM PDT 24
Finished Jul 15 06:09:12 PM PDT 24
Peak memory 201720 kb
Host smart-b349b614-e1a5-4129-85cb-dcd566aa63da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635270642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1635270642
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2370518012
Short name T254
Test name
Test status
Simulation time 72381785222 ps
CPU time 151.52 seconds
Started Jul 15 06:09:11 PM PDT 24
Finished Jul 15 06:11:43 PM PDT 24
Peak memory 210508 kb
Host smart-b4d96400-6f59-4e81-a3d3-102894a95f79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370518012 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2370518012
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.293281672
Short name T459
Test name
Test status
Simulation time 342535569 ps
CPU time 1.43 seconds
Started Jul 15 06:07:05 PM PDT 24
Finished Jul 15 06:07:07 PM PDT 24
Peak memory 201652 kb
Host smart-a1d3cdb1-3b76-4e52-83f3-89fdf7485dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293281672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.293281672
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3813885201
Short name T210
Test name
Test status
Simulation time 512568661407 ps
CPU time 648.31 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:18:00 PM PDT 24
Peak memory 201800 kb
Host smart-eb18a2f8-9fcc-4876-8d49-476f8229b6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813885201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3813885201
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1051878209
Short name T233
Test name
Test status
Simulation time 493432210309 ps
CPU time 291.2 seconds
Started Jul 15 06:07:05 PM PDT 24
Finished Jul 15 06:11:57 PM PDT 24
Peak memory 201844 kb
Host smart-21a8f89e-8f00-40a0-9396-ac03737721b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051878209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1051878209
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3745725801
Short name T685
Test name
Test status
Simulation time 498366550267 ps
CPU time 1090.91 seconds
Started Jul 15 06:07:10 PM PDT 24
Finished Jul 15 06:25:22 PM PDT 24
Peak memory 201832 kb
Host smart-0adeaa27-28a7-4c59-8da0-224a21f3f511
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745725801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3745725801
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2308190523
Short name T623
Test name
Test status
Simulation time 331216075661 ps
CPU time 190.09 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:10:27 PM PDT 24
Peak memory 202024 kb
Host smart-5c50e4c3-5b8a-4711-98e0-33729c95c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308190523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2308190523
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2542956740
Short name T783
Test name
Test status
Simulation time 499102876815 ps
CPU time 556.71 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:16:23 PM PDT 24
Peak memory 201904 kb
Host smart-af2a6ff0-c213-4fd3-bd0f-e7bd9183979d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542956740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2542956740
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2864857026
Short name T166
Test name
Test status
Simulation time 397653425741 ps
CPU time 204.86 seconds
Started Jul 15 06:07:08 PM PDT 24
Finished Jul 15 06:10:34 PM PDT 24
Peak memory 201892 kb
Host smart-da5c86a3-8a32-46a5-a424-f42be6437c23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864857026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2864857026
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4197744251
Short name T693
Test name
Test status
Simulation time 98028469203 ps
CPU time 537.01 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:16:05 PM PDT 24
Peak memory 202232 kb
Host smart-648ff6dc-b420-4880-bf49-ce1004e3ca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197744251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4197744251
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1379149559
Short name T395
Test name
Test status
Simulation time 33211352922 ps
CPU time 19.5 seconds
Started Jul 15 06:07:02 PM PDT 24
Finished Jul 15 06:07:22 PM PDT 24
Peak memory 201704 kb
Host smart-4a8dc5a5-e1b1-4a28-928d-6cbf7f6cd479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379149559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1379149559
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3163169061
Short name T9
Test name
Test status
Simulation time 4415238154 ps
CPU time 3.48 seconds
Started Jul 15 06:07:09 PM PDT 24
Finished Jul 15 06:07:13 PM PDT 24
Peak memory 201680 kb
Host smart-4bee5fc1-2a3a-4939-9f0b-672be302d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163169061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3163169061
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2679502809
Short name T78
Test name
Test status
Simulation time 4328913311 ps
CPU time 9.86 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:07:18 PM PDT 24
Peak memory 217152 kb
Host smart-47d4dd39-fd96-4b01-baf9-a6d7f48b52dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679502809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2679502809
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3437466071
Short name T470
Test name
Test status
Simulation time 5984988546 ps
CPU time 7.67 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:07:15 PM PDT 24
Peak memory 201736 kb
Host smart-711eaff4-1924-4af1-907b-6bfe77340fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437466071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3437466071
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3655126542
Short name T652
Test name
Test status
Simulation time 332793278745 ps
CPU time 179.76 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:10:11 PM PDT 24
Peak memory 201892 kb
Host smart-01fda29a-d637-40ce-8513-e87648a2b960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655126542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3655126542
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1840394788
Short name T228
Test name
Test status
Simulation time 113964726321 ps
CPU time 73.41 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:08:19 PM PDT 24
Peak memory 202032 kb
Host smart-75407512-287d-412c-b815-ca7837646863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840394788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1840394788
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3988316190
Short name T358
Test name
Test status
Simulation time 511821795 ps
CPU time 0.8 seconds
Started Jul 15 06:09:18 PM PDT 24
Finished Jul 15 06:09:19 PM PDT 24
Peak memory 201608 kb
Host smart-03bdba87-c9b3-48cc-bf75-d210697bb0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988316190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3988316190
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.302909386
Short name T777
Test name
Test status
Simulation time 174963794164 ps
CPU time 364.18 seconds
Started Jul 15 06:09:11 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 201836 kb
Host smart-b1bddced-bf1a-4a0e-83be-163f1b031c65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302909386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.302909386
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3410933023
Short name T653
Test name
Test status
Simulation time 160612333419 ps
CPU time 168.71 seconds
Started Jul 15 06:09:10 PM PDT 24
Finished Jul 15 06:11:59 PM PDT 24
Peak memory 201844 kb
Host smart-80bfe2ee-3108-44ed-ad86-46de89e05ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410933023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3410933023
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1579566439
Short name T462
Test name
Test status
Simulation time 496837691956 ps
CPU time 1132.02 seconds
Started Jul 15 06:09:12 PM PDT 24
Finished Jul 15 06:28:05 PM PDT 24
Peak memory 201872 kb
Host smart-2852af2b-7019-4ece-a720-37ce8835787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579566439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1579566439
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.313194732
Short name T699
Test name
Test status
Simulation time 323408642947 ps
CPU time 793.25 seconds
Started Jul 15 06:09:12 PM PDT 24
Finished Jul 15 06:22:27 PM PDT 24
Peak memory 201884 kb
Host smart-07d369c5-0290-49e3-9eb8-9ef3fedc4b35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=313194732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.313194732
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1891777249
Short name T748
Test name
Test status
Simulation time 336382199548 ps
CPU time 178.9 seconds
Started Jul 15 06:09:13 PM PDT 24
Finished Jul 15 06:12:13 PM PDT 24
Peak memory 201920 kb
Host smart-fbfaa140-fde3-4ea2-95a4-93a6d1ff6af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891777249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1891777249
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3997924079
Short name T6
Test name
Test status
Simulation time 329257842158 ps
CPU time 740.66 seconds
Started Jul 15 06:09:11 PM PDT 24
Finished Jul 15 06:21:32 PM PDT 24
Peak memory 201888 kb
Host smart-d31fd747-a4a6-41e4-ac08-00ef783a27e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997924079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3997924079
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.203942695
Short name T291
Test name
Test status
Simulation time 591965012252 ps
CPU time 768.62 seconds
Started Jul 15 06:09:27 PM PDT 24
Finished Jul 15 06:22:16 PM PDT 24
Peak memory 201952 kb
Host smart-72c1dd86-1d8c-48f3-b0b9-b3fe0ae5d051
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203942695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.203942695
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.306040714
Short name T636
Test name
Test status
Simulation time 204512907489 ps
CPU time 221.19 seconds
Started Jul 15 06:09:12 PM PDT 24
Finished Jul 15 06:12:54 PM PDT 24
Peak memory 201864 kb
Host smart-704aa8c5-1092-4870-b7d3-495e2cb2a6db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306040714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.306040714
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1040157873
Short name T351
Test name
Test status
Simulation time 113819896421 ps
CPU time 336.38 seconds
Started Jul 15 06:09:17 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 202140 kb
Host smart-2aa8635b-bda6-4225-b7c5-6ca5a43d1b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040157873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1040157873
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.872731047
Short name T471
Test name
Test status
Simulation time 25308915328 ps
CPU time 25.87 seconds
Started Jul 15 06:09:11 PM PDT 24
Finished Jul 15 06:09:38 PM PDT 24
Peak memory 201692 kb
Host smart-1c4197da-55fa-450d-931c-78039bde24f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872731047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.872731047
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.627728202
Short name T650
Test name
Test status
Simulation time 4638626045 ps
CPU time 3.69 seconds
Started Jul 15 06:09:12 PM PDT 24
Finished Jul 15 06:09:17 PM PDT 24
Peak memory 201732 kb
Host smart-8998e8b2-fec5-4df2-ae29-54617d9192b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627728202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.627728202
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2909217025
Short name T340
Test name
Test status
Simulation time 5955351766 ps
CPU time 8.04 seconds
Started Jul 15 06:09:11 PM PDT 24
Finished Jul 15 06:09:19 PM PDT 24
Peak memory 201744 kb
Host smart-c6428481-f77e-42c1-96c8-1ad2d6b7311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909217025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2909217025
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.352951436
Short name T169
Test name
Test status
Simulation time 417721343026 ps
CPU time 250.95 seconds
Started Jul 15 06:09:17 PM PDT 24
Finished Jul 15 06:13:28 PM PDT 24
Peak memory 201900 kb
Host smart-775eec4c-5c56-4223-8fb1-d9025e981d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352951436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
352951436
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1907163821
Short name T631
Test name
Test status
Simulation time 100408835356 ps
CPU time 153.15 seconds
Started Jul 15 06:09:14 PM PDT 24
Finished Jul 15 06:11:48 PM PDT 24
Peak memory 218384 kb
Host smart-126fd08d-61ce-45ff-8d01-ef7880861ff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907163821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1907163821
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2792998910
Short name T750
Test name
Test status
Simulation time 348770307 ps
CPU time 1.46 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:09:26 PM PDT 24
Peak memory 201608 kb
Host smart-03729b21-7863-4714-94ef-a47cfe47b7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792998910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2792998910
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2607472855
Short name T374
Test name
Test status
Simulation time 164264625647 ps
CPU time 383.62 seconds
Started Jul 15 06:09:18 PM PDT 24
Finished Jul 15 06:15:42 PM PDT 24
Peak memory 201860 kb
Host smart-6ee91d78-f060-4823-8a69-994b3c5f3403
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607472855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2607472855
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4241813980
Short name T293
Test name
Test status
Simulation time 534809345922 ps
CPU time 956.43 seconds
Started Jul 15 06:09:18 PM PDT 24
Finished Jul 15 06:25:15 PM PDT 24
Peak memory 201916 kb
Host smart-c8750bcf-0565-43cc-b78b-7b77634af875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241813980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4241813980
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4162835703
Short name T719
Test name
Test status
Simulation time 491950571828 ps
CPU time 313.19 seconds
Started Jul 15 06:09:18 PM PDT 24
Finished Jul 15 06:14:31 PM PDT 24
Peak memory 201788 kb
Host smart-ac77aeed-921e-4685-80d6-464cd701393e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162835703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4162835703
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.723153552
Short name T445
Test name
Test status
Simulation time 495180992642 ps
CPU time 1034.93 seconds
Started Jul 15 06:09:18 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 201924 kb
Host smart-9da5d21f-b6eb-4aae-85e8-ff033bdf2623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723153552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.723153552
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3248904567
Short name T448
Test name
Test status
Simulation time 162054367233 ps
CPU time 86.89 seconds
Started Jul 15 06:09:18 PM PDT 24
Finished Jul 15 06:10:46 PM PDT 24
Peak memory 201884 kb
Host smart-e2ccd0d2-02fc-44d8-a416-125cb047ec87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248904567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3248904567
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3210711266
Short name T742
Test name
Test status
Simulation time 582724119235 ps
CPU time 931.27 seconds
Started Jul 15 06:09:17 PM PDT 24
Finished Jul 15 06:24:48 PM PDT 24
Peak memory 201904 kb
Host smart-9203ba17-48ef-4890-9547-ce0965dafe8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210711266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3210711266
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2777640514
Short name T690
Test name
Test status
Simulation time 203774516921 ps
CPU time 421.74 seconds
Started Jul 15 06:09:17 PM PDT 24
Finished Jul 15 06:16:19 PM PDT 24
Peak memory 201848 kb
Host smart-5b524c67-ba35-4f83-b4c1-eaaa3e701e19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777640514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2777640514
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3763186929
Short name T36
Test name
Test status
Simulation time 84795715351 ps
CPU time 429.49 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:16:34 PM PDT 24
Peak memory 202284 kb
Host smart-056f7868-ccd5-4a8c-873e-575a7466f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763186929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3763186929
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3239730518
Short name T607
Test name
Test status
Simulation time 41731436135 ps
CPU time 89.53 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:10:54 PM PDT 24
Peak memory 201708 kb
Host smart-56b8df1d-fe1e-4176-8c45-364fb06e286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239730518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3239730518
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3250810812
Short name T555
Test name
Test status
Simulation time 4792158307 ps
CPU time 9.55 seconds
Started Jul 15 06:09:21 PM PDT 24
Finished Jul 15 06:09:32 PM PDT 24
Peak memory 201592 kb
Host smart-6846e934-5e60-457f-bcca-2fc5b6557a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250810812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3250810812
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3088549401
Short name T542
Test name
Test status
Simulation time 5977404632 ps
CPU time 7.12 seconds
Started Jul 15 06:09:13 PM PDT 24
Finished Jul 15 06:09:20 PM PDT 24
Peak memory 201668 kb
Host smart-9b2e66b5-bba3-4158-a525-34f4d9185209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088549401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3088549401
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2459342280
Short name T556
Test name
Test status
Simulation time 230888053300 ps
CPU time 283.87 seconds
Started Jul 15 06:09:22 PM PDT 24
Finished Jul 15 06:14:07 PM PDT 24
Peak memory 201952 kb
Host smart-49c2da18-ff1c-434d-ac53-fbcad6a4f9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459342280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2459342280
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.986375480
Short name T15
Test name
Test status
Simulation time 355021329799 ps
CPU time 143.38 seconds
Started Jul 15 06:09:26 PM PDT 24
Finished Jul 15 06:11:50 PM PDT 24
Peak memory 210568 kb
Host smart-ebde02e0-f723-406a-a6f8-3609dcf985a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986375480 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.986375480
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3748672036
Short name T305
Test name
Test status
Simulation time 461119428 ps
CPU time 1.47 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:09:26 PM PDT 24
Peak memory 201608 kb
Host smart-0dd887ac-f5cd-48ea-a916-c28a9772e42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748672036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3748672036
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.694090246
Short name T704
Test name
Test status
Simulation time 328073617863 ps
CPU time 773.89 seconds
Started Jul 15 06:09:25 PM PDT 24
Finished Jul 15 06:22:19 PM PDT 24
Peak memory 201940 kb
Host smart-92efce26-5a94-40d1-90a1-5eaa6892558d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694090246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.694090246
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2021325629
Short name T757
Test name
Test status
Simulation time 524694222709 ps
CPU time 319.87 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:14:44 PM PDT 24
Peak memory 201920 kb
Host smart-10d06aaf-7874-4525-bc34-93313f2b92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021325629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2021325629
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.610754504
Short name T242
Test name
Test status
Simulation time 164770238282 ps
CPU time 98.74 seconds
Started Jul 15 06:09:22 PM PDT 24
Finished Jul 15 06:11:01 PM PDT 24
Peak memory 201844 kb
Host smart-5cd5d4ca-5a50-4a30-800c-3a2ba76f0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610754504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.610754504
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2478804179
Short name T585
Test name
Test status
Simulation time 163044101535 ps
CPU time 97.77 seconds
Started Jul 15 06:09:22 PM PDT 24
Finished Jul 15 06:11:01 PM PDT 24
Peak memory 201892 kb
Host smart-1801ab84-1a27-42a4-b351-d8d6e1665804
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478804179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2478804179
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3061268768
Short name T589
Test name
Test status
Simulation time 489407836602 ps
CPU time 122.9 seconds
Started Jul 15 06:09:21 PM PDT 24
Finished Jul 15 06:11:24 PM PDT 24
Peak memory 201880 kb
Host smart-a1ca5c77-e9cb-4a68-ac0b-ace71ae8a43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061268768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3061268768
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.4064060825
Short name T418
Test name
Test status
Simulation time 165215249632 ps
CPU time 207.44 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 201888 kb
Host smart-77990ff2-dfa1-42f0-8f9b-4c27e6bca98b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064060825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.4064060825
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3296630290
Short name T281
Test name
Test status
Simulation time 177636070727 ps
CPU time 423.22 seconds
Started Jul 15 06:09:22 PM PDT 24
Finished Jul 15 06:16:26 PM PDT 24
Peak memory 201804 kb
Host smart-2a79ad0f-4f6a-4613-bc64-6e85a6569b8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296630290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3296630290
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.242641272
Short name T365
Test name
Test status
Simulation time 599454657541 ps
CPU time 561.38 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:18:47 PM PDT 24
Peak memory 201880 kb
Host smart-b32b2025-7cc7-4e78-97f1-c2ee29063edc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242641272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.242641272
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1558671780
Short name T440
Test name
Test status
Simulation time 154305956675 ps
CPU time 526.56 seconds
Started Jul 15 06:09:25 PM PDT 24
Finished Jul 15 06:18:12 PM PDT 24
Peak memory 202212 kb
Host smart-573eef41-1ea6-4aa7-afbd-f9c0b5701de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558671780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1558671780
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1824344484
Short name T368
Test name
Test status
Simulation time 34902430556 ps
CPU time 79.75 seconds
Started Jul 15 06:09:22 PM PDT 24
Finished Jul 15 06:10:43 PM PDT 24
Peak memory 201736 kb
Host smart-868f6322-1ae1-46ad-9149-f05e0b8a617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824344484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1824344484
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.519351331
Short name T758
Test name
Test status
Simulation time 3416468022 ps
CPU time 2.03 seconds
Started Jul 15 06:09:21 PM PDT 24
Finished Jul 15 06:09:23 PM PDT 24
Peak memory 201688 kb
Host smart-0939c816-f1a9-49cf-8cf1-161aada288a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519351331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.519351331
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1180466892
Short name T412
Test name
Test status
Simulation time 5608354789 ps
CPU time 6.44 seconds
Started Jul 15 06:09:24 PM PDT 24
Finished Jul 15 06:09:31 PM PDT 24
Peak memory 201668 kb
Host smart-d853b949-b226-4316-a10b-1e636868bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180466892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1180466892
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2932885388
Short name T147
Test name
Test status
Simulation time 496906270469 ps
CPU time 304.39 seconds
Started Jul 15 06:09:23 PM PDT 24
Finished Jul 15 06:14:28 PM PDT 24
Peak memory 201928 kb
Host smart-3e1b7b68-76d4-4de4-9034-996aec377820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932885388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2932885388
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3780022551
Short name T19
Test name
Test status
Simulation time 69389462709 ps
CPU time 126.31 seconds
Started Jul 15 06:09:22 PM PDT 24
Finished Jul 15 06:11:29 PM PDT 24
Peak memory 210500 kb
Host smart-d0560dd3-d8d8-42ac-87a3-c98869ff2d64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780022551 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3780022551
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4201208774
Short name T548
Test name
Test status
Simulation time 410153941 ps
CPU time 0.9 seconds
Started Jul 15 06:09:33 PM PDT 24
Finished Jul 15 06:09:35 PM PDT 24
Peak memory 201684 kb
Host smart-953ae342-22fe-4d35-bbc2-d5038f493559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201208774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4201208774
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2485359347
Short name T298
Test name
Test status
Simulation time 558654871654 ps
CPU time 216.72 seconds
Started Jul 15 06:09:29 PM PDT 24
Finished Jul 15 06:13:07 PM PDT 24
Peak memory 201832 kb
Host smart-ab27b47c-9e31-43f6-a7c8-aa23c68de08c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485359347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2485359347
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3958387495
Short name T247
Test name
Test status
Simulation time 344503522902 ps
CPU time 747.16 seconds
Started Jul 15 06:09:30 PM PDT 24
Finished Jul 15 06:21:57 PM PDT 24
Peak memory 201868 kb
Host smart-4043e484-05dc-45a6-b6c5-6be33bb6ad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958387495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3958387495
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2970836216
Short name T385
Test name
Test status
Simulation time 329286307507 ps
CPU time 740.5 seconds
Started Jul 15 06:09:30 PM PDT 24
Finished Jul 15 06:21:51 PM PDT 24
Peak memory 201960 kb
Host smart-42696bea-970e-41c4-8de6-3275c93b3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970836216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2970836216
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2086688171
Short name T136
Test name
Test status
Simulation time 329387187338 ps
CPU time 99.34 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:11:11 PM PDT 24
Peak memory 201840 kb
Host smart-1d03752d-ed42-42e0-a4f2-ea9602c5f30f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086688171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2086688171
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3355546317
Short name T505
Test name
Test status
Simulation time 163225721635 ps
CPU time 355.22 seconds
Started Jul 15 06:09:32 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 201940 kb
Host smart-5f8c8e15-8408-4c4f-8479-9eb6cbc92e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355546317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3355546317
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.412267107
Short name T321
Test name
Test status
Simulation time 504783250290 ps
CPU time 280.02 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:14:12 PM PDT 24
Peak memory 201892 kb
Host smart-3c3596d0-19ac-482f-81e5-9753da396f19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412267107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.412267107
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3939566509
Short name T479
Test name
Test status
Simulation time 567607060195 ps
CPU time 502.56 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:17:54 PM PDT 24
Peak memory 201820 kb
Host smart-87020b22-0780-4560-afd3-55f84a03bea6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939566509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3939566509
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1036807369
Short name T584
Test name
Test status
Simulation time 604731199390 ps
CPU time 1375.05 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:32:27 PM PDT 24
Peak memory 201864 kb
Host smart-62224f6b-1c52-4878-9560-c769b850a1c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036807369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1036807369
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.729430867
Short name T638
Test name
Test status
Simulation time 136257634303 ps
CPU time 707.18 seconds
Started Jul 15 06:09:33 PM PDT 24
Finished Jul 15 06:21:21 PM PDT 24
Peak memory 202220 kb
Host smart-2d04d1a4-e026-4e4a-9087-2c846f142298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729430867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.729430867
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3004699977
Short name T495
Test name
Test status
Simulation time 35829280341 ps
CPU time 81.99 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:10:54 PM PDT 24
Peak memory 201704 kb
Host smart-3cc4bbb2-aeea-4bbe-8770-270869099ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004699977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3004699977
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3856619154
Short name T420
Test name
Test status
Simulation time 4725311264 ps
CPU time 4.3 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:09:36 PM PDT 24
Peak memory 201688 kb
Host smart-0efb4c1e-519e-42b7-a339-c92e6e44dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856619154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3856619154
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2204380251
Short name T672
Test name
Test status
Simulation time 6118654026 ps
CPU time 3.94 seconds
Started Jul 15 06:09:31 PM PDT 24
Finished Jul 15 06:09:35 PM PDT 24
Peak memory 201708 kb
Host smart-e4715bc5-99d2-4b57-809b-4e2a7a9dac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204380251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2204380251
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2291083590
Short name T752
Test name
Test status
Simulation time 460521611294 ps
CPU time 683.56 seconds
Started Jul 15 06:09:33 PM PDT 24
Finished Jul 15 06:20:57 PM PDT 24
Peak memory 210412 kb
Host smart-848d3327-077b-4f06-8d83-69ce6caf0be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291083590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2291083590
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1224413515
Short name T284
Test name
Test status
Simulation time 35826861886 ps
CPU time 92.29 seconds
Started Jul 15 06:09:32 PM PDT 24
Finished Jul 15 06:11:04 PM PDT 24
Peak memory 210544 kb
Host smart-5203832c-9c90-4da2-93bb-cbf10ed6ac84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224413515 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1224413515
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4065415693
Short name T344
Test name
Test status
Simulation time 434588098 ps
CPU time 1.6 seconds
Started Jul 15 06:09:41 PM PDT 24
Finished Jul 15 06:09:43 PM PDT 24
Peak memory 201588 kb
Host smart-1fa38573-828c-4835-8b20-730f3b4bc23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065415693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4065415693
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1378225539
Short name T684
Test name
Test status
Simulation time 342804706204 ps
CPU time 812.04 seconds
Started Jul 15 06:09:41 PM PDT 24
Finished Jul 15 06:23:14 PM PDT 24
Peak memory 201908 kb
Host smart-a9ee9b52-4158-42ac-997c-ac5520c8bf31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378225539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1378225539
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1072144116
Short name T453
Test name
Test status
Simulation time 345792396618 ps
CPU time 816.81 seconds
Started Jul 15 06:09:38 PM PDT 24
Finished Jul 15 06:23:15 PM PDT 24
Peak memory 201888 kb
Host smart-858239b8-109c-426e-a95f-4cce5508bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072144116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1072144116
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2017758975
Short name T122
Test name
Test status
Simulation time 166539024125 ps
CPU time 350.82 seconds
Started Jul 15 06:09:40 PM PDT 24
Finished Jul 15 06:15:31 PM PDT 24
Peak memory 201876 kb
Host smart-763ec478-96df-44f9-8dad-4d981347096e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017758975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2017758975
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.371655953
Short name T759
Test name
Test status
Simulation time 166207947560 ps
CPU time 395.38 seconds
Started Jul 15 06:09:39 PM PDT 24
Finished Jul 15 06:16:15 PM PDT 24
Peak memory 201896 kb
Host smart-b5848ef8-c09a-4e87-b8d5-10d7ae30e483
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=371655953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.371655953
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2929840660
Short name T510
Test name
Test status
Simulation time 495159049773 ps
CPU time 276.31 seconds
Started Jul 15 06:09:40 PM PDT 24
Finished Jul 15 06:14:17 PM PDT 24
Peak memory 201868 kb
Host smart-d4c14488-8c5d-41c8-9baf-2f4c8828a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929840660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2929840660
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1082248345
Short name T474
Test name
Test status
Simulation time 490273808325 ps
CPU time 1059.25 seconds
Started Jul 15 06:09:39 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 201920 kb
Host smart-2e293fb9-a28e-4a6b-9264-6cb6c370733b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082248345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1082248345
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3525544490
Short name T219
Test name
Test status
Simulation time 564544708090 ps
CPU time 1176.85 seconds
Started Jul 15 06:09:41 PM PDT 24
Finished Jul 15 06:29:19 PM PDT 24
Peak memory 201968 kb
Host smart-0cfe8829-efd4-4a8a-b409-437e3e2f8629
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525544490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3525544490
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1984163691
Short name T357
Test name
Test status
Simulation time 410214504586 ps
CPU time 990 seconds
Started Jul 15 06:09:41 PM PDT 24
Finished Jul 15 06:26:12 PM PDT 24
Peak memory 201836 kb
Host smart-74ee0958-8c2a-4d56-88f8-5048e38104d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984163691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1984163691
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1967404446
Short name T195
Test name
Test status
Simulation time 105574457909 ps
CPU time 389.3 seconds
Started Jul 15 06:09:40 PM PDT 24
Finished Jul 15 06:16:10 PM PDT 24
Peak memory 202232 kb
Host smart-db234807-c94a-4525-976e-e2c011e8c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967404446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1967404446
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1830481579
Short name T723
Test name
Test status
Simulation time 22160190397 ps
CPU time 25.8 seconds
Started Jul 15 06:09:38 PM PDT 24
Finished Jul 15 06:10:05 PM PDT 24
Peak memory 201712 kb
Host smart-34e1da9b-735c-46b1-83b7-26fbaadd4938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830481579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1830481579
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1115314648
Short name T568
Test name
Test status
Simulation time 3331151749 ps
CPU time 4.39 seconds
Started Jul 15 06:09:37 PM PDT 24
Finished Jul 15 06:09:42 PM PDT 24
Peak memory 201724 kb
Host smart-6bb47c6d-0e36-4072-a871-673e50c9adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115314648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1115314648
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1059427386
Short name T503
Test name
Test status
Simulation time 5991971262 ps
CPU time 9.95 seconds
Started Jul 15 06:09:36 PM PDT 24
Finished Jul 15 06:09:47 PM PDT 24
Peak memory 201704 kb
Host smart-f41fa3bb-87f9-4aaf-96c2-26640a9b34b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059427386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1059427386
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4055003820
Short name T138
Test name
Test status
Simulation time 335895478000 ps
CPU time 196.16 seconds
Started Jul 15 06:09:39 PM PDT 24
Finished Jul 15 06:12:55 PM PDT 24
Peak memory 201892 kb
Host smart-d0589e6c-897e-4974-a973-19331e4b3e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055003820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4055003820
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3130414563
Short name T724
Test name
Test status
Simulation time 378702561 ps
CPU time 0.84 seconds
Started Jul 15 06:09:47 PM PDT 24
Finished Jul 15 06:09:48 PM PDT 24
Peak memory 201676 kb
Host smart-37a05b16-3a19-43c4-b085-b79ba922ce5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130414563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3130414563
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3593005864
Short name T613
Test name
Test status
Simulation time 163019427165 ps
CPU time 374.6 seconds
Started Jul 15 06:09:48 PM PDT 24
Finished Jul 15 06:16:03 PM PDT 24
Peak memory 201900 kb
Host smart-8ab8cc8f-defe-4a10-bf24-47aa8491590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593005864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3593005864
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.583324786
Short name T349
Test name
Test status
Simulation time 491513777221 ps
CPU time 1175.74 seconds
Started Jul 15 06:09:46 PM PDT 24
Finished Jul 15 06:29:23 PM PDT 24
Peak memory 201764 kb
Host smart-4bd13d37-eb2c-4406-ba6b-73b7a95eb391
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=583324786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.583324786
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2219873097
Short name T361
Test name
Test status
Simulation time 167998271616 ps
CPU time 105.99 seconds
Started Jul 15 06:09:39 PM PDT 24
Finished Jul 15 06:11:26 PM PDT 24
Peak memory 201948 kb
Host smart-3aaeb201-9a28-444b-b9d7-1d67fc6a3969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219873097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2219873097
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1148188314
Short name T475
Test name
Test status
Simulation time 495029979002 ps
CPU time 358.17 seconds
Started Jul 15 06:09:40 PM PDT 24
Finished Jul 15 06:15:39 PM PDT 24
Peak memory 201872 kb
Host smart-1fed9616-b1a4-4838-89e9-50097f0d232d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148188314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1148188314
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4006795698
Short name T521
Test name
Test status
Simulation time 197740814554 ps
CPU time 415.48 seconds
Started Jul 15 06:09:46 PM PDT 24
Finished Jul 15 06:16:42 PM PDT 24
Peak memory 201916 kb
Host smart-6eed422d-4a04-484e-8d0f-21fd916894f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006795698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4006795698
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4201319901
Short name T371
Test name
Test status
Simulation time 414483880298 ps
CPU time 239.23 seconds
Started Jul 15 06:09:48 PM PDT 24
Finished Jul 15 06:13:48 PM PDT 24
Peak memory 201876 kb
Host smart-f6b7498e-067d-43ac-b275-ae162969bb8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201319901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4201319901
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2702763158
Short name T528
Test name
Test status
Simulation time 63883468298 ps
CPU time 283.11 seconds
Started Jul 15 06:09:47 PM PDT 24
Finished Jul 15 06:14:31 PM PDT 24
Peak memory 202288 kb
Host smart-afc9dc04-1358-410b-953b-5a7a4c20ad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702763158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2702763158
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3194729103
Short name T797
Test name
Test status
Simulation time 41655952656 ps
CPU time 42.94 seconds
Started Jul 15 06:09:48 PM PDT 24
Finished Jul 15 06:10:31 PM PDT 24
Peak memory 201688 kb
Host smart-9bd8dee7-1a75-4714-8abc-5bc5e28ddf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194729103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3194729103
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2412370444
Short name T428
Test name
Test status
Simulation time 4435302181 ps
CPU time 3.69 seconds
Started Jul 15 06:09:50 PM PDT 24
Finished Jul 15 06:09:55 PM PDT 24
Peak memory 201820 kb
Host smart-80af70ca-0d30-4c4d-b27b-e19d4bb469c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412370444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2412370444
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1150450142
Short name T369
Test name
Test status
Simulation time 5668574897 ps
CPU time 13.78 seconds
Started Jul 15 06:09:39 PM PDT 24
Finished Jul 15 06:09:54 PM PDT 24
Peak memory 201684 kb
Host smart-d643b9df-0028-4af4-a57e-f214ee1f9c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150450142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1150450142
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.712132981
Short name T720
Test name
Test status
Simulation time 1077208795067 ps
CPU time 903.83 seconds
Started Jul 15 06:09:48 PM PDT 24
Finished Jul 15 06:24:53 PM PDT 24
Peak memory 218520 kb
Host smart-50206364-ebbb-40ad-8d58-0bd542361e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712132981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
712132981
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3056027249
Short name T149
Test name
Test status
Simulation time 920003985470 ps
CPU time 421.26 seconds
Started Jul 15 06:09:47 PM PDT 24
Finished Jul 15 06:16:49 PM PDT 24
Peak memory 210528 kb
Host smart-b99e2407-6097-458b-9a11-a3b2b62d6467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056027249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3056027249
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2237129009
Short name T569
Test name
Test status
Simulation time 354711280 ps
CPU time 0.81 seconds
Started Jul 15 06:09:53 PM PDT 24
Finished Jul 15 06:09:55 PM PDT 24
Peak memory 201644 kb
Host smart-35332903-9e9f-401b-81aa-5216b657045a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237129009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2237129009
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3530038398
Short name T789
Test name
Test status
Simulation time 344035347642 ps
CPU time 366.19 seconds
Started Jul 15 06:09:52 PM PDT 24
Finished Jul 15 06:15:59 PM PDT 24
Peak memory 201916 kb
Host smart-fe41fb38-cd20-41c0-839c-7be5b1f94c68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530038398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3530038398
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.587575764
Short name T268
Test name
Test status
Simulation time 185530989223 ps
CPU time 227.56 seconds
Started Jul 15 06:09:52 PM PDT 24
Finished Jul 15 06:13:40 PM PDT 24
Peak memory 201928 kb
Host smart-3caaefce-edd4-400b-b5e7-64458519cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587575764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.587575764
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.23932640
Short name T532
Test name
Test status
Simulation time 486663427482 ps
CPU time 1149.48 seconds
Started Jul 15 06:09:56 PM PDT 24
Finished Jul 15 06:29:06 PM PDT 24
Peak memory 201820 kb
Host smart-6956773a-7c1d-45da-b9af-f75b24f87fe1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=23932640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt
_fixed.23932640
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.16626100
Short name T480
Test name
Test status
Simulation time 161913094819 ps
CPU time 94.11 seconds
Started Jul 15 06:09:47 PM PDT 24
Finished Jul 15 06:11:22 PM PDT 24
Peak memory 201888 kb
Host smart-38a80fc7-eae8-4d7e-af57-57c54b120325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16626100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.16626100
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2767806592
Short name T327
Test name
Test status
Simulation time 328338750837 ps
CPU time 679.08 seconds
Started Jul 15 06:09:54 PM PDT 24
Finished Jul 15 06:21:14 PM PDT 24
Peak memory 201892 kb
Host smart-644f4a80-d300-4ce2-944a-e5f32f4d384e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767806592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2767806592
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3568045227
Short name T272
Test name
Test status
Simulation time 353930919171 ps
CPU time 727.87 seconds
Started Jul 15 06:09:54 PM PDT 24
Finished Jul 15 06:22:03 PM PDT 24
Peak memory 201960 kb
Host smart-772a5bcb-bd04-4c56-83b4-8c8b6d94ec0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568045227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3568045227
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2313440103
Short name T517
Test name
Test status
Simulation time 400079374320 ps
CPU time 242.36 seconds
Started Jul 15 06:09:53 PM PDT 24
Finished Jul 15 06:13:56 PM PDT 24
Peak memory 201920 kb
Host smart-b770802a-c213-4ec7-a080-8486fddc3512
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313440103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2313440103
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.548961214
Short name T531
Test name
Test status
Simulation time 105837747485 ps
CPU time 428.79 seconds
Started Jul 15 06:09:54 PM PDT 24
Finished Jul 15 06:17:04 PM PDT 24
Peak memory 201728 kb
Host smart-2ed037b1-2880-4068-a765-680af8d935dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548961214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.548961214
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1633082125
Short name T595
Test name
Test status
Simulation time 34701856527 ps
CPU time 81.22 seconds
Started Jul 15 06:09:56 PM PDT 24
Finished Jul 15 06:11:18 PM PDT 24
Peak memory 201616 kb
Host smart-00f0a6c2-0749-4158-9ef0-7f18a4d0fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633082125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1633082125
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1520475498
Short name T598
Test name
Test status
Simulation time 2978566785 ps
CPU time 7.22 seconds
Started Jul 15 06:09:54 PM PDT 24
Finished Jul 15 06:10:02 PM PDT 24
Peak memory 201212 kb
Host smart-6582d9f9-b49b-4a79-9c49-0e148fb933ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520475498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1520475498
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2015980777
Short name T741
Test name
Test status
Simulation time 5934122920 ps
CPU time 14.14 seconds
Started Jul 15 06:09:48 PM PDT 24
Finished Jul 15 06:10:02 PM PDT 24
Peak memory 201644 kb
Host smart-797c3f4a-1472-4e19-942a-a858084b84c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015980777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2015980777
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1144595441
Short name T241
Test name
Test status
Simulation time 335971504109 ps
CPU time 747.48 seconds
Started Jul 15 06:09:53 PM PDT 24
Finished Jul 15 06:22:22 PM PDT 24
Peak memory 201880 kb
Host smart-27a17241-c770-4e19-a38d-4e4839865bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144595441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1144595441
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.670026445
Short name T599
Test name
Test status
Simulation time 42873314256 ps
CPU time 52.77 seconds
Started Jul 15 06:09:55 PM PDT 24
Finished Jul 15 06:10:48 PM PDT 24
Peak memory 202020 kb
Host smart-cf793f47-844e-453a-9a37-6e3c6eb748e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670026445 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.670026445
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.273097290
Short name T408
Test name
Test status
Simulation time 458828556 ps
CPU time 0.88 seconds
Started Jul 15 06:10:07 PM PDT 24
Finished Jul 15 06:10:09 PM PDT 24
Peak memory 201608 kb
Host smart-4d00d22f-a592-4f75-8ff4-d51ea6c0b2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273097290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.273097290
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3247321404
Short name T647
Test name
Test status
Simulation time 354101238617 ps
CPU time 246.14 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:14:09 PM PDT 24
Peak memory 201900 kb
Host smart-c9069157-fbd2-41ee-a47e-c86c762a048f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247321404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3247321404
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1840098494
Short name T285
Test name
Test status
Simulation time 204144885125 ps
CPU time 166.15 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:12:49 PM PDT 24
Peak memory 201824 kb
Host smart-b4ea0ad4-7433-4006-8bbe-22fc1dcbb475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840098494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1840098494
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2548922420
Short name T198
Test name
Test status
Simulation time 173680668212 ps
CPU time 63.86 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:11:07 PM PDT 24
Peak memory 201972 kb
Host smart-d11035e7-e638-458e-9a88-3221970ce1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548922420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2548922420
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2885161854
Short name T596
Test name
Test status
Simulation time 496105151491 ps
CPU time 594.4 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:19:57 PM PDT 24
Peak memory 201892 kb
Host smart-4a41061b-4a4a-4dbf-a804-60edd6816692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885161854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2885161854
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1457740004
Short name T657
Test name
Test status
Simulation time 167656494557 ps
CPU time 90.99 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:11:34 PM PDT 24
Peak memory 201880 kb
Host smart-93a6bf4d-ad94-47d9-a0a7-ccf4227ab42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457740004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1457740004
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1854378254
Short name T781
Test name
Test status
Simulation time 331804268259 ps
CPU time 182.53 seconds
Started Jul 15 06:10:06 PM PDT 24
Finished Jul 15 06:13:10 PM PDT 24
Peak memory 201884 kb
Host smart-1e0db637-19e7-46d9-b225-925cec155367
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854378254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1854378254
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1285894720
Short name T702
Test name
Test status
Simulation time 370136564501 ps
CPU time 223.74 seconds
Started Jul 15 06:10:04 PM PDT 24
Finished Jul 15 06:13:48 PM PDT 24
Peak memory 201880 kb
Host smart-dd8d54fc-e8bb-4d43-98ea-aec793a5a8f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285894720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1285894720
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2039671758
Short name T633
Test name
Test status
Simulation time 615444012187 ps
CPU time 1323.52 seconds
Started Jul 15 06:10:03 PM PDT 24
Finished Jul 15 06:32:07 PM PDT 24
Peak memory 201904 kb
Host smart-4bd02aa8-162c-4746-b700-50d701c8602b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039671758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2039671758
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2239053750
Short name T737
Test name
Test status
Simulation time 96247883715 ps
CPU time 390.79 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:16:33 PM PDT 24
Peak memory 202224 kb
Host smart-967935de-1b18-45f7-b75b-3fc69df87273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239053750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2239053750
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3981362843
Short name T519
Test name
Test status
Simulation time 26715405186 ps
CPU time 24.63 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:10:27 PM PDT 24
Peak memory 201672 kb
Host smart-55bab732-2865-4739-a871-c52c2bc59fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981362843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3981362843
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2671875239
Short name T587
Test name
Test status
Simulation time 5188967114 ps
CPU time 12.48 seconds
Started Jul 15 06:10:02 PM PDT 24
Finished Jul 15 06:10:15 PM PDT 24
Peak memory 201712 kb
Host smart-846bd3fd-61d3-4684-8910-f6166a0b4228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671875239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2671875239
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2711445836
Short name T668
Test name
Test status
Simulation time 5840630298 ps
CPU time 7.64 seconds
Started Jul 15 06:10:01 PM PDT 24
Finished Jul 15 06:10:09 PM PDT 24
Peak memory 201744 kb
Host smart-b1a10c16-c22a-4502-a6c0-6b4e37b592a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711445836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2711445836
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1859289698
Short name T303
Test name
Test status
Simulation time 317405350591 ps
CPU time 1103.66 seconds
Started Jul 15 06:10:10 PM PDT 24
Finished Jul 15 06:28:34 PM PDT 24
Peak memory 210364 kb
Host smart-604704cb-fed1-4a27-a0c3-9d3ea6f96fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859289698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1859289698
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1997647389
Short name T35
Test name
Test status
Simulation time 35787105420 ps
CPU time 100.49 seconds
Started Jul 15 06:10:01 PM PDT 24
Finished Jul 15 06:11:42 PM PDT 24
Peak memory 211468 kb
Host smart-43667145-3be1-4f57-b847-fc4d4bcbc8b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997647389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1997647389
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1478204004
Short name T579
Test name
Test status
Simulation time 345191403 ps
CPU time 1.42 seconds
Started Jul 15 06:10:15 PM PDT 24
Finished Jul 15 06:10:17 PM PDT 24
Peak memory 201632 kb
Host smart-18c04eb6-14c9-4c0b-933b-289a6f96eb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478204004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1478204004
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1799857388
Short name T494
Test name
Test status
Simulation time 165513179323 ps
CPU time 171.44 seconds
Started Jul 15 06:10:07 PM PDT 24
Finished Jul 15 06:12:59 PM PDT 24
Peak memory 201944 kb
Host smart-6155f92a-2d60-4a3c-9d7c-aaf286a0a283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799857388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1799857388
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1366837924
Short name T478
Test name
Test status
Simulation time 331096046160 ps
CPU time 403.28 seconds
Started Jul 15 06:10:11 PM PDT 24
Finished Jul 15 06:16:54 PM PDT 24
Peak memory 201920 kb
Host smart-001a56a8-4a62-4db0-8bd4-837727f4906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366837924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1366837924
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.31426275
Short name T794
Test name
Test status
Simulation time 168329665896 ps
CPU time 258.07 seconds
Started Jul 15 06:10:11 PM PDT 24
Finished Jul 15 06:14:29 PM PDT 24
Peak memory 201916 kb
Host smart-fc4f9d93-47be-49b1-8a44-10b013c42759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31426275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.31426275
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2577696841
Short name T5
Test name
Test status
Simulation time 159826456159 ps
CPU time 94.28 seconds
Started Jul 15 06:10:10 PM PDT 24
Finished Jul 15 06:11:45 PM PDT 24
Peak memory 201844 kb
Host smart-2035bd81-e3a8-4c1d-a6a3-36d818fa467e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577696841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2577696841
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2557093358
Short name T155
Test name
Test status
Simulation time 486996031064 ps
CPU time 1083.33 seconds
Started Jul 15 06:10:09 PM PDT 24
Finished Jul 15 06:28:13 PM PDT 24
Peak memory 201944 kb
Host smart-890cb50c-89e4-48f9-b028-6742e3c4d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557093358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2557093358
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.768883831
Short name T339
Test name
Test status
Simulation time 487139962172 ps
CPU time 1054.21 seconds
Started Jul 15 06:10:10 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 201872 kb
Host smart-12eb669e-457b-48eb-a6a1-57073cf59853
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=768883831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.768883831
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1143151104
Short name T177
Test name
Test status
Simulation time 355810726470 ps
CPU time 203.45 seconds
Started Jul 15 06:10:08 PM PDT 24
Finished Jul 15 06:13:32 PM PDT 24
Peak memory 201824 kb
Host smart-4438be77-c681-4e0a-bead-4a40e43a36a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143151104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1143151104
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1514033842
Short name T359
Test name
Test status
Simulation time 391304592437 ps
CPU time 893.27 seconds
Started Jul 15 06:10:09 PM PDT 24
Finished Jul 15 06:25:03 PM PDT 24
Peak memory 201804 kb
Host smart-c6006fc7-f9c6-4c1e-b841-0616b97f930f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514033842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1514033842
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4254121796
Short name T564
Test name
Test status
Simulation time 46992119492 ps
CPU time 53.23 seconds
Started Jul 15 06:10:09 PM PDT 24
Finished Jul 15 06:11:02 PM PDT 24
Peak memory 201680 kb
Host smart-5308bcd1-9f65-4f06-b94b-84bfb4253c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254121796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4254121796
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3903543959
Short name T366
Test name
Test status
Simulation time 3684752216 ps
CPU time 8.82 seconds
Started Jul 15 06:10:08 PM PDT 24
Finished Jul 15 06:10:18 PM PDT 24
Peak memory 201644 kb
Host smart-2814160d-a437-4d7b-9ba4-8198f74f158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903543959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3903543959
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1232474516
Short name T322
Test name
Test status
Simulation time 5797609758 ps
CPU time 12.41 seconds
Started Jul 15 06:10:09 PM PDT 24
Finished Jul 15 06:10:22 PM PDT 24
Peak memory 201588 kb
Host smart-4b8c0a7c-0d3b-4d0e-a602-9ff5a66af9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232474516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1232474516
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1689925910
Short name T405
Test name
Test status
Simulation time 167735470014 ps
CPU time 95.74 seconds
Started Jul 15 06:10:17 PM PDT 24
Finished Jul 15 06:11:53 PM PDT 24
Peak memory 201944 kb
Host smart-cb839c10-7fd8-4f63-a73a-9d341bfeba39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689925910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1689925910
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.656921055
Short name T708
Test name
Test status
Simulation time 139629059784 ps
CPU time 88.45 seconds
Started Jul 15 06:10:08 PM PDT 24
Finished Jul 15 06:11:36 PM PDT 24
Peak memory 218768 kb
Host smart-97c635b9-0ed9-4136-bc27-da0dff9f1372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656921055 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.656921055
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4141687197
Short name T545
Test name
Test status
Simulation time 331083587 ps
CPU time 1.35 seconds
Started Jul 15 06:10:23 PM PDT 24
Finished Jul 15 06:10:25 PM PDT 24
Peak memory 201632 kb
Host smart-0f983a33-58ab-4093-a98c-6b98526ad1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141687197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4141687197
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.559461733
Short name T396
Test name
Test status
Simulation time 178465866871 ps
CPU time 422.64 seconds
Started Jul 15 06:10:16 PM PDT 24
Finished Jul 15 06:17:19 PM PDT 24
Peak memory 201884 kb
Host smart-bf964398-9790-40e6-9ec1-44fe6157352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559461733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.559461733
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1103986821
Short name T722
Test name
Test status
Simulation time 324788255255 ps
CPU time 148.56 seconds
Started Jul 15 06:10:14 PM PDT 24
Finished Jul 15 06:12:43 PM PDT 24
Peak memory 201920 kb
Host smart-0fc68df5-b1ea-41eb-8848-093324c87a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103986821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1103986821
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2821879235
Short name T148
Test name
Test status
Simulation time 162262845031 ps
CPU time 147.64 seconds
Started Jul 15 06:10:16 PM PDT 24
Finished Jul 15 06:12:44 PM PDT 24
Peak memory 201872 kb
Host smart-b3757eb6-8bc8-4b23-a6cb-023082904ce5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821879235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2821879235
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1758120062
Short name T570
Test name
Test status
Simulation time 162349644812 ps
CPU time 100.62 seconds
Started Jul 15 06:10:16 PM PDT 24
Finished Jul 15 06:11:57 PM PDT 24
Peak memory 201852 kb
Host smart-8db9b1d4-2a12-4d41-a1c2-be83d066ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758120062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1758120062
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.4030280547
Short name T315
Test name
Test status
Simulation time 494936285008 ps
CPU time 569.63 seconds
Started Jul 15 06:10:15 PM PDT 24
Finished Jul 15 06:19:45 PM PDT 24
Peak memory 201836 kb
Host smart-1d8487e2-31b1-43e4-920f-36ae4f4743e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030280547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.4030280547
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2200620777
Short name T670
Test name
Test status
Simulation time 345575898571 ps
CPU time 396.04 seconds
Started Jul 15 06:10:17 PM PDT 24
Finished Jul 15 06:16:53 PM PDT 24
Peak memory 201972 kb
Host smart-2b8c0bcd-3974-465a-b050-814aa65921fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200620777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2200620777
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3942315476
Short name T560
Test name
Test status
Simulation time 216204370239 ps
CPU time 495.39 seconds
Started Jul 15 06:10:15 PM PDT 24
Finished Jul 15 06:18:30 PM PDT 24
Peak memory 201892 kb
Host smart-c4e52fc2-1a5d-4021-b3ca-d44f7f478096
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942315476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3942315476
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1968333253
Short name T620
Test name
Test status
Simulation time 117361690704 ps
CPU time 474.13 seconds
Started Jul 15 06:10:22 PM PDT 24
Finished Jul 15 06:18:17 PM PDT 24
Peak memory 202284 kb
Host smart-a0e173a4-b4bd-41bd-9703-309897028310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968333253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1968333253
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.161728448
Short name T360
Test name
Test status
Simulation time 40311009848 ps
CPU time 82.16 seconds
Started Jul 15 06:10:21 PM PDT 24
Finished Jul 15 06:11:44 PM PDT 24
Peak memory 201728 kb
Host smart-b1d92120-d049-455f-ba34-8e6121acd1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161728448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.161728448
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2790688089
Short name T347
Test name
Test status
Simulation time 5341360907 ps
CPU time 3.06 seconds
Started Jul 15 06:10:23 PM PDT 24
Finished Jul 15 06:10:26 PM PDT 24
Peak memory 201672 kb
Host smart-bafd1a62-01f9-4351-a9a6-c9f438677b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790688089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2790688089
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1265498141
Short name T332
Test name
Test status
Simulation time 5853730793 ps
CPU time 4.31 seconds
Started Jul 15 06:10:13 PM PDT 24
Finished Jul 15 06:10:18 PM PDT 24
Peak memory 201696 kb
Host smart-08b0715d-538f-4a20-b33f-cf66cf5a1e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265498141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1265498141
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1243692168
Short name T43
Test name
Test status
Simulation time 355510424096 ps
CPU time 211.16 seconds
Started Jul 15 06:10:25 PM PDT 24
Finished Jul 15 06:13:56 PM PDT 24
Peak memory 201932 kb
Host smart-abe8831f-810e-4d23-b49a-1fe2031a1402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243692168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1243692168
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3092055110
Short name T688
Test name
Test status
Simulation time 61856264530 ps
CPU time 127.52 seconds
Started Jul 15 06:10:23 PM PDT 24
Finished Jul 15 06:12:31 PM PDT 24
Peak memory 210296 kb
Host smart-f463a5ed-4c82-4685-9735-65a2da4e3878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092055110 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3092055110
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2333846435
Short name T762
Test name
Test status
Simulation time 363010704 ps
CPU time 0.9 seconds
Started Jul 15 06:07:08 PM PDT 24
Finished Jul 15 06:07:10 PM PDT 24
Peak memory 201644 kb
Host smart-dcd453ad-0193-4264-9462-c1d18732c636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333846435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2333846435
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3883054500
Short name T283
Test name
Test status
Simulation time 552272354463 ps
CPU time 1133 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 201876 kb
Host smart-f9309679-49ed-4d9e-b842-b39bcee8e141
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883054500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3883054500
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4119908176
Short name T614
Test name
Test status
Simulation time 184426165011 ps
CPU time 424.24 seconds
Started Jul 15 06:07:05 PM PDT 24
Finished Jul 15 06:14:11 PM PDT 24
Peak memory 201812 kb
Host smart-54269e57-3024-4cca-b6d9-124e60b9593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119908176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4119908176
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.308989675
Short name T402
Test name
Test status
Simulation time 166085190276 ps
CPU time 311.76 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:12:17 PM PDT 24
Peak memory 201932 kb
Host smart-9cebdeab-384e-494f-9067-2c63805c5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308989675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.308989675
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2847182249
Short name T751
Test name
Test status
Simulation time 164675407653 ps
CPU time 396.77 seconds
Started Jul 15 06:07:05 PM PDT 24
Finished Jul 15 06:13:43 PM PDT 24
Peak memory 201896 kb
Host smart-fb53b6c4-20c2-4f4a-b66c-521f696c1f54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847182249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2847182249
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.67404974
Short name T604
Test name
Test status
Simulation time 490469439505 ps
CPU time 319.4 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:12:24 PM PDT 24
Peak memory 201948 kb
Host smart-45c073d0-93a8-48ee-ac82-11055ba114d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67404974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.67404974
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.831124614
Short name T382
Test name
Test status
Simulation time 491356414335 ps
CPU time 1085.58 seconds
Started Jul 15 06:07:10 PM PDT 24
Finished Jul 15 06:25:16 PM PDT 24
Peak memory 201868 kb
Host smart-16ef0c6b-62b6-424b-9468-f747668fd43f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=831124614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.831124614
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3132742222
Short name T411
Test name
Test status
Simulation time 610230012823 ps
CPU time 918.18 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:22:26 PM PDT 24
Peak memory 201828 kb
Host smart-5f58ed8f-c759-49cb-b766-b03515e07b06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132742222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3132742222
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1419084417
Short name T772
Test name
Test status
Simulation time 120257776008 ps
CPU time 441.51 seconds
Started Jul 15 06:07:08 PM PDT 24
Finished Jul 15 06:14:31 PM PDT 24
Peak memory 202212 kb
Host smart-db0918b4-0fc2-44f0-ace4-3878cb7538e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419084417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1419084417
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2833437653
Short name T463
Test name
Test status
Simulation time 27687465402 ps
CPU time 15.61 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:07:24 PM PDT 24
Peak memory 201624 kb
Host smart-652a6c4e-ac86-4540-9e05-78149997d218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833437653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2833437653
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2659082487
Short name T442
Test name
Test status
Simulation time 4705027415 ps
CPU time 6.59 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:07:11 PM PDT 24
Peak memory 201700 kb
Host smart-b92198cb-4ee1-4bef-a754-ed72e5de11c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659082487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2659082487
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3456636010
Short name T64
Test name
Test status
Simulation time 4471048484 ps
CPU time 3.5 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:07:15 PM PDT 24
Peak memory 217124 kb
Host smart-e429e407-d106-474c-ab24-93ccb20a54a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456636010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3456636010
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3460015846
Short name T430
Test name
Test status
Simulation time 5709653964 ps
CPU time 2.26 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:07:11 PM PDT 24
Peak memory 201660 kb
Host smart-c5cf3346-b2b1-4ef0-aa87-33cd2cea560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460015846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3460015846
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.880741072
Short name T16
Test name
Test status
Simulation time 114374137859 ps
CPU time 181.21 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:10:07 PM PDT 24
Peak memory 210464 kb
Host smart-a379fcf9-c3e1-4a88-bdca-89d15f9ed71a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880741072 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.880741072
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2567140961
Short name T778
Test name
Test status
Simulation time 453027364 ps
CPU time 0.87 seconds
Started Jul 15 06:10:31 PM PDT 24
Finished Jul 15 06:10:32 PM PDT 24
Peak memory 201588 kb
Host smart-e697163e-7c85-44f6-b37a-bc6b1509f53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567140961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2567140961
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3562334916
Short name T546
Test name
Test status
Simulation time 366862947393 ps
CPU time 409.44 seconds
Started Jul 15 06:10:28 PM PDT 24
Finished Jul 15 06:17:18 PM PDT 24
Peak memory 201820 kb
Host smart-031be2f8-8ca7-42c6-bdea-e18cc452581e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562334916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3562334916
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3906831460
Short name T205
Test name
Test status
Simulation time 162345291972 ps
CPU time 381.1 seconds
Started Jul 15 06:10:31 PM PDT 24
Finished Jul 15 06:16:52 PM PDT 24
Peak memory 201920 kb
Host smart-6cbb7127-4abc-4cf0-acf2-cffa96276022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906831460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3906831460
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.183168986
Short name T290
Test name
Test status
Simulation time 167677833813 ps
CPU time 51.96 seconds
Started Jul 15 06:10:22 PM PDT 24
Finished Jul 15 06:11:14 PM PDT 24
Peak memory 201880 kb
Host smart-0c152156-9e1e-49d0-a11d-cdf6c6a2e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183168986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.183168986
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1785294953
Short name T618
Test name
Test status
Simulation time 486287084665 ps
CPU time 1026.82 seconds
Started Jul 15 06:10:24 PM PDT 24
Finished Jul 15 06:27:31 PM PDT 24
Peak memory 201820 kb
Host smart-8f9f3cfd-b685-404d-9245-246e37522774
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785294953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1785294953
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.157322416
Short name T582
Test name
Test status
Simulation time 479809494878 ps
CPU time 1026.19 seconds
Started Jul 15 06:10:20 PM PDT 24
Finished Jul 15 06:27:27 PM PDT 24
Peak memory 201896 kb
Host smart-f0781f46-b411-42d6-91d9-d92f813ffe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157322416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.157322416
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2855323335
Short name T591
Test name
Test status
Simulation time 167476790324 ps
CPU time 351.44 seconds
Started Jul 15 06:10:25 PM PDT 24
Finished Jul 15 06:16:16 PM PDT 24
Peak memory 201884 kb
Host smart-29aac25c-796f-4395-9910-7192da39f4f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855323335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2855323335
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.884193293
Short name T139
Test name
Test status
Simulation time 557548230657 ps
CPU time 159.97 seconds
Started Jul 15 06:10:25 PM PDT 24
Finished Jul 15 06:13:06 PM PDT 24
Peak memory 201968 kb
Host smart-6505e811-384f-442a-9f5c-026f9ee7a87d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884193293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.884193293
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2199144254
Short name T328
Test name
Test status
Simulation time 595171524208 ps
CPU time 626.71 seconds
Started Jul 15 06:10:28 PM PDT 24
Finished Jul 15 06:20:56 PM PDT 24
Peak memory 201884 kb
Host smart-55e11bc4-7ec2-4c05-b6c5-b0364759bd97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199144254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2199144254
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.116457253
Short name T26
Test name
Test status
Simulation time 100841574185 ps
CPU time 333.77 seconds
Started Jul 15 06:10:28 PM PDT 24
Finished Jul 15 06:16:03 PM PDT 24
Peak memory 202248 kb
Host smart-9fc2bb44-b8da-4e50-81c8-9e72b1091753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116457253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.116457253
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3537369574
Short name T581
Test name
Test status
Simulation time 45368168997 ps
CPU time 50.45 seconds
Started Jul 15 06:10:30 PM PDT 24
Finished Jul 15 06:11:21 PM PDT 24
Peak memory 201736 kb
Host smart-aa3285c9-c492-410c-9904-4f16756ecbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537369574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3537369574
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3866940392
Short name T42
Test name
Test status
Simulation time 3332232484 ps
CPU time 2.49 seconds
Started Jul 15 06:10:31 PM PDT 24
Finished Jul 15 06:10:34 PM PDT 24
Peak memory 201732 kb
Host smart-8268e94e-2f53-44a4-b6cc-43fff29f3ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866940392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3866940392
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2322292481
Short name T99
Test name
Test status
Simulation time 5950965039 ps
CPU time 4.39 seconds
Started Jul 15 06:10:24 PM PDT 24
Finished Jul 15 06:10:29 PM PDT 24
Peak memory 201708 kb
Host smart-4576fa81-89e3-4f40-b5be-ff864e10cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322292481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2322292481
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.401988120
Short name T202
Test name
Test status
Simulation time 527545968987 ps
CPU time 240.89 seconds
Started Jul 15 06:10:33 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 201932 kb
Host smart-ac87c46c-fb52-4694-a32d-b0cc718d3826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401988120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
401988120
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2595406796
Short name T619
Test name
Test status
Simulation time 63814068606 ps
CPU time 60.86 seconds
Started Jul 15 06:10:30 PM PDT 24
Finished Jul 15 06:11:31 PM PDT 24
Peak memory 210200 kb
Host smart-a01d93e7-02dd-42a2-a8cb-ba4f1387f29b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595406796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2595406796
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.505194600
Short name T499
Test name
Test status
Simulation time 298240253 ps
CPU time 0.94 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:10:47 PM PDT 24
Peak memory 201608 kb
Host smart-7a9f4e35-d245-4543-b73c-e8e6d76f3161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505194600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.505194600
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3052468575
Short name T423
Test name
Test status
Simulation time 180774656029 ps
CPU time 347.07 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:16:33 PM PDT 24
Peak memory 201872 kb
Host smart-d1d777dc-cc9b-4734-bbc0-fd8584c4d5a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052468575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3052468575
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2372059638
Short name T266
Test name
Test status
Simulation time 494415906114 ps
CPU time 1205.36 seconds
Started Jul 15 06:10:40 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 201888 kb
Host smart-8f4519ee-8fdd-406a-9a71-af9a204e056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372059638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2372059638
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1970183429
Short name T433
Test name
Test status
Simulation time 490034011121 ps
CPU time 1006.06 seconds
Started Jul 15 06:10:39 PM PDT 24
Finished Jul 15 06:27:26 PM PDT 24
Peak memory 201832 kb
Host smart-e325be55-5506-48e8-8285-f60999b3da84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970183429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1970183429
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.265822684
Short name T342
Test name
Test status
Simulation time 165307553163 ps
CPU time 382.5 seconds
Started Jul 15 06:10:37 PM PDT 24
Finished Jul 15 06:17:00 PM PDT 24
Peak memory 201948 kb
Host smart-fa5a16ec-2e51-4434-b995-823642607dcd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=265822684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.265822684
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.412638184
Short name T200
Test name
Test status
Simulation time 180875565079 ps
CPU time 403.58 seconds
Started Jul 15 06:10:36 PM PDT 24
Finished Jul 15 06:17:20 PM PDT 24
Peak memory 201952 kb
Host smart-b05951a0-8960-49b2-b9b5-ad3f0cdb5cc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412638184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.412638184
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2780521502
Short name T796
Test name
Test status
Simulation time 608797268284 ps
CPU time 1297.96 seconds
Started Jul 15 06:10:39 PM PDT 24
Finished Jul 15 06:32:17 PM PDT 24
Peak memory 201876 kb
Host smart-17780667-15ee-4af5-b54d-074f18949fd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780521502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2780521502
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1516672536
Short name T304
Test name
Test status
Simulation time 103980066119 ps
CPU time 361.13 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:16:47 PM PDT 24
Peak memory 202104 kb
Host smart-5b2c0a7d-b202-4b1b-a779-3ef594795da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516672536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1516672536
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.328297974
Short name T514
Test name
Test status
Simulation time 41028681436 ps
CPU time 88.69 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:12:15 PM PDT 24
Peak memory 201688 kb
Host smart-cbacf27b-0c1c-47f6-b151-56f92e7e94fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328297974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.328297974
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3236765064
Short name T380
Test name
Test status
Simulation time 3873282309 ps
CPU time 1.15 seconds
Started Jul 15 06:10:48 PM PDT 24
Finished Jul 15 06:10:49 PM PDT 24
Peak memory 201696 kb
Host smart-242fa3b1-63b7-4d46-86ba-22e182a64709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236765064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3236765064
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3344367704
Short name T629
Test name
Test status
Simulation time 5581808537 ps
CPU time 4.12 seconds
Started Jul 15 06:10:28 PM PDT 24
Finished Jul 15 06:10:33 PM PDT 24
Peak memory 201532 kb
Host smart-edf519fa-d0f6-4d8d-b4b8-628711804027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344367704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3344367704
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2530036939
Short name T664
Test name
Test status
Simulation time 329654104739 ps
CPU time 218.75 seconds
Started Jul 15 06:10:44 PM PDT 24
Finished Jul 15 06:14:23 PM PDT 24
Peak memory 201884 kb
Host smart-0b4137a2-42e0-4330-a062-50802c9f980e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530036939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2530036939
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.963258574
Short name T507
Test name
Test status
Simulation time 544695655100 ps
CPU time 356.04 seconds
Started Jul 15 06:10:48 PM PDT 24
Finished Jul 15 06:16:44 PM PDT 24
Peak memory 210516 kb
Host smart-99a66389-deeb-422e-8cc7-ee1792292176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963258574 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.963258574
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.683038819
Short name T456
Test name
Test status
Simulation time 339391753 ps
CPU time 0.81 seconds
Started Jul 15 06:11:02 PM PDT 24
Finished Jul 15 06:11:03 PM PDT 24
Peak memory 201776 kb
Host smart-a6505860-01cc-4fb4-8ef8-74036df6e0dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683038819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.683038819
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2876877440
Short name T454
Test name
Test status
Simulation time 181489429207 ps
CPU time 94.33 seconds
Started Jul 15 06:10:46 PM PDT 24
Finished Jul 15 06:12:21 PM PDT 24
Peak memory 201960 kb
Host smart-6ffd2c97-7ac6-4b51-903f-3fbbb260e6d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876877440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2876877440
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2345820509
Short name T432
Test name
Test status
Simulation time 527226019765 ps
CPU time 306.27 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:15:53 PM PDT 24
Peak memory 201916 kb
Host smart-48556495-a883-4e12-8988-86fdf061b7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345820509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2345820509
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.774618934
Short name T141
Test name
Test status
Simulation time 492284648729 ps
CPU time 1021.65 seconds
Started Jul 15 06:10:46 PM PDT 24
Finished Jul 15 06:27:48 PM PDT 24
Peak memory 201876 kb
Host smart-92dbdec5-102a-4182-bfc9-16ed73ccca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774618934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.774618934
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3630490116
Short name T398
Test name
Test status
Simulation time 494455963953 ps
CPU time 936.18 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:26:21 PM PDT 24
Peak memory 201912 kb
Host smart-439637f6-92c5-4805-a9a3-2c8f3d5bc76f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630490116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3630490116
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1554938099
Short name T663
Test name
Test status
Simulation time 163746322089 ps
CPU time 95.42 seconds
Started Jul 15 06:10:47 PM PDT 24
Finished Jul 15 06:12:23 PM PDT 24
Peak memory 201872 kb
Host smart-cdc7f13e-abc0-451b-8e1a-ea6804614159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554938099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1554938099
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.839399513
Short name T547
Test name
Test status
Simulation time 162998575717 ps
CPU time 171.31 seconds
Started Jul 15 06:10:46 PM PDT 24
Finished Jul 15 06:13:38 PM PDT 24
Peak memory 201820 kb
Host smart-d7fa8e25-f535-4912-a621-bc33667bae7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=839399513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.839399513
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.243315617
Short name T238
Test name
Test status
Simulation time 386600500002 ps
CPU time 125.49 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:12:51 PM PDT 24
Peak memory 201840 kb
Host smart-2cc35963-7b57-43bf-a5cb-d8b623ab741f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243315617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.243315617
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3120998923
Short name T689
Test name
Test status
Simulation time 604555164495 ps
CPU time 1273.25 seconds
Started Jul 15 06:10:46 PM PDT 24
Finished Jul 15 06:32:00 PM PDT 24
Peak memory 201816 kb
Host smart-e2ab27a8-69fc-45c2-9a3e-35618e69e45b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120998923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3120998923
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.201705783
Short name T52
Test name
Test status
Simulation time 113230895280 ps
CPU time 407.92 seconds
Started Jul 15 06:10:53 PM PDT 24
Finished Jul 15 06:17:41 PM PDT 24
Peak memory 202292 kb
Host smart-0857aafb-e788-4c71-86df-66b82506f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201705783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.201705783
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1352133238
Short name T632
Test name
Test status
Simulation time 36859694404 ps
CPU time 77.46 seconds
Started Jul 15 06:10:46 PM PDT 24
Finished Jul 15 06:12:04 PM PDT 24
Peak memory 201688 kb
Host smart-8f08c350-3063-4ffa-b28b-177149e106a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352133238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1352133238
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.270001324
Short name T686
Test name
Test status
Simulation time 3679366513 ps
CPU time 1.77 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:10:48 PM PDT 24
Peak memory 201716 kb
Host smart-55d7d452-4b7f-46af-a7ff-c46601015ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270001324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.270001324
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1362227348
Short name T695
Test name
Test status
Simulation time 6151416695 ps
CPU time 14.41 seconds
Started Jul 15 06:10:45 PM PDT 24
Finished Jul 15 06:11:01 PM PDT 24
Peak memory 201708 kb
Host smart-1f29a689-8cdb-4c75-90a7-33abcdcbddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362227348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1362227348
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3752369716
Short name T791
Test name
Test status
Simulation time 351022382112 ps
CPU time 830.42 seconds
Started Jul 15 06:10:53 PM PDT 24
Finished Jul 15 06:24:44 PM PDT 24
Peak memory 213712 kb
Host smart-b4e6c8af-1616-495b-8ee6-6cb23802c776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752369716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3752369716
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2503029455
Short name T37
Test name
Test status
Simulation time 84361906467 ps
CPU time 367.61 seconds
Started Jul 15 06:10:53 PM PDT 24
Finished Jul 15 06:17:00 PM PDT 24
Peak memory 211564 kb
Host smart-dbc8637e-1bad-404a-a9e0-6539ed7d75e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503029455 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2503029455
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2318202434
Short name T314
Test name
Test status
Simulation time 439213223 ps
CPU time 0.85 seconds
Started Jul 15 06:10:59 PM PDT 24
Finished Jul 15 06:11:00 PM PDT 24
Peak memory 201592 kb
Host smart-977205ee-dbe4-420a-bbc4-f5c8d0a2dc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318202434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2318202434
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.268120986
Short name T271
Test name
Test status
Simulation time 166084845528 ps
CPU time 362.6 seconds
Started Jul 15 06:11:02 PM PDT 24
Finished Jul 15 06:17:05 PM PDT 24
Peak memory 202084 kb
Host smart-c29868f4-ed5f-48ed-8b1f-7340024d3544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268120986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.268120986
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.260868373
Short name T771
Test name
Test status
Simulation time 336697750687 ps
CPU time 733.7 seconds
Started Jul 15 06:10:53 PM PDT 24
Finished Jul 15 06:23:08 PM PDT 24
Peak memory 201868 kb
Host smart-ee0b743e-265c-479b-977f-67e119f9a101
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=260868373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.260868373
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3658130868
Short name T391
Test name
Test status
Simulation time 325177315188 ps
CPU time 181.05 seconds
Started Jul 15 06:10:53 PM PDT 24
Finished Jul 15 06:13:54 PM PDT 24
Peak memory 201916 kb
Host smart-affef1c8-b86d-4c87-83c8-0af5b7f4b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658130868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3658130868
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.814488153
Short name T610
Test name
Test status
Simulation time 325846135867 ps
CPU time 696.87 seconds
Started Jul 15 06:10:54 PM PDT 24
Finished Jul 15 06:22:31 PM PDT 24
Peak memory 201912 kb
Host smart-77526e14-b6a5-436a-86a9-e1c1a4594f4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=814488153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.814488153
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.831564910
Short name T325
Test name
Test status
Simulation time 603507425123 ps
CPU time 262.06 seconds
Started Jul 15 06:10:55 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 201880 kb
Host smart-b7f444b5-d09e-440c-89eb-53366bdf73ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831564910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.831564910
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2152186405
Short name T190
Test name
Test status
Simulation time 72671422145 ps
CPU time 383.48 seconds
Started Jul 15 06:11:02 PM PDT 24
Finished Jul 15 06:17:26 PM PDT 24
Peak memory 202172 kb
Host smart-c030bf6f-ee2b-4c37-af6a-7b36cf4d422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152186405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2152186405
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4169577869
Short name T364
Test name
Test status
Simulation time 37445680521 ps
CPU time 46.27 seconds
Started Jul 15 06:10:56 PM PDT 24
Finished Jul 15 06:11:43 PM PDT 24
Peak memory 201688 kb
Host smart-6b4bd569-6b11-47c6-ac86-3ce9c3d89e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169577869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4169577869
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2199558019
Short name T640
Test name
Test status
Simulation time 5035391113 ps
CPU time 6 seconds
Started Jul 15 06:10:55 PM PDT 24
Finished Jul 15 06:11:01 PM PDT 24
Peak memory 201728 kb
Host smart-9110bfbf-aff0-46b9-8d0f-4550c7df652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199558019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2199558019
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3078990918
Short name T621
Test name
Test status
Simulation time 5744857949 ps
CPU time 4.04 seconds
Started Jul 15 06:10:50 PM PDT 24
Finished Jul 15 06:10:55 PM PDT 24
Peak memory 201728 kb
Host smart-88c904fa-3403-4313-8225-0970a111d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078990918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3078990918
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.842085478
Short name T216
Test name
Test status
Simulation time 501910471148 ps
CPU time 582.38 seconds
Started Jul 15 06:10:59 PM PDT 24
Finished Jul 15 06:20:41 PM PDT 24
Peak memory 201936 kb
Host smart-372b0be6-fdee-4588-8e19-7c77347b6ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842085478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
842085478
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1624576602
Short name T765
Test name
Test status
Simulation time 73719264789 ps
CPU time 41.56 seconds
Started Jul 15 06:11:00 PM PDT 24
Finished Jul 15 06:11:42 PM PDT 24
Peak memory 210196 kb
Host smart-7a8206d7-be97-45d0-a488-ec45a19e70e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624576602 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1624576602
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3377590660
Short name T726
Test name
Test status
Simulation time 486888009 ps
CPU time 0.9 seconds
Started Jul 15 06:11:07 PM PDT 24
Finished Jul 15 06:11:08 PM PDT 24
Peak memory 201680 kb
Host smart-39676606-7272-45b4-9d42-8c0a6f005b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377590660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3377590660
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3719260007
Short name T235
Test name
Test status
Simulation time 626776455170 ps
CPU time 1469.38 seconds
Started Jul 15 06:11:13 PM PDT 24
Finished Jul 15 06:35:43 PM PDT 24
Peak memory 201876 kb
Host smart-9a7296e9-bb0c-43d2-a938-2eb9cc469ad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719260007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3719260007
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3080693214
Short name T86
Test name
Test status
Simulation time 171676800348 ps
CPU time 368.83 seconds
Started Jul 15 06:11:07 PM PDT 24
Finished Jul 15 06:17:16 PM PDT 24
Peak memory 201912 kb
Host smart-155c9f3d-7397-414f-af96-2ebb47979f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080693214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3080693214
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3247516180
Short name T536
Test name
Test status
Simulation time 488743750798 ps
CPU time 1136.16 seconds
Started Jul 15 06:11:00 PM PDT 24
Finished Jul 15 06:29:57 PM PDT 24
Peak memory 201884 kb
Host smart-52b4da71-3673-4938-8f7d-296d33bca836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247516180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3247516180
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3016599300
Short name T337
Test name
Test status
Simulation time 329310969015 ps
CPU time 726.25 seconds
Started Jul 15 06:11:07 PM PDT 24
Finished Jul 15 06:23:14 PM PDT 24
Peak memory 201860 kb
Host smart-c76cf6df-8507-47f2-a8b7-558a8ca2462f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016599300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3016599300
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1816258685
Short name T573
Test name
Test status
Simulation time 165363356826 ps
CPU time 137.15 seconds
Started Jul 15 06:11:02 PM PDT 24
Finished Jul 15 06:13:19 PM PDT 24
Peak memory 201896 kb
Host smart-af038854-a43e-42eb-845c-e237e6ab274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816258685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1816258685
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3888213004
Short name T406
Test name
Test status
Simulation time 331618521432 ps
CPU time 768.92 seconds
Started Jul 15 06:10:57 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 201940 kb
Host smart-344d4cf9-47d9-4e0f-a106-4b6ec0cf7c11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888213004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3888213004
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1274855593
Short name T756
Test name
Test status
Simulation time 334078545983 ps
CPU time 192.9 seconds
Started Jul 15 06:11:07 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 201900 kb
Host smart-31ae1fc9-e120-4ab0-ad32-4dfdf5346721
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274855593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1274855593
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2264979118
Short name T766
Test name
Test status
Simulation time 594689374766 ps
CPU time 686.7 seconds
Started Jul 15 06:11:06 PM PDT 24
Finished Jul 15 06:22:34 PM PDT 24
Peak memory 201896 kb
Host smart-ce20aca4-3753-4608-bd35-ecde034726eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264979118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2264979118
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3739498021
Short name T527
Test name
Test status
Simulation time 94419473576 ps
CPU time 360.04 seconds
Started Jul 15 06:11:13 PM PDT 24
Finished Jul 15 06:17:14 PM PDT 24
Peak memory 202240 kb
Host smart-0a9921e2-684e-41e0-a29e-4296890ef90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739498021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3739498021
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3410955049
Short name T329
Test name
Test status
Simulation time 22456437348 ps
CPU time 24.61 seconds
Started Jul 15 06:11:08 PM PDT 24
Finished Jul 15 06:11:33 PM PDT 24
Peak memory 201676 kb
Host smart-8f47d7ee-0eb5-4708-9bbd-f0d32683893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410955049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3410955049
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2274775525
Short name T493
Test name
Test status
Simulation time 4027068231 ps
CPU time 4.44 seconds
Started Jul 15 06:11:05 PM PDT 24
Finished Jul 15 06:11:10 PM PDT 24
Peak memory 201716 kb
Host smart-4f00c5f0-8b9e-4b40-a8e6-85b8bdb6f255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274775525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2274775525
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3913961900
Short name T164
Test name
Test status
Simulation time 5874182572 ps
CPU time 9.67 seconds
Started Jul 15 06:10:59 PM PDT 24
Finished Jul 15 06:11:09 PM PDT 24
Peak memory 201696 kb
Host smart-0ca43d8a-7224-4095-8ab2-52023d8dda0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913961900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3913961900
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3142762751
Short name T132
Test name
Test status
Simulation time 520256854413 ps
CPU time 1066.67 seconds
Started Jul 15 06:11:09 PM PDT 24
Finished Jul 15 06:28:56 PM PDT 24
Peak memory 201872 kb
Host smart-4891b740-e0b7-4ba0-9bd7-f15079089bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142762751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3142762751
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2141939095
Short name T39
Test name
Test status
Simulation time 437301197940 ps
CPU time 272.85 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:15:48 PM PDT 24
Peak memory 210536 kb
Host smart-52644b2f-9d7b-4471-a155-8262af3747c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141939095 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2141939095
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2764655615
Short name T45
Test name
Test status
Simulation time 462087077 ps
CPU time 1.07 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:11:17 PM PDT 24
Peak memory 201484 kb
Host smart-224fb6ca-8471-48f8-b66f-bd399a81c139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764655615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2764655615
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3215215398
Short name T176
Test name
Test status
Simulation time 445380101676 ps
CPU time 248.94 seconds
Started Jul 15 06:11:14 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 201896 kb
Host smart-cda05da4-50b7-4b21-8256-9095cc0da916
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215215398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3215215398
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.209184262
Short name T160
Test name
Test status
Simulation time 503464535714 ps
CPU time 300.73 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:16:17 PM PDT 24
Peak memory 201924 kb
Host smart-a14f0e4e-b322-4346-9329-5e9bb1945b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209184262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.209184262
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1103721483
Short name T167
Test name
Test status
Simulation time 334959556129 ps
CPU time 52.8 seconds
Started Jul 15 06:11:09 PM PDT 24
Finished Jul 15 06:12:02 PM PDT 24
Peak memory 201928 kb
Host smart-804d6181-161e-471a-8230-ef2bb109075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103721483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1103721483
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1904725038
Short name T352
Test name
Test status
Simulation time 492061174201 ps
CPU time 1161.83 seconds
Started Jul 15 06:11:13 PM PDT 24
Finished Jul 15 06:30:35 PM PDT 24
Peak memory 201908 kb
Host smart-3424cb71-6872-4fb5-a564-4ea20a03a835
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904725038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1904725038
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1581092556
Short name T130
Test name
Test status
Simulation time 318251097538 ps
CPU time 181.09 seconds
Started Jul 15 06:11:10 PM PDT 24
Finished Jul 15 06:14:11 PM PDT 24
Peak memory 201904 kb
Host smart-56866bcf-5bd2-4154-b6ff-2332dd4a081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581092556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1581092556
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1165220157
Short name T522
Test name
Test status
Simulation time 163646450180 ps
CPU time 384.62 seconds
Started Jul 15 06:11:07 PM PDT 24
Finished Jul 15 06:17:32 PM PDT 24
Peak memory 201944 kb
Host smart-961ff2d8-33f6-41f4-8bae-8b6d9472f4fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165220157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1165220157
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3340018306
Short name T199
Test name
Test status
Simulation time 383749658263 ps
CPU time 897.88 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:26:14 PM PDT 24
Peak memory 202012 kb
Host smart-089d516d-c990-4e11-a787-2db00601cb1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340018306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3340018306
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2234112565
Short name T747
Test name
Test status
Simulation time 190577124856 ps
CPU time 97.95 seconds
Started Jul 15 06:11:08 PM PDT 24
Finished Jul 15 06:12:46 PM PDT 24
Peak memory 201868 kb
Host smart-9ffded01-5e0a-444b-972d-c7c26261d0b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234112565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2234112565
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1114845848
Short name T496
Test name
Test status
Simulation time 113027937154 ps
CPU time 367.63 seconds
Started Jul 15 06:11:17 PM PDT 24
Finished Jul 15 06:17:25 PM PDT 24
Peak memory 202220 kb
Host smart-f86280df-9601-477f-b8ff-01241d581b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114845848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1114845848
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3191771240
Short name T676
Test name
Test status
Simulation time 35316406228 ps
CPU time 79.67 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:12:35 PM PDT 24
Peak memory 201700 kb
Host smart-d8a6e429-2336-46cf-8bbc-7337aa58669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191771240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3191771240
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2112271316
Short name T31
Test name
Test status
Simulation time 4443508225 ps
CPU time 2.97 seconds
Started Jul 15 06:11:17 PM PDT 24
Finished Jul 15 06:11:21 PM PDT 24
Peak memory 201708 kb
Host smart-6e491f96-5236-4018-ac08-e17c2cdb15b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112271316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2112271316
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2781637398
Short name T394
Test name
Test status
Simulation time 5903876597 ps
CPU time 4.09 seconds
Started Jul 15 06:11:07 PM PDT 24
Finished Jul 15 06:11:12 PM PDT 24
Peak memory 201728 kb
Host smart-9d304c69-59d7-4d4d-b65d-ca8766f1350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781637398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2781637398
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1861674641
Short name T721
Test name
Test status
Simulation time 170003177003 ps
CPU time 813.43 seconds
Started Jul 15 06:11:17 PM PDT 24
Finished Jul 15 06:24:51 PM PDT 24
Peak memory 210584 kb
Host smart-ec668679-34c9-478e-9560-bdf9905116a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861674641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1861674641
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3598155897
Short name T22
Test name
Test status
Simulation time 59443182858 ps
CPU time 145.42 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:13:41 PM PDT 24
Peak memory 210584 kb
Host smart-fdbb0087-c1c9-4a44-a97c-536c782f99e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598155897 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3598155897
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1555807532
Short name T730
Test name
Test status
Simulation time 345628694 ps
CPU time 0.96 seconds
Started Jul 15 06:11:25 PM PDT 24
Finished Jul 15 06:11:26 PM PDT 24
Peak memory 201640 kb
Host smart-b857ad49-af2c-4117-8fb4-526fceecec53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555807532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1555807532
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1264460301
Short name T227
Test name
Test status
Simulation time 170847047939 ps
CPU time 104.67 seconds
Started Jul 15 06:11:17 PM PDT 24
Finished Jul 15 06:13:02 PM PDT 24
Peak memory 201920 kb
Host smart-08f02481-fe4b-43f5-b601-fa0ea5390b27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264460301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1264460301
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.445188407
Short name T178
Test name
Test status
Simulation time 491597803694 ps
CPU time 303.46 seconds
Started Jul 15 06:11:16 PM PDT 24
Finished Jul 15 06:16:20 PM PDT 24
Peak memory 201900 kb
Host smart-823ad4cf-5a36-4bd8-8d46-0041d90ed61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445188407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.445188407
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2039968169
Short name T11
Test name
Test status
Simulation time 167245597482 ps
CPU time 76.52 seconds
Started Jul 15 06:11:13 PM PDT 24
Finished Jul 15 06:12:30 PM PDT 24
Peak memory 201880 kb
Host smart-6eaeb07f-3a8e-443a-8ad8-ecd7ff3bcfb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039968169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2039968169
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1527859921
Short name T458
Test name
Test status
Simulation time 162673191075 ps
CPU time 85.07 seconds
Started Jul 15 06:11:16 PM PDT 24
Finished Jul 15 06:12:42 PM PDT 24
Peak memory 201984 kb
Host smart-13edb0d7-1fea-4802-9051-2bf3ce870525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527859921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1527859921
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3935930656
Short name T375
Test name
Test status
Simulation time 164650709371 ps
CPU time 183.75 seconds
Started Jul 15 06:11:14 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 201884 kb
Host smart-baa6ab51-68af-4cf8-a2f3-075ce9a3091b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935930656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3935930656
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4234383017
Short name T137
Test name
Test status
Simulation time 367865679942 ps
CPU time 59.65 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:12:16 PM PDT 24
Peak memory 201852 kb
Host smart-c3e71f16-d87d-4e54-86a0-63bc6155da2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234383017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4234383017
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4025274416
Short name T646
Test name
Test status
Simulation time 597283474003 ps
CPU time 1278.36 seconds
Started Jul 15 06:11:14 PM PDT 24
Finished Jul 15 06:32:33 PM PDT 24
Peak memory 201824 kb
Host smart-30942629-107c-44aa-a811-0ea074af1e8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025274416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4025274416
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2220719209
Short name T580
Test name
Test status
Simulation time 123387011331 ps
CPU time 568.52 seconds
Started Jul 15 06:11:20 PM PDT 24
Finished Jul 15 06:20:49 PM PDT 24
Peak memory 202284 kb
Host smart-56557dac-0ffe-4719-85db-d7d049cae7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220719209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2220719209
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4018431764
Short name T793
Test name
Test status
Simulation time 37449453920 ps
CPU time 20.92 seconds
Started Jul 15 06:11:12 PM PDT 24
Finished Jul 15 06:11:34 PM PDT 24
Peak memory 201656 kb
Host smart-441e18be-39aa-4e92-bc35-3966aa28a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018431764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4018431764
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2201988233
Short name T635
Test name
Test status
Simulation time 3685274859 ps
CPU time 5.61 seconds
Started Jul 15 06:11:15 PM PDT 24
Finished Jul 15 06:11:21 PM PDT 24
Peak memory 201540 kb
Host smart-366f8221-abff-4471-ab01-24aa72d4857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201988233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2201988233
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3904729693
Short name T422
Test name
Test status
Simulation time 5625295094 ps
CPU time 13.33 seconds
Started Jul 15 06:11:12 PM PDT 24
Finished Jul 15 06:11:26 PM PDT 24
Peak memory 201632 kb
Host smart-4452837b-1aeb-4721-a893-e35bc0138aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904729693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3904729693
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.753184278
Short name T324
Test name
Test status
Simulation time 430706261 ps
CPU time 0.91 seconds
Started Jul 15 06:11:35 PM PDT 24
Finished Jul 15 06:11:36 PM PDT 24
Peak memory 201664 kb
Host smart-e4fd853c-ad72-49a6-9d73-d2eb1cc0f18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753184278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.753184278
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3174956059
Short name T773
Test name
Test status
Simulation time 380387814045 ps
CPU time 362.94 seconds
Started Jul 15 06:11:27 PM PDT 24
Finished Jul 15 06:17:30 PM PDT 24
Peak memory 201852 kb
Host smart-29c9421f-65be-406a-9373-6dc6b57042d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174956059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3174956059
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1881240871
Short name T687
Test name
Test status
Simulation time 161640749657 ps
CPU time 393.88 seconds
Started Jul 15 06:11:29 PM PDT 24
Finished Jul 15 06:18:03 PM PDT 24
Peak memory 201924 kb
Host smart-55bfbf8d-6df0-4e2d-a420-d5a3bd3c3d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881240871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1881240871
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3669477575
Short name T662
Test name
Test status
Simulation time 168647400081 ps
CPU time 376.56 seconds
Started Jul 15 06:11:32 PM PDT 24
Finished Jul 15 06:17:49 PM PDT 24
Peak memory 201956 kb
Host smart-0984880c-e202-4323-a235-de2d6ad23aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669477575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3669477575
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1335128121
Short name T753
Test name
Test status
Simulation time 164020955021 ps
CPU time 349.28 seconds
Started Jul 15 06:11:23 PM PDT 24
Finished Jul 15 06:17:13 PM PDT 24
Peak memory 201896 kb
Host smart-80261456-757f-4206-9b6e-576ae19a10f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335128121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1335128121
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1313020530
Short name T249
Test name
Test status
Simulation time 483122573399 ps
CPU time 262.54 seconds
Started Jul 15 06:11:23 PM PDT 24
Finished Jul 15 06:15:46 PM PDT 24
Peak memory 201956 kb
Host smart-e96a76bd-dc2b-4033-9117-0c6fed589495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313020530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1313020530
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.64921446
Short name T558
Test name
Test status
Simulation time 156526321014 ps
CPU time 81.69 seconds
Started Jul 15 06:11:21 PM PDT 24
Finished Jul 15 06:12:43 PM PDT 24
Peak memory 201856 kb
Host smart-5e575e3d-e02b-4ee9-9dcc-38733e23b1ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=64921446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed
.64921446
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2765028091
Short name T146
Test name
Test status
Simulation time 533046536731 ps
CPU time 1213.78 seconds
Started Jul 15 06:11:27 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 201916 kb
Host smart-b7359397-3e2b-4bfc-9d46-707edc5d4aef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765028091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2765028091
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3882137429
Short name T336
Test name
Test status
Simulation time 389590754217 ps
CPU time 147.14 seconds
Started Jul 15 06:11:29 PM PDT 24
Finished Jul 15 06:13:57 PM PDT 24
Peak memory 201880 kb
Host smart-ede5e5c3-bae4-4450-be2d-45d2f92e027d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882137429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3882137429
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.434555653
Short name T50
Test name
Test status
Simulation time 134673707147 ps
CPU time 720.78 seconds
Started Jul 15 06:11:29 PM PDT 24
Finished Jul 15 06:23:30 PM PDT 24
Peak memory 202228 kb
Host smart-106d2904-61db-4fd3-8f9d-3d3e249ca223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434555653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.434555653
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2319680958
Short name T409
Test name
Test status
Simulation time 29528730106 ps
CPU time 3.99 seconds
Started Jul 15 06:11:29 PM PDT 24
Finished Jul 15 06:11:34 PM PDT 24
Peak memory 201716 kb
Host smart-47535280-67cc-47ea-b9fd-a4306ee1e567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319680958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2319680958
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3534262737
Short name T306
Test name
Test status
Simulation time 3819815216 ps
CPU time 2.79 seconds
Started Jul 15 06:11:27 PM PDT 24
Finished Jul 15 06:11:30 PM PDT 24
Peak memory 201648 kb
Host smart-ab50c043-6504-4825-b879-3a3e9a238ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534262737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3534262737
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1913309900
Short name T549
Test name
Test status
Simulation time 5777490179 ps
CPU time 6.94 seconds
Started Jul 15 06:11:21 PM PDT 24
Finished Jul 15 06:11:28 PM PDT 24
Peak memory 201628 kb
Host smart-feb27efb-dc2d-40ba-980f-8c2fd21d7f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913309900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1913309900
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1812813292
Short name T280
Test name
Test status
Simulation time 375403185871 ps
CPU time 680.71 seconds
Started Jul 15 06:11:28 PM PDT 24
Finished Jul 15 06:22:49 PM PDT 24
Peak memory 201876 kb
Host smart-968b6bc2-b7e0-4a3c-978d-4423a75690d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812813292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1812813292
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1026540232
Short name T14
Test name
Test status
Simulation time 89222069312 ps
CPU time 144.32 seconds
Started Jul 15 06:11:28 PM PDT 24
Finished Jul 15 06:13:53 PM PDT 24
Peak memory 210516 kb
Host smart-ff95e06f-7cee-4228-9057-96149851bb33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026540232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1026540232
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4022452859
Short name T485
Test name
Test status
Simulation time 289306680 ps
CPU time 1.21 seconds
Started Jul 15 06:11:43 PM PDT 24
Finished Jul 15 06:11:45 PM PDT 24
Peak memory 201596 kb
Host smart-547245d0-f072-4657-b474-fe76ffe29a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022452859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4022452859
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2096741355
Short name T682
Test name
Test status
Simulation time 178777823740 ps
CPU time 370.06 seconds
Started Jul 15 06:11:36 PM PDT 24
Finished Jul 15 06:17:47 PM PDT 24
Peak memory 201932 kb
Host smart-2876f219-88cf-4871-80d3-2eea0ea85bf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096741355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2096741355
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.18836184
Short name T179
Test name
Test status
Simulation time 328449742551 ps
CPU time 716.39 seconds
Started Jul 15 06:11:36 PM PDT 24
Finished Jul 15 06:23:33 PM PDT 24
Peak memory 201964 kb
Host smart-f5d36d93-f9ab-4eee-9de4-83796d9f2948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18836184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.18836184
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.295529426
Short name T767
Test name
Test status
Simulation time 328056010624 ps
CPU time 759.28 seconds
Started Jul 15 06:11:36 PM PDT 24
Finished Jul 15 06:24:15 PM PDT 24
Peak memory 201868 kb
Host smart-d3f226e9-ab82-4875-86c9-6072d20a0af1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=295529426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.295529426
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4028153528
Short name T749
Test name
Test status
Simulation time 323029498071 ps
CPU time 695.09 seconds
Started Jul 15 06:11:36 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 201992 kb
Host smart-4f78f30e-40af-4b6e-8a7c-55ae30196083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028153528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4028153528
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1530833748
Short name T711
Test name
Test status
Simulation time 166041734667 ps
CPU time 97.67 seconds
Started Jul 15 06:11:38 PM PDT 24
Finished Jul 15 06:13:16 PM PDT 24
Peak memory 201960 kb
Host smart-69d9e9ee-4c55-4f65-b17d-a87018f4bf8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530833748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1530833748
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.912665921
Short name T253
Test name
Test status
Simulation time 564519807251 ps
CPU time 652.78 seconds
Started Jul 15 06:11:37 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 201896 kb
Host smart-3714a377-7279-4154-bb47-58ab22b21351
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912665921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.912665921
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3327911081
Short name T696
Test name
Test status
Simulation time 411604932321 ps
CPU time 274.45 seconds
Started Jul 15 06:11:36 PM PDT 24
Finished Jul 15 06:16:11 PM PDT 24
Peak memory 201928 kb
Host smart-ebe97f95-96f1-47a1-a8bf-0821319470cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327911081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3327911081
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3716868629
Short name T665
Test name
Test status
Simulation time 84398539946 ps
CPU time 412.23 seconds
Started Jul 15 06:11:44 PM PDT 24
Finished Jul 15 06:18:37 PM PDT 24
Peak memory 202228 kb
Host smart-dbba3e47-af1f-4f49-8b40-5a68b6f4bd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716868629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3716868629
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2939805080
Short name T674
Test name
Test status
Simulation time 44155277256 ps
CPU time 33.08 seconds
Started Jul 15 06:11:43 PM PDT 24
Finished Jul 15 06:12:17 PM PDT 24
Peak memory 201680 kb
Host smart-cf640309-5bcd-4a4a-886e-ddef14e687c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939805080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2939805080
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2459226239
Short name T576
Test name
Test status
Simulation time 5321654935 ps
CPU time 11.51 seconds
Started Jul 15 06:11:45 PM PDT 24
Finished Jul 15 06:11:57 PM PDT 24
Peak memory 201700 kb
Host smart-7ca841d6-b016-4730-8408-58cd32e0333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459226239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2459226239
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1725360187
Short name T426
Test name
Test status
Simulation time 5870423193 ps
CPU time 15.51 seconds
Started Jul 15 06:11:37 PM PDT 24
Finished Jul 15 06:11:53 PM PDT 24
Peak memory 201708 kb
Host smart-d1d1b953-69aa-4d26-9a45-cbb175816548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725360187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1725360187
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3182443976
Short name T181
Test name
Test status
Simulation time 229258189200 ps
CPU time 155.23 seconds
Started Jul 15 06:11:44 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 201888 kb
Host smart-308d3c9d-a162-4a49-97cc-df1da1a6271f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182443976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3182443976
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3007441121
Short name T267
Test name
Test status
Simulation time 959381736066 ps
CPU time 310.23 seconds
Started Jul 15 06:11:43 PM PDT 24
Finished Jul 15 06:16:54 PM PDT 24
Peak memory 210564 kb
Host smart-858edc00-fd16-4123-b0f8-90f8602766ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007441121 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3007441121
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.981150361
Short name T378
Test name
Test status
Simulation time 410301971 ps
CPU time 0.73 seconds
Started Jul 15 06:11:49 PM PDT 24
Finished Jul 15 06:11:50 PM PDT 24
Peak memory 201636 kb
Host smart-31647c9c-c711-4938-a3ad-440d4f483deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981150361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.981150361
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2105389396
Short name T221
Test name
Test status
Simulation time 489748678657 ps
CPU time 751.26 seconds
Started Jul 15 06:11:42 PM PDT 24
Finished Jul 15 06:24:14 PM PDT 24
Peak memory 201920 kb
Host smart-6307d998-c4b3-46d7-914e-fc84c4311cce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105389396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2105389396
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2895766462
Short name T273
Test name
Test status
Simulation time 337267803893 ps
CPU time 406.83 seconds
Started Jul 15 06:11:42 PM PDT 24
Finished Jul 15 06:18:30 PM PDT 24
Peak memory 201860 kb
Host smart-f5617dbc-ff06-489e-acf0-78ac64ad3574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895766462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2895766462
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1401353318
Short name T150
Test name
Test status
Simulation time 160348356955 ps
CPU time 351.19 seconds
Started Jul 15 06:11:44 PM PDT 24
Finished Jul 15 06:17:36 PM PDT 24
Peak memory 201848 kb
Host smart-d56037b7-b327-49d9-9771-0486182ceaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401353318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1401353318
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2268011723
Short name T320
Test name
Test status
Simulation time 322686334555 ps
CPU time 155.17 seconds
Started Jul 15 06:11:43 PM PDT 24
Finished Jul 15 06:14:18 PM PDT 24
Peak memory 201904 kb
Host smart-375d68ab-a87f-4c82-97be-e366d2a3949b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268011723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2268011723
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2974968323
Short name T578
Test name
Test status
Simulation time 165181802955 ps
CPU time 44.65 seconds
Started Jul 15 06:11:45 PM PDT 24
Finished Jul 15 06:12:30 PM PDT 24
Peak memory 201896 kb
Host smart-fd3f1651-1506-49bb-a52b-cd14e1e0f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974968323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2974968323
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2970404159
Short name T516
Test name
Test status
Simulation time 330616016495 ps
CPU time 792.76 seconds
Started Jul 15 06:11:42 PM PDT 24
Finished Jul 15 06:24:56 PM PDT 24
Peak memory 201932 kb
Host smart-9ac8d814-d787-45e8-9b51-81493c8265ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970404159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2970404159
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.605330219
Short name T25
Test name
Test status
Simulation time 608124639752 ps
CPU time 1339.02 seconds
Started Jul 15 06:11:44 PM PDT 24
Finished Jul 15 06:34:04 PM PDT 24
Peak memory 201904 kb
Host smart-ef5e9655-75fb-484d-acbd-8e5e1f056f8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605330219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.605330219
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4188898577
Short name T153
Test name
Test status
Simulation time 80640533447 ps
CPU time 438.51 seconds
Started Jul 15 06:11:45 PM PDT 24
Finished Jul 15 06:19:04 PM PDT 24
Peak memory 202384 kb
Host smart-5c554159-7c6c-49e7-b776-a20966ec8490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188898577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4188898577
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1502063203
Short name T484
Test name
Test status
Simulation time 37256350380 ps
CPU time 22.41 seconds
Started Jul 15 06:11:45 PM PDT 24
Finished Jul 15 06:12:08 PM PDT 24
Peak memory 201652 kb
Host smart-56817906-067b-4cb1-a005-ee1a8e9ef7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502063203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1502063203
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2415449616
Short name T622
Test name
Test status
Simulation time 4369374657 ps
CPU time 10.14 seconds
Started Jul 15 06:11:44 PM PDT 24
Finished Jul 15 06:11:54 PM PDT 24
Peak memory 201648 kb
Host smart-77891ceb-f9a3-4e39-91ab-5befe8cfcfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415449616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2415449616
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.888897725
Short name T335
Test name
Test status
Simulation time 5761565626 ps
CPU time 4.18 seconds
Started Jul 15 06:11:43 PM PDT 24
Finished Jul 15 06:11:47 PM PDT 24
Peak memory 201612 kb
Host smart-4fce1305-a3e9-4c4f-9b74-2246b4179a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888897725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.888897725
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1272536932
Short name T609
Test name
Test status
Simulation time 171275187220 ps
CPU time 106.46 seconds
Started Jul 15 06:11:49 PM PDT 24
Finished Jul 15 06:13:36 PM PDT 24
Peak memory 201856 kb
Host smart-533a7be8-ea69-4ba7-9a99-40d8fb3ff4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272536932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1272536932
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1590746199
Short name T661
Test name
Test status
Simulation time 428372657 ps
CPU time 1.09 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:07:18 PM PDT 24
Peak memory 201772 kb
Host smart-af6ee40b-6f4a-4adb-8b38-938fa9776b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590746199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1590746199
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.9178566
Short name T449
Test name
Test status
Simulation time 312799651886 ps
CPU time 15.4 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:07:24 PM PDT 24
Peak memory 201856 kb
Host smart-111f6585-640f-4268-8b1d-4a9f9a52e11f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9178566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.9178566
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.109411218
Short name T207
Test name
Test status
Simulation time 488210601992 ps
CPU time 577.65 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:16:45 PM PDT 24
Peak memory 201924 kb
Host smart-f102574a-d092-4665-ba4d-fe4f2754dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109411218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.109411218
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4118183398
Short name T761
Test name
Test status
Simulation time 327946980959 ps
CPU time 758.17 seconds
Started Jul 15 06:07:05 PM PDT 24
Finished Jul 15 06:19:45 PM PDT 24
Peak memory 201956 kb
Host smart-40ced209-6996-4e42-bd8b-b65ff798a370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118183398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4118183398
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3703939933
Short name T346
Test name
Test status
Simulation time 503516970692 ps
CPU time 230.44 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:10:59 PM PDT 24
Peak memory 201872 kb
Host smart-5fea8f49-d12c-4882-9722-c7fb8082d0e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703939933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3703939933
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3107575282
Short name T265
Test name
Test status
Simulation time 163961403531 ps
CPU time 103.66 seconds
Started Jul 15 06:07:08 PM PDT 24
Finished Jul 15 06:08:53 PM PDT 24
Peak memory 201884 kb
Host smart-5a8840bc-05e2-41b8-8d85-1cca980924ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107575282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3107575282
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1457719634
Short name T427
Test name
Test status
Simulation time 492250336692 ps
CPU time 1090.63 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:25:15 PM PDT 24
Peak memory 201872 kb
Host smart-56f02270-6f69-4a4d-9949-cae0bbdc29d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457719634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1457719634
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.704076063
Short name T174
Test name
Test status
Simulation time 452903545769 ps
CPU time 206.71 seconds
Started Jul 15 06:07:10 PM PDT 24
Finished Jul 15 06:10:37 PM PDT 24
Peak memory 201844 kb
Host smart-daaad98b-b217-4c48-922a-3b4b766b7bf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704076063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.704076063
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.883721640
Short name T348
Test name
Test status
Simulation time 400052203016 ps
CPU time 725.85 seconds
Started Jul 15 06:07:10 PM PDT 24
Finished Jul 15 06:19:16 PM PDT 24
Peak memory 201936 kb
Host smart-55c99f3b-a1bb-4b67-841a-09ea9ab4aeee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883721640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.883721640
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.75503383
Short name T508
Test name
Test status
Simulation time 26665930939 ps
CPU time 61.59 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:08:09 PM PDT 24
Peak memory 201728 kb
Host smart-f001f37c-cd73-4691-b8b6-cd0e9ead8941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75503383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.75503383
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1994916794
Short name T745
Test name
Test status
Simulation time 5104431654 ps
CPU time 11.95 seconds
Started Jul 15 06:07:06 PM PDT 24
Finished Jul 15 06:07:19 PM PDT 24
Peak memory 201724 kb
Host smart-e51ac65f-c12a-4dfa-823f-0122f171c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994916794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1994916794
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.64978322
Short name T509
Test name
Test status
Simulation time 5868254608 ps
CPU time 3.84 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:07:12 PM PDT 24
Peak memory 201676 kb
Host smart-1d5319f6-18d5-4faf-a92d-3009324eb151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64978322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.64978322
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2447399999
Short name T91
Test name
Test status
Simulation time 182062357085 ps
CPU time 265.18 seconds
Started Jul 15 06:07:07 PM PDT 24
Finished Jul 15 06:11:33 PM PDT 24
Peak memory 201872 kb
Host smart-f63589ad-d23c-4709-a158-05ffe8d1b1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447399999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2447399999
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2228075732
Short name T541
Test name
Test status
Simulation time 227451718744 ps
CPU time 89.48 seconds
Started Jul 15 06:07:04 PM PDT 24
Finished Jul 15 06:08:34 PM PDT 24
Peak memory 217192 kb
Host smart-19e445ad-2ca1-49b2-a4f3-d631db11e4a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228075732 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2228075732
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2382625137
Short name T373
Test name
Test status
Simulation time 318785378 ps
CPU time 1.34 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:07:22 PM PDT 24
Peak memory 201648 kb
Host smart-99635913-f7fc-457a-aaf7-393ba3769050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382625137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2382625137
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2999032412
Short name T486
Test name
Test status
Simulation time 343611720928 ps
CPU time 223.56 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:10:58 PM PDT 24
Peak memory 201900 kb
Host smart-7e9b095d-b4d5-4fd5-9006-fa905f8859d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999032412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2999032412
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3912959848
Short name T223
Test name
Test status
Simulation time 179967524969 ps
CPU time 54.12 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:08:09 PM PDT 24
Peak memory 201896 kb
Host smart-4abff838-5f6f-4ebb-8511-56487342007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912959848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3912959848
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2599280387
Short name T419
Test name
Test status
Simulation time 165924877630 ps
CPU time 193.41 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:10:31 PM PDT 24
Peak memory 201884 kb
Host smart-6d4f02b3-a75c-482d-b1bc-ddbfad01eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599280387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2599280387
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.140455026
Short name T436
Test name
Test status
Simulation time 334132862176 ps
CPU time 791.75 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:20:26 PM PDT 24
Peak memory 201832 kb
Host smart-aaca074e-7743-4ab5-a13b-4dfde5bcc5e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=140455026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.140455026
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1740775257
Short name T605
Test name
Test status
Simulation time 486819988260 ps
CPU time 1124.5 seconds
Started Jul 15 06:07:12 PM PDT 24
Finished Jul 15 06:25:57 PM PDT 24
Peak memory 201908 kb
Host smart-7ee2df35-91cc-454a-a66b-afbbee2bc3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740775257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1740775257
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1623481346
Short name T316
Test name
Test status
Simulation time 332358795424 ps
CPU time 666.75 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:18:20 PM PDT 24
Peak memory 201924 kb
Host smart-ce845c96-312f-444d-a426-37c37de2332b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623481346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1623481346
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1798377989
Short name T736
Test name
Test status
Simulation time 196236172443 ps
CPU time 51.48 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:08:06 PM PDT 24
Peak memory 201944 kb
Host smart-d1d19302-841b-455d-98af-6b757966c648
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798377989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1798377989
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2188428515
Short name T492
Test name
Test status
Simulation time 386373668104 ps
CPU time 890.45 seconds
Started Jul 15 06:07:19 PM PDT 24
Finished Jul 15 06:22:10 PM PDT 24
Peak memory 201876 kb
Host smart-0789e2ca-233c-4eff-9537-0a2f5349410a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188428515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2188428515
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.29990749
Short name T424
Test name
Test status
Simulation time 129348623768 ps
CPU time 446.63 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 202184 kb
Host smart-449ad931-39c4-46f8-a1eb-dc12b7cb556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29990749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.29990749
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1348432418
Short name T435
Test name
Test status
Simulation time 32909784411 ps
CPU time 15.87 seconds
Started Jul 15 06:07:12 PM PDT 24
Finished Jul 15 06:07:29 PM PDT 24
Peak memory 201692 kb
Host smart-39406240-0565-46bb-9621-c744351ebbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348432418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1348432418
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1662062741
Short name T401
Test name
Test status
Simulation time 4599396625 ps
CPU time 5.31 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:07:21 PM PDT 24
Peak memory 201732 kb
Host smart-cca6e2ca-8579-41e7-896c-099ba7562328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662062741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1662062741
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1766848897
Short name T512
Test name
Test status
Simulation time 6159567308 ps
CPU time 4.51 seconds
Started Jul 15 06:07:10 PM PDT 24
Finished Jul 15 06:07:16 PM PDT 24
Peak memory 201644 kb
Host smart-f207656e-e52c-4d7a-be13-f62c520064aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766848897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1766848897
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3289794473
Short name T32
Test name
Test status
Simulation time 409649954420 ps
CPU time 1112.49 seconds
Started Jul 15 06:07:12 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 202228 kb
Host smart-c6756d99-3c09-4633-99e9-d8c12d8309f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289794473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3289794473
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.689250613
Short name T550
Test name
Test status
Simulation time 77087605889 ps
CPU time 122.81 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:09:25 PM PDT 24
Peak memory 210572 kb
Host smart-b1929a13-76d5-496f-8723-223636061fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689250613 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.689250613
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3764160309
Short name T472
Test name
Test status
Simulation time 404565032 ps
CPU time 1.53 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:07:16 PM PDT 24
Peak memory 201660 kb
Host smart-8dcb7307-afc4-4835-b6b0-d956efbf8fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764160309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3764160309
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3126193210
Short name T792
Test name
Test status
Simulation time 161342612946 ps
CPU time 84.68 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:08:40 PM PDT 24
Peak memory 201916 kb
Host smart-4c3375c7-d377-4983-935d-0ca4bdadad04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126193210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3126193210
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1698229488
Short name T208
Test name
Test status
Simulation time 200217336242 ps
CPU time 400.85 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:13:55 PM PDT 24
Peak memory 201884 kb
Host smart-acc98a72-342d-4c5f-8e8c-cbe580471d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698229488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1698229488
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1453969013
Short name T341
Test name
Test status
Simulation time 331555760521 ps
CPU time 746.51 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:19:42 PM PDT 24
Peak memory 201784 kb
Host smart-0e9565a0-60f0-4689-86f9-014254ea05bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453969013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1453969013
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2661209697
Short name T656
Test name
Test status
Simulation time 171335280428 ps
CPU time 107.06 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:09:04 PM PDT 24
Peak memory 201888 kb
Host smart-77b1144f-01e4-462f-8420-76c6b0c3a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661209697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2661209697
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3456304487
Short name T372
Test name
Test status
Simulation time 163921188240 ps
CPU time 58.28 seconds
Started Jul 15 06:07:17 PM PDT 24
Finished Jul 15 06:08:16 PM PDT 24
Peak memory 201808 kb
Host smart-8cf683f7-d6ea-4f4f-9780-94ef9873fd72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456304487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3456304487
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2816202280
Short name T279
Test name
Test status
Simulation time 525250536571 ps
CPU time 1055.81 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:24:51 PM PDT 24
Peak memory 201900 kb
Host smart-75f66965-05ff-475e-b251-c41e5008d74f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816202280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2816202280
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3539364305
Short name T790
Test name
Test status
Simulation time 631220163875 ps
CPU time 714.68 seconds
Started Jul 15 06:07:17 PM PDT 24
Finished Jul 15 06:19:13 PM PDT 24
Peak memory 201880 kb
Host smart-944218ca-31cc-4a70-bcd1-a8a54e8692c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539364305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3539364305
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3367955318
Short name T191
Test name
Test status
Simulation time 96553342915 ps
CPU time 555.04 seconds
Started Jul 15 06:07:17 PM PDT 24
Finished Jul 15 06:16:32 PM PDT 24
Peak memory 202104 kb
Host smart-642455f0-ed51-4bc6-bb9f-fa4a7c7aabf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367955318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3367955318
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.974861570
Short name T345
Test name
Test status
Simulation time 31737720096 ps
CPU time 74.15 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:08:28 PM PDT 24
Peak memory 201720 kb
Host smart-ca129b25-8562-4931-b8bd-46033a24221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974861570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.974861570
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2221624330
Short name T715
Test name
Test status
Simulation time 5213502234 ps
CPU time 6.86 seconds
Started Jul 15 06:07:12 PM PDT 24
Finished Jul 15 06:07:19 PM PDT 24
Peak memory 201708 kb
Host smart-afa8e9c7-f056-4c9c-8b77-f3e2bfd0738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221624330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2221624330
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1937902714
Short name T353
Test name
Test status
Simulation time 5792339754 ps
CPU time 4.48 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:07:17 PM PDT 24
Peak memory 201692 kb
Host smart-6d8c5c91-d6ac-4095-b1ab-b322f231ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937902714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1937902714
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1124233414
Short name T125
Test name
Test status
Simulation time 328166789607 ps
CPU time 72.32 seconds
Started Jul 15 06:07:12 PM PDT 24
Finished Jul 15 06:08:25 PM PDT 24
Peak memory 201804 kb
Host smart-337d7ace-09ed-45bc-939e-4c43bb265244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124233414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1124233414
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2844950468
Short name T41
Test name
Test status
Simulation time 19597941179 ps
CPU time 52.24 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:08:08 PM PDT 24
Peak memory 210480 kb
Host smart-0162ea26-111a-490d-a197-a2fc5d897e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844950468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2844950468
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3766998812
Short name T566
Test name
Test status
Simulation time 513114969 ps
CPU time 1.8 seconds
Started Jul 15 06:07:19 PM PDT 24
Finished Jul 15 06:07:22 PM PDT 24
Peak memory 201648 kb
Host smart-9bcc8540-e213-471b-8f22-97d557349f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766998812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3766998812
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3841421179
Short name T231
Test name
Test status
Simulation time 171221400748 ps
CPU time 104.16 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:09:05 PM PDT 24
Peak memory 201884 kb
Host smart-90fe5973-b90c-4eaf-a058-b91553606d3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841421179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3841421179
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.314960668
Short name T446
Test name
Test status
Simulation time 328400780739 ps
CPU time 375.93 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:13:31 PM PDT 24
Peak memory 201912 kb
Host smart-de059364-9f0d-4198-89cf-2edd760d3685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314960668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.314960668
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3911882550
Short name T397
Test name
Test status
Simulation time 323859908333 ps
CPU time 753.98 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:19:51 PM PDT 24
Peak memory 201880 kb
Host smart-b8dff619-113c-4fd4-974e-acfc66e88925
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911882550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3911882550
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1155494024
Short name T788
Test name
Test status
Simulation time 169590293857 ps
CPU time 83.8 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:08:37 PM PDT 24
Peak memory 201916 kb
Host smart-b87bef3a-be76-463b-9f53-761c50500b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155494024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1155494024
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.357661908
Short name T318
Test name
Test status
Simulation time 166133206801 ps
CPU time 191.12 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:10:32 PM PDT 24
Peak memory 201876 kb
Host smart-cd2856b1-561e-4be1-93e5-d5b5d0a11087
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=357661908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.357661908
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4175314210
Short name T627
Test name
Test status
Simulation time 513129919068 ps
CPU time 1025.69 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:24:27 PM PDT 24
Peak memory 202080 kb
Host smart-14f0ea4c-643e-4911-aaa1-d9270f6342b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175314210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4175314210
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1396238066
Short name T363
Test name
Test status
Simulation time 417825480150 ps
CPU time 89.28 seconds
Started Jul 15 06:07:14 PM PDT 24
Finished Jul 15 06:08:44 PM PDT 24
Peak memory 201888 kb
Host smart-0fa55234-ae75-4ac1-9f35-349763893a8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396238066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1396238066
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2028479492
Short name T763
Test name
Test status
Simulation time 115355098678 ps
CPU time 472.21 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 202196 kb
Host smart-486dc374-372c-4d10-896f-d1c1b53ce298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028479492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2028479492
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.317627902
Short name T592
Test name
Test status
Simulation time 39758706715 ps
CPU time 86.17 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:08:42 PM PDT 24
Peak memory 201656 kb
Host smart-60365a1a-3ccb-4d26-910c-301f68d47dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317627902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.317627902
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4035851302
Short name T659
Test name
Test status
Simulation time 3484079109 ps
CPU time 3.03 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:07:17 PM PDT 24
Peak memory 201716 kb
Host smart-d5fde50b-9ad8-4938-85cc-7ec213cfd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035851302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4035851302
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1246663006
Short name T755
Test name
Test status
Simulation time 5884693692 ps
CPU time 7.72 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:07:28 PM PDT 24
Peak memory 201700 kb
Host smart-88a929ad-35ed-44c1-8f0a-efffda7f5ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246663006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1246663006
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1817551717
Short name T712
Test name
Test status
Simulation time 241053945512 ps
CPU time 1253.79 seconds
Started Jul 15 06:07:18 PM PDT 24
Finished Jul 15 06:28:13 PM PDT 24
Peak memory 202236 kb
Host smart-849ab66d-9aa9-4a70-be72-12f90bdcaf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817551717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1817551717
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.4203909548
Short name T307
Test name
Test status
Simulation time 302647197 ps
CPU time 1.05 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:07:22 PM PDT 24
Peak memory 201648 kb
Host smart-e0620009-d0fa-4755-8790-2bc8879b9b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203909548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4203909548
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1358636370
Short name T80
Test name
Test status
Simulation time 342168374739 ps
CPU time 209.18 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:10:52 PM PDT 24
Peak memory 201976 kb
Host smart-32a8602c-ad5a-4c41-84de-dc91c28f95b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358636370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1358636370
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.810033003
Short name T630
Test name
Test status
Simulation time 166969672548 ps
CPU time 54.62 seconds
Started Jul 15 06:07:16 PM PDT 24
Finished Jul 15 06:08:12 PM PDT 24
Peak memory 201912 kb
Host smart-a72e1df1-e202-482d-aa50-9ea2d24f3140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810033003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.810033003
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3921361499
Short name T415
Test name
Test status
Simulation time 491354676677 ps
CPU time 1006.72 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 201884 kb
Host smart-c316a88d-d169-4c3c-baee-cac59cf3aee7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921361499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3921361499
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2638407380
Short name T460
Test name
Test status
Simulation time 495705190389 ps
CPU time 1008.25 seconds
Started Jul 15 06:07:11 PM PDT 24
Finished Jul 15 06:24:00 PM PDT 24
Peak memory 201984 kb
Host smart-482b5543-f1fe-4320-a686-ce12f38106f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638407380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2638407380
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.246510177
Short name T602
Test name
Test status
Simulation time 323314688986 ps
CPU time 715.33 seconds
Started Jul 15 06:07:15 PM PDT 24
Finished Jul 15 06:19:11 PM PDT 24
Peak memory 201852 kb
Host smart-417d044b-6c83-43f4-8db5-ad31720adaa7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=246510177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.246510177
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2232488349
Short name T142
Test name
Test status
Simulation time 173947562493 ps
CPU time 360.69 seconds
Started Jul 15 06:07:13 PM PDT 24
Finished Jul 15 06:13:14 PM PDT 24
Peak memory 201904 kb
Host smart-44c5251e-da04-450a-8e9f-61dd11814091
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232488349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2232488349
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4036549738
Short name T677
Test name
Test status
Simulation time 613748691276 ps
CPU time 1409.75 seconds
Started Jul 15 06:07:12 PM PDT 24
Finished Jul 15 06:30:42 PM PDT 24
Peak memory 201972 kb
Host smart-c30358e4-e192-4388-9abe-e8c444f4d073
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036549738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4036549738
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1426017186
Short name T301
Test name
Test status
Simulation time 71365638892 ps
CPU time 399.64 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:14:02 PM PDT 24
Peak memory 202176 kb
Host smart-be648a23-5c64-4274-8dcf-5bb7299dcff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426017186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1426017186
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1963751469
Short name T768
Test name
Test status
Simulation time 34214049734 ps
CPU time 21.46 seconds
Started Jul 15 06:07:28 PM PDT 24
Finished Jul 15 06:07:51 PM PDT 24
Peak memory 201704 kb
Host smart-600313b9-fe43-4e4d-baae-4cdb35b2c81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963751469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1963751469
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2108481378
Short name T310
Test name
Test status
Simulation time 3203802930 ps
CPU time 2.28 seconds
Started Jul 15 06:07:24 PM PDT 24
Finished Jul 15 06:07:27 PM PDT 24
Peak memory 201700 kb
Host smart-8fab4e5c-7bf7-4170-8a8a-b0d437e5197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108481378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2108481378
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3135648891
Short name T333
Test name
Test status
Simulation time 6020852560 ps
CPU time 4.77 seconds
Started Jul 15 06:07:20 PM PDT 24
Finished Jul 15 06:07:26 PM PDT 24
Peak memory 201700 kb
Host smart-8e4f7ceb-28bc-49cb-989e-4d8504872011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135648891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3135648891
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2540503540
Short name T246
Test name
Test status
Simulation time 183707479116 ps
CPU time 364.79 seconds
Started Jul 15 06:07:21 PM PDT 24
Finished Jul 15 06:13:27 PM PDT 24
Peak memory 201976 kb
Host smart-4eaa8db9-bd1d-40d2-a7a2-debae35b1b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540503540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2540503540
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.848544424
Short name T544
Test name
Test status
Simulation time 84005525933 ps
CPU time 109.26 seconds
Started Jul 15 06:07:22 PM PDT 24
Finished Jul 15 06:09:12 PM PDT 24
Peak memory 202552 kb
Host smart-7fb30ce8-c42e-46e3-b3ed-b24323b000d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848544424 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.848544424
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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