Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7043	1			T2	55		T4	10		T5	36
testmodes[AdcCtrlTestmodeNormal]	5295	1			T1	3		T2	51		T3	2
testmodes[AdcCtrlTestmodeLowpower]	5548	1			T2	59		T3	1		T5	29
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4007	1			T2	15		T4	5		T5	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1655	1			T2	15		T4	4		T5	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1274	1			T2	24		T5	9		T7	30
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1672	1			T2	19		T4	4		T5	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2024	1			T1	2		T2	16		T4	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1243	1			T2	16		T3	1		T5	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1253	1			T2	21		T5	6		T7	28
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1283	1			T2	20		T3	1		T5	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2777	1			T2	18		T5	8		T7	18