Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22408

1

T1

2

T2

165

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3680

1

T1

1

T3

20

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20126

1

T1

3

T2

165

T3

22

auto[1]

5962

1

T3

25

T6

3

T8

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T224	12		-	-		-	-
values[0]	51	1			T225	9		T226	22		T227	1
values[1]	618	1			T48	23		T39	2		T27	10
values[2]	670	1			T3	20		T44	13		T137	12
values[3]	784	1			T9	23		T137	1		T15	5
values[4]	753	1			T10	20		T38	1		T43	1
values[5]	3020	1			T1	1		T6	3		T8	36
values[6]	838	1			T46	21		T15	8		T157	12
values[7]	572	1			T1	1		T3	25		T61	2
values[8]	697	1			T38	5		T40	3		T140	12
values[9]	1124	1			T1	1		T3	2		T9	18
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	884	1			T3	20		T44	13		T48	23
values[1]	743	1			T61	1		T15	5		T29	10
values[2]	618	1			T9	23		T10	20		T43	1
values[3]	3126	1			T1	1		T6	3		T8	36
values[4]	662	1			T9	5		T141	1		T29	4
values[5]	772	1			T1	1		T46	21		T15	8
values[6]	821	1			T3	25		T38	5		T61	2
values[7]	498	1			T46	10		T40	3		T140	12
values[8]	790	1			T1	1		T3	2		T9	18
values[9]	213	1			T10	14		T12	14		T40	15
minimum	16961	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T44	13		T48	13		T39	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	9		T15	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T61	1		T29	10		T42	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	2		T32	7		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	13		T10	20		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	1		T137	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T1	1		T6	3		T8	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T38	1		T26	23		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	3		T141	1		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	4		T41	1		T158	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	6		T157	12		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T46	11		T193	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	12		T61	1		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T38	2		T16	4		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	6		T229	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	2		T140	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T3	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	15		T48	8		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	8		T40	7		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T10	14		T40	2		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16836	1			T2	165		T4	20		T5	103
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	10		T39	1		T175	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	11		T15	1		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	7		T151	2		T182	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	3		T144	7		T147	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	10		T137	11		T230	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	4		T149	13		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T50	11		T137	2		T25	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T26	18		T16	1		T230	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	2		T17	1		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T158	13		T231	9		T88	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	2		T18	5		T156	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	10		T193	6		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	13		T61	1		T15	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	3		T16	1		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T46	4		T147	12		T232	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	1		T140	11		T202	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T185	2		T168	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	3		T48	2		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T12	6		T40	5		T90	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T40	1		T149	10		T233	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T224	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T226	22		T234	9		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	1		T227	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	13		T39	1		T29	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T27	1		T153	2		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T44	13		T137	1		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	9		T15	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	13		T42	7		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T137	1		T15	2		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	20		T137	1		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T38	1		T43	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T1	1		T6	3		T8	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	4		T41	1		T167	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	6		T157	12		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T46	11		T228	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	12		T61	1		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	1		T151	14		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	8		T42	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	2		T40	2		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T1	1		T3	1		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T9	15		T10	14		T48	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T224	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T234	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T225	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	10		T39	1		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	9		T147	15		T168	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T137	11		T143	9		T182	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	11		T15	1		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	10		T42	7		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	3		T42	4		T143	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T137	2		T230	7		T201	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T140	4		T26	18		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T9	2		T50	11		T25	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T155	14		T88	9		T236	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	2		T156	4		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T46	10		T144	5		T193	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	13		T61	1		T18	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T151	4		T17	1		T155	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	10		T147	12		T187	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T38	3		T40	1		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T12	6		T46	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T9	3		T48	2		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T44	1		T48	11		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	12		T15	2		T27	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T61	1		T29	1		T42	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	5		T32	5		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	11		T10	1		T137	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	1		T137	1		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T1	1		T6	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T38	1		T26	20		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	3		T141	1		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	1		T41	1		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	7		T157	1		T18	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T46	11		T193	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	14		T61	2		T15	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T38	5		T16	3		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	5		T229	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	2		T140	12		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T3	2		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	4		T48	3		T39	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T12	7		T40	9		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T10	1		T40	3		T149	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16950	1			T2	165		T4	20		T5	103
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T44	12		T48	12		T29	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	8		T238	20		T239	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	9		T42	3		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	2		T147	11		T187	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	12		T10	19		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T167	9		T147	14		T240	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T8	33		T40	2		T28	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T26	21		T16	1		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	2		T17	1		T154	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	3		T158	10		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	1		T157	11		T156	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	10		T193	7		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	11		T15	6		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	2		T151	13		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	5		T147	9		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T40	1		T158	12		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T243	5		T244	12		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	14		T48	7		T39	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	7		T40	3		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T10	13		T152	13		T226	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T247	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T224	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T226	1		T234	10		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T225	9		T227	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	11		T39	2		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	10		T153	2		T147	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T44	1		T137	12		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	12		T15	2		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	11		T42	11		T151	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T137	1		T15	5		T42	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	1		T137	3		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T38	1		T43	1		T140	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T1	1		T6	3		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	1		T41	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	7		T157	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T46	11		T228	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	14		T61	2		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T151	5		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	12		T42	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T38	5		T40	2		T140	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T3	2		T12	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T9	4		T10	1		T48	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T224	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T226	21		T234	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	12		T29	2		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T147	11		T238	20		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	12		T29	9		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	8		T32	2		T240	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	12		T42	3		T151	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T187	4		T248	18		T243	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	19		T40	2		T230	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T26	21		T16	1		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T8	33		T9	2		T28	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	3		T167	11		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	1		T157	11		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T46	10		T193	7		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	11		T238	4		T169	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T151	13		T155	12		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	6		T147	9		T187	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	1		T16	2		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T12	7		T46	5		T40	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T9	14		T10	13		T48	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20344

1

T1

1

T2

165

T3

47

auto[ADC_CTRL_FILTER_COND_OUT]

5744

1

T1

2

T6

3

T8

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19965

1

T1

3

T2

165

T3

45

auto[1]

6123

1

T3

2

T6

3

T8

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T250	8		T251	37		T252	1
values[0]	47	1			T168	10		T253	15		T177	17
values[1]	653	1			T3	2		T43	1		T61	2
values[2]	689	1			T12	14		T44	13		T46	10
values[3]	680	1			T9	23		T38	6		T137	1
values[4]	681	1			T1	1		T10	14		T39	2
values[5]	713	1			T137	3		T29	10		T31	1
values[6]	584	1			T1	1		T3	20		T9	23
values[7]	651	1			T1	1		T46	21		T26	20
values[8]	622	1			T3	25		T10	20		T40	3
values[9]	3773	1			T6	3		T8	36		T11	2
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	857	1			T3	2		T43	1		T44	13
values[1]	2926	1			T6	3		T8	36		T11	2
values[2]	823	1			T9	23		T38	6		T61	1
values[3]	496	1			T1	1		T10	14		T39	2
values[4]	674	1			T1	1		T137	3		T40	3
values[5]	737	1			T3	20		T9	23		T46	21
values[6]	618	1			T1	1		T15	2		T26	20
values[7]	737	1			T3	25		T10	20		T40	3
values[8]	1018	1			T39	1		T40	12		T15	18
values[9]	233	1			T39	11		T31	1		T153	1
minimum	16969	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T44	13		T42	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T43	1		T61	1		T26	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	8		T46	6		T48	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1554	1			T6	3		T8	36		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	18		T40	2		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T38	3		T61	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	14		T39	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	1		T182	1		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T137	1		T40	2		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	1		T15	2		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	9		T46	11		T29	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	13		T48	13		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	1		T15	1		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T26	9		T230	13		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	12		T40	3		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	20		T27	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T40	7		T228	1		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T39	1		T15	8		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T31	1		T153	1		T241	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T39	8		T143	1		T155	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16834	1			T2	165		T4	20		T5	103
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T42	11		T154	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T61	1		T26	7		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	6		T46	4		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1032	1			T50	11		T140	11		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	5		T40	1		T230	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T38	3		T151	14		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T39	1		T144	5		T187	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T182	16		T255	3		T256	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T137	2		T40	1		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	3		T17	1		T187	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	11		T46	10		T151	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	10		T48	10		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	1		T147	12		T182	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T26	11		T230	14		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	13		T140	4		T175	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T27	9		T149	13		T201	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T40	5		T155	16		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	10		T16	1		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T257	1		T258	10		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T39	3		T143	11		T155	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	1		T15	2		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T250	1		T251	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T168	1		T93	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T253	15		T177	17		T259	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T42	8		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	1		T61	1		T26	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	8		T44	13		T46	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	1		T15	6		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	18		T149	1		T230	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	3		T137	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T10	14		T39	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T15	2		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T137	1		T31	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	10		T41	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	9		T40	2		T29	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T9	13		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T46	11		T147	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	9		T153	1		T167	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	12		T40	3		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	20		T149	1		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T40	7		T31	1		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1791	1			T6	3		T8	36		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T250	7		T251	21		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T168	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T259	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T42	11		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T61	1		T26	7		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	6		T46	4		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T140	11		T15	2		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	5		T149	10		T230	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	3		T151	14		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	1		T40	1		T187	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T15	3		T255	3		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	2		T144	5		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T182	16		T187	4		T189	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	11		T40	1		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	10		T48	10		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T46	10		T147	12		T176	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	11		T147	12		T243	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	13		T140	4		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T149	13		T230	14		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T40	5		T175	1		T155	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1204	1			T39	3		T50	11		T15	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2