Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22267

1

T1

2

T2

165

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3821

1

T1

1

T3

47

T9

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20017

1

T1

1

T2

165

T3

2

auto[1]

6071

1

T1

2

T3

45

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	329	1			T137	1		T29	3		T154	28
values[0]	23	1			T194	3		T198	16		T323	1
values[1]	558	1			T9	23		T10	14		T39	2
values[2]	832	1			T3	2		T10	20		T48	10
values[3]	686	1			T3	20		T38	5		T39	1
values[4]	712	1			T38	1		T46	21		T137	3
values[5]	751	1			T1	2		T12	14		T40	3
values[6]	702	1			T1	1		T9	18		T43	1
values[7]	649	1			T48	23		T61	2		T140	5
values[8]	759	1			T9	5		T46	10		T137	12
values[9]	3138	1			T3	25		T6	3		T8	36
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T10	34		T39	2		T141	1
values[1]	598	1			T3	2		T48	10		T39	1
values[2]	675	1			T3	20		T38	5		T40	3
values[3]	860	1			T1	1		T38	1		T46	21
values[4]	612	1			T1	2		T12	14		T40	3
values[5]	696	1			T9	18		T43	1		T40	12
values[6]	3135	1			T6	3		T8	36		T11	2
values[7]	550	1			T9	5		T46	10		T137	12
values[8]	824	1			T3	25		T44	13		T39	11
values[9]	234	1			T157	1		T262	37		T248	28
minimum	17119	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	20		T16	4		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T10	14		T39	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	8		T15	2		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T39	1		T148	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T38	2		T40	3		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	9		T151	13		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T46	11		T32	7		T155	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	1		T38	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	2		T40	2		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	8		T42	1		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	15		T43	1		T40	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	6		T16	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T6	3		T8	36		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T140	1		T26	14		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	3		T46	6		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T137	1		T40	2		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T44	13		T29	4		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	12		T39	8		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T275	1		T204	3		T177	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T157	1		T262	23		T248	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16863	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T9	13		T140	1		T167	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	1		T143	11		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	1		T144	5		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	2		T15	3		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T158	13		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T38	3		T27	9		T51	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	11		T151	14		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	10		T155	12		T193	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T137	2		T26	11		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	1		T15	1		T155	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	6		T42	4		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	3		T40	5		T176	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	2		T16	1		T250	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T48	10		T50	11		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T140	4		T26	7		T230	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	2		T46	4		T15	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T137	11		T40	1		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T42	7		T154	13		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	13		T39	3		T147	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T204	4		T299	10		T324	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T262	14		T248	12		T305	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T9	10		T140	11		T168	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T154	15		T168	1		T243	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T137	1		T29	3		T215	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T198	16		T286	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T194	3		T323	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T143	1		T147	12		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	13		T10	14		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	20		T48	8		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	1		T31	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	2		T40	3		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	9		T39	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	11		T27	1		T193	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T38	1		T137	1		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T40	2		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T12	8		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T9	15		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	6		T16	2		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	13		T61	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T140	1		T152	14		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	3		T46	6		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T137	1		T40	2		T26	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1618	1			T6	3		T8	36		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	12		T39	8		T29	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T154	13		T168	9		T243	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T215	8		T262	14		T248	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T286	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	11		T147	15		T142	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	10		T39	1		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T48	2		T15	3		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T144	5		T156	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	3		T51	4		T249	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	11		T202	2		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T46	10		T27	9		T193	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T137	2		T26	11		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T40	1		T155	28		T193	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	6		T17	1		T175	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	3		T40	5		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	2		T16	1		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	10		T61	1		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T140	4		T156	1		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	2		T46	4		T15	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T137	11		T40	1		T26	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T50	11		T25	7		T33	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	13		T39	3		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	1		T16	3		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	1		T39	2		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	3		T15	5		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	2		T39	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	5		T40	1		T27	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	12		T151	15		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	11		T32	5		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T1	1		T38	1		T137	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	2		T40	2		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	7		T42	5		T175	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	4		T43	1		T40	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	7		T16	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T6	3		T8	3		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T140	5		T26	8		T230	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	3		T46	5		T15	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T137	12		T40	3		T230	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T44	1		T29	1		T42	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	14		T39	7		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T275	1		T204	5		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T157	1		T262	15		T248	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17000	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T9	11		T140	12		T167	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	19		T16	2		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	13		T148	10		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T48	7		T151	4		T167	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	11		T158	10		T246	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	2		T51	4		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	8		T151	12		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	10		T32	2		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T26	8		T17	1		T187	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	1		T155	12		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	7		T169	4		T239	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	14		T40	3		T176	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	1		T16	1		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T8	33		T48	12		T28	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T26	13		T230	9		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T9	2		T46	5		T15	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T230	12		T240	4		T189	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T44	12		T29	3		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	11		T39	4		T29	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T204	2		T177	17		T299	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T262	22		T248	15		T325	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T198	15		T240	2		T98	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T9	12		T167	11		T284	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T154	14		T168	10		T243	25
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T137	1		T29	1		T215	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T198	1		T286	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T194	3		T323	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T143	12		T147	16		T142	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	11		T10	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T48	3		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	2		T31	1		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	5		T40	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	12		T39	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	11		T27	10		T193	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T38	1		T137	3		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T40	2		T32	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T12	7		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T9	4		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	7		T16	2		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	11		T61	2		T149	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T140	5		T152	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	3		T46	5		T15	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T137	12		T40	3		T26	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T6	3		T8	3		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	14		T39	7		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T154	14		T243	18		T289	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T29	2		T215	15		T262	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T198	15		T286	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T147	11		T240	2		T326	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	12		T10	13		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	19		T48	7		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T148	21		T156	6		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	2		T167	9		T51	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	8		T155	10		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	10		T193	7		T249	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T26	8		T151	12		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	1		T32	2		T155	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	7		T17	1		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	14		T40	3		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	1		T16	1		T238	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	12		T242	13		T161	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T152	13		T157	11		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	2		T46	5		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T26	13		T230	9		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T8	33		T44	12		T28	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	11		T39	4		T29	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28