Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22841

1

T1

2

T2

165

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3247

1

T1

1

T3

2

T9

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20109

1

T1

1

T2

165

T4

20

auto[1]

5979

1

T1

2

T3

47

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T316	7		T284	14		T252	10
values[0]	98	1			T31	1		T230	17		T253	15
values[1]	851	1			T3	25		T44	13		T39	1
values[2]	655	1			T9	5		T40	3		T15	18
values[3]	683	1			T38	5		T40	3		T141	1
values[4]	839	1			T1	1		T39	11		T29	3
values[5]	568	1			T3	2		T38	1		T46	21
values[6]	734	1			T3	20		T9	23		T10	14
values[7]	541	1			T1	1		T48	10		T26	20
values[8]	2911	1			T6	3		T8	36		T9	18
values[9]	1228	1			T1	1		T12	14		T137	3
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1056	1			T3	25		T44	13		T39	1
values[1]	574	1			T9	5		T38	5		T137	1
values[2]	858	1			T141	1		T15	13		T153	1
values[3]	797	1			T1	1		T38	1		T46	21
values[4]	663	1			T3	22		T39	2		T31	2
values[5]	585	1			T1	1		T9	23		T10	14
values[6]	2822	1			T6	3		T8	36		T11	2
values[7]	625	1			T9	18		T48	23		T137	12
values[8]	908	1			T1	1		T10	20		T12	14
values[9]	231	1			T137	3		T15	2		T152	14
minimum	16969	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	12		T140	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T44	13		T39	1		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	8		T29	4		T149	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	3		T38	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T141	1		T15	2		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	6		T167	8		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T38	1		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T46	11		T39	8		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	9		T39	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T31	1		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	8		T26	9		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T9	13		T10	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T6	3		T8	36		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T43	1		T144	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	15		T16	2		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	13		T137	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	1		T10	20		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T61	2		T40	2		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T137	1		T15	1		T154	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T152	14		T276	1		T321	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T327	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	13		T140	4		T42	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T144	7		T187	11		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	10		T149	23		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T9	2		T38	3		T312	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	3		T182	4		T18	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	2		T197	13		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	7		T242	7		T232	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T46	10		T39	3		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	11		T39	1		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T3	1		T151	4		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	2		T26	11		T266	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T9	10		T46	4		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T50	11		T25	7		T33	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T144	5		T264	10		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	3		T16	1		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	10		T137	11		T140	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	6		T40	5		T26	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T61	1		T40	1		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T137	2		T15	1		T154	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T321	8		T178	14		T316	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T327	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T284	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T316	1		T252	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T230	10		T253	15		T190	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T31	1		T328	18		T302	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	12		T140	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T44	13		T39	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	8		T149	2		T193	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	3		T40	3		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T141	1		T15	2		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T38	2		T40	2		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T29	3		T42	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T39	8		T167	8		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T38	1		T31	1		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	1		T46	11		T230	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	9		T39	1		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	13		T10	14		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T48	8		T26	9		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T228	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T6	3		T8	36		T9	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	1		T48	13		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T1	1		T12	8		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T61	2		T40	2		T16	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T284	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T316	6		T252	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T230	7		T190	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T328	13		T302	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	13		T140	4		T42	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T144	7		T187	11		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	10		T149	23		T193	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	2		T197	13		T329	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	3		T144	5		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T38	3		T40	1		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T42	7		T189	24		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	3		T147	15		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T151	14		T143	9		T155	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T3	1		T46	10		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T39	1		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	10		T46	4		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	2		T26	11		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T144	5		T249	7		T248	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T9	3		T50	11		T25	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T48	10		T137	11		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T12	6		T137	2		T40	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T61	1		T40	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T3	14		T140	5		T42	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T44	1		T39	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	12		T29	1		T149	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T9	3		T38	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T141	1		T15	5		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T15	7		T167	1		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T38	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T46	11		T39	7		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	12		T39	2		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	2		T31	1		T32	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	3		T26	12		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	1		T9	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T6	3		T8	3		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T43	1		T144	6		T264	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	4		T16	2		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	11		T137	12		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T1	1		T10	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T61	3		T40	3		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T137	3		T15	2		T154	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T152	1		T276	1		T321	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T327	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	11		T230	9		T156	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T44	12		T29	9		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	6		T29	3		T198	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T9	2		T40	2		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T240	15		T189	19		T303	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	1		T167	7		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T29	2		T42	3		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	10		T39	4		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	8		T151	12		T147	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T32	2		T151	13		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	7		T26	8		T241	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	12		T10	13		T46	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T8	33		T28	12		T272	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T240	4		T19	4		T289	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	14		T16	1		T169	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	12		T244	12		T273	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	19		T12	7		T40	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	2		T151	4		T167	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T154	14		T241	6		T330	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T152	13		T321	9		T331	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T327	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T284	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T316	7		T252	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T230	8		T253	1		T190	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T31	1		T328	14		T302	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	14		T140	5		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	1		T39	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	12		T149	25		T193	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	3		T40	1		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	1		T15	5		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	5		T40	2		T15	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T29	1		T42	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T39	7		T167	1		T147	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	1		T31	1		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T3	2		T46	11		T230	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	12		T39	2		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	11		T10	1		T46	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	3		T26	12		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	1		T228	1		T144	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T6	3		T8	3		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	1		T48	11		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T1	1		T12	7		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T61	3		T40	3		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T284	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T230	9		T253	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T328	17		T302	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T156	6		T176	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T44	12		T29	9		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	6		T193	8		T249	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	2		T40	2		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T29	3		T198	15		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	1		T15	1		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	2		T42	3		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T39	4		T167	7		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	12		T155	12		T215	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T46	10		T230	12		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	8		T147	14		T241	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	12		T10	13		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	7		T26	8		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T240	4		T249	7		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T8	33		T9	14		T10	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T48	12		T244	12		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	7		T40	3		T26	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T16	2		T151	4		T152	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28