Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22598

1

T1

2

T2

165

T3

25

auto[ADC_CTRL_FILTER_COND_OUT]

3490

1

T1

1

T3

22

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19467

1

T1

2

T2

163

T4

20

auto[1]

6621

1

T1

1

T2

2

T3

47

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	722	1			T2	2		T5	1		T7	4
values[0]	34	1			T243	9		T273	4		T314	20
values[1]	633	1			T61	1		T26	21		T16	5
values[2]	2917	1			T1	1		T6	3		T8	36
values[3]	666	1			T141	1		T15	18		T41	1
values[4]	711	1			T46	21		T39	3		T27	10
values[5]	767	1			T3	25		T9	18		T44	13
values[6]	727	1			T1	1		T3	20		T9	23
values[7]	666	1			T1	1		T3	2		T12	14
values[8]	528	1			T10	14		T39	11		T137	1
values[9]	1224	1			T10	20		T43	1		T46	10
minimum	16493	1			T2	163		T4	20		T5	102

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	632	1			T9	5		T61	1		T26	21
values[1]	2917	1			T1	1		T6	3		T8	36
values[2]	558	1			T141	1		T15	18		T27	10
values[3]	868	1			T9	18		T46	21		T39	3
values[4]	697	1			T1	1		T3	45		T44	13
values[5]	791	1			T1	1		T9	23		T38	6
values[6]	565	1			T3	2		T12	14		T61	2
values[7]	587	1			T10	14		T39	11		T137	1
values[8]	1189	1			T10	20		T43	1		T48	10
values[9]	116	1			T46	10		T48	23		T31	1
minimum	17168	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	3		T61	1		T26	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	12		T155	11		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T1	1		T6	3		T8	36
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T182	1		T158	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T141	1		T230	10		T158	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	8		T27	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T229	1		T157	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T9	15		T46	11		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T3	12		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	9		T44	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	13		T38	1		T151	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T38	2		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T61	1		T32	7		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T12	8		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	14		T137	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	8		T140	1		T151	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T43	1		T48	8		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T10	20		T26	9		T29	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T46	6		T48	13		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T31	1		T18	1		T83	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16845	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	1		T237	1		T176	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T26	7		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T155	14		T244	4		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T50	11		T25	7		T33	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T15	1		T182	16		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T230	7		T158	7		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	10		T27	9		T201	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	1		T144	5		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	3		T46	10		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	13		T40	1		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	11		T137	11		T51	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	10		T151	16		T147	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	3		T137	2		T40	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T61	1		T17	1		T187	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	1		T12	6		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T140	11		T202	2		T175	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T39	3		T140	4		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T48	2		T15	3		T155	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T26	11		T149	13		T230	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T46	4		T48	10		T168	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T18	5		T83	1		T88	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T42	4		T237	10		T176	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	536	1			T2	2		T5	1		T7	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T315	1		T88	1		T101	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T243	6		T273	4		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T314	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T61	1		T26	14		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	1		T148	12		T155	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T1	1		T6	3		T8	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	1		T182	1		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T141	1		T230	10		T158	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	8		T41	1		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T229	1		T157	1		T166	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	11		T39	2		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	12		T15	6		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	15		T44	13		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T9	13		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	9		T38	2		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T38	1		T61	1		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T3	1		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	14		T137	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	8		T140	1		T154	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T43	1		T46	6		T48	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T10	20		T26	9		T29	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16368	1			T2	163		T4	20		T5	102
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T48	10		T15	3		T193	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T88	1		T101	8		T22	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T243	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T314	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	7		T16	1		T231	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T42	4		T155	14		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T9	2		T50	11		T25	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	1		T182	16		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T230	7		T158	7		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	10		T201	8		T187	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T182	4		T35	3		T279	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	10		T39	1		T27	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	13		T15	2		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	3		T137	11		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	10		T40	1		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	11		T38	3		T137	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T61	1		T151	2		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	1		T12	6		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	11		T202	2		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	3		T140	4		T154	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T46	4		T48	2		T155	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T26	11		T149	13		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	3		T61	1		T26	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	1		T155	15		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	1		T6	3		T8	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	2		T182	17		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T230	8		T158	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	12		T27	10		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T229	1		T157	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	4		T46	11		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	1		T3	14		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	12		T44	1		T137	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	11		T38	1		T151	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T38	5		T137	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T61	2		T32	5		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	2		T12	7		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T137	1		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	7		T140	5		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T43	1		T48	3		T15	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T10	1		T26	12		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T46	5		T48	11		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T31	1		T18	6		T83	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16985	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T42	5		T237	11		T176	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	2		T26	13		T16	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T148	11		T155	10		T269	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T8	33		T28	12		T272	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T158	10		T311	8		T263	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T230	9		T158	12		T176	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	6		T187	4		T241	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T166	2		T304	10		T288	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T9	14		T46	10		T42	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	11		T40	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	8		T44	12		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	12		T151	16		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	3		T16	1		T189	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T32	2		T17	1		T187	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	7		T40	2		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	13		T152	13		T241	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	4		T151	13		T154	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	7		T29	3		T167	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T10	19		T26	8		T29	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T46	5		T48	12		T179	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T273	3		T251	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T176	10		T314	8		T306	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	567	1			T2	2		T5	1		T7	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T315	1		T88	2		T101	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T243	4		T273	1		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T314	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T61	1		T26	8		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	5		T148	1		T155	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T1	1		T6	3		T8	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	2		T182	17		T158	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T141	1		T230	8		T158	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	12		T41	1		T201	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T229	1		T157	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T46	11		T39	3		T27	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	14		T15	7		T149	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	4		T44	1		T137	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T9	11		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	12		T38	5		T137	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	1		T61	2		T32	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T3	2		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	1		T137	1		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	7		T140	5		T154	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T43	1		T46	5		T48	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T10	1		T26	12		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T2	163		T4	20		T5	102
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T48	12		T148	10		T193	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T101	10		T313	14		T191	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T243	5		T273	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T314	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T26	13		T16	2		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T148	11		T155	10		T269	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T8	33		T9	2		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T158	10		T311	8		T263	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T230	9		T158	12		T176	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	6		T187	4		T241	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T166	2		T204	2		T288	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	10		T42	3		T240	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	11		T15	1		T166	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	14		T44	12		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	12		T40	1		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	8		T40	3		T189	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T32	2		T151	4		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	7		T40	2		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	13		T249	7		T98	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	4		T154	14		T198	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T46	5		T48	7		T29	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T10	19		T26	8		T29	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28