Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20315

1

T1

1

T2

165

T3

47

auto[ADC_CTRL_FILTER_COND_OUT]

5773

1

T1

2

T6

3

T8

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19890

1

T1

3

T2

165

T3

45

auto[1]

6198

1

T3

2

T6

3

T8

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T39	12		T31	1		T16	3
values[0]	28	1			T18	6		T177	17		T259	4
values[1]	727	1			T3	2		T43	1		T61	2
values[2]	643	1			T12	14		T44	13		T46	10
values[3]	724	1			T9	23		T38	6		T137	1
values[4]	625	1			T1	1		T10	14		T39	2
values[5]	695	1			T137	3		T15	5		T29	10
values[6]	669	1			T1	1		T3	20		T9	23
values[7]	616	1			T1	1		T46	21		T26	20
values[8]	631	1			T3	25		T10	20		T40	3
values[9]	3532	1			T6	3		T8	36		T11	2
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	742	1			T3	2		T43	1		T44	13
values[1]	2865	1			T6	3		T8	36		T11	2
values[2]	724	1			T9	23		T38	6		T61	1
values[3]	592	1			T1	1		T10	14		T39	2
values[4]	652	1			T1	1		T137	3		T40	3
values[5]	714	1			T3	20		T9	23		T48	23
values[6]	654	1			T1	1		T46	21		T15	2
values[7]	711	1			T3	25		T10	20		T40	3
values[8]	1122	1			T39	1		T40	12		T140	5
values[9]	158	1			T39	11		T31	1		T143	12
minimum	17154	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T44	13		T42	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T43	1		T61	1		T26	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	8		T46	6		T48	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1547	1			T6	3		T8	36		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	18		T40	2		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	3		T61	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	14		T39	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T182	1		T241	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T137	1		T40	2		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	1		T15	2		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	9		T29	4		T151	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	13		T48	13		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T46	11		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	9		T230	13		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	12		T40	3		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	20		T27	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T40	7		T140	1		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T39	1		T15	8		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T31	1		T257	1		T258	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T39	8		T143	1		T166	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16874	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T262	23		T168	1		T164	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T42	11		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T61	1		T26	7		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	6		T46	4		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1014	1			T50	11		T140	11		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	5		T40	1		T230	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	3		T151	14		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	1		T144	5		T187	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T182	16		T255	3		T256	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T137	2		T40	1		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	3		T17	1		T187	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	11		T151	4		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	10		T48	10		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	10		T15	1		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T26	11		T230	14		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	13		T175	1		T182	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T27	9		T149	13		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	5		T140	4		T155	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T15	10		T16	1		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T258	10		T172	8		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T39	3		T143	11		T332	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T262	14		T168	9		T259	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T31	1		T274	1		T333	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T39	9		T16	2		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T18	1		T93	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T177	17		T259	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T42	8		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	1		T61	1		T26	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	8		T44	13		T46	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T140	1		T15	6		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	18		T230	10		T242	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	3		T137	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	14		T39	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T146	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	1		T31	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	2		T29	10		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	9		T40	2		T29	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T9	13		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T46	11		T167	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T26	9		T230	13		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	12		T40	3		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	20		T149	1		T151	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T40	7		T140	1		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1719	1			T6	3		T8	36		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T333	1		T260	12		T281	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T39	3		T16	1		T182	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T18	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T259	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T42	11		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T61	1		T26	7		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	6		T46	4		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T140	11		T15	2		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	5		T230	7		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	3		T151	14		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T39	1		T40	1		T187	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T182	16		T255	3		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T137	2		T144	5		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	3		T187	4		T266	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	11		T40	1		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	10		T48	10		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	10		T147	12		T321	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	11		T230	14		T147	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	13		T15	1		T182	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T149	13		T151	2		T156	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T40	5		T140	4		T175	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1160	1			T50	11		T15	10		T25	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	2		T44	1		T42	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T43	1		T61	2		T26	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	7		T46	5		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1340	1			T6	3		T8	3		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	7		T40	2		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	6		T61	1		T32	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	1		T39	2		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	1		T182	17		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T137	3		T40	3		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T15	5		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	12		T29	1		T151	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	11		T48	11		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T46	11		T15	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T26	12		T230	15		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	14		T40	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	1		T27	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T40	9		T140	5		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T39	1		T15	12		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T31	1		T257	1		T258	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T39	7		T143	12		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17006	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T262	15		T168	10		T164	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T44	12		T42	3		T189	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	13		T17	1		T215	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	7		T46	5		T48	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1221	1			T8	33		T15	1		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	16		T40	1		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	2		T151	12		T157	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	13		T187	8		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T241	6		T169	8		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T238	4		T231	15		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	9		T187	4		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	8		T29	3		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	12		T48	12		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	10		T147	9		T198	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	8		T230	12		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	11		T40	2		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	19		T151	4		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T40	3		T155	12		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T15	6		T16	1		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T258	10		T172	8		T334	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T39	4		T166	2		T260	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T154	14		T51	4		T148	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T262	22		T273	1		T177	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T31	1		T274	1		T333	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T39	8		T16	2		T182	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T18	6		T93	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T177	2		T259	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	2		T42	16		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	1		T61	2		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	7		T44	1		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T140	12		T15	7		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	7		T230	8		T242	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T38	6		T137	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	1		T39	2		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T1	1		T146	1		T182	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T137	3		T31	1		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	5		T29	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	12		T40	3		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T9	11		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T46	11		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	12		T230	15		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	14		T40	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T149	14		T151	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T40	9		T140	5		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1512	1			T6	3		T8	3		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T333	8		T260	11		T335	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	4		T16	1		T187	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T177	15		T259	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T42	3		T154	14		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	13		T262	22		T243	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	7		T44	12		T46	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	1		T17	1		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	16		T230	9		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T32	2		T151	12		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	13		T40	1		T187	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T241	6		T169	8		T256	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T238	4		T231	15		T19	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	9		T187	4		T189	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	8		T29	3		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	12		T48	12		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T46	10		T167	9		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T26	8		T230	12		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	11		T40	2		T198	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	19		T151	4		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T40	3		T155	12		T156	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1367	1			T8	33		T15	6		T28	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28