Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22307

1

T1

2

T2

165

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3781

1

T1

1

T3

47

T9

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20021

1

T1

1

T2

165

T3

2

auto[1]

6067

1

T1

2

T3

45

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T42	14		T336	1		T337	15
values[0]	68	1			T187	9		T194	3		T198	16
values[1]	557	1			T9	23		T10	14		T39	2
values[2]	772	1			T3	2		T10	20		T48	10
values[3]	673	1			T3	20		T38	5		T39	1
values[4]	791	1			T38	1		T46	21		T137	3
values[5]	692	1			T1	2		T12	14		T40	3
values[6]	702	1			T1	1		T9	18		T43	1
values[7]	652	1			T48	23		T40	12		T140	5
values[8]	792	1			T9	5		T46	10		T137	12
values[9]	3409	1			T3	25		T6	3		T8	36
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	877	1			T10	34		T39	2		T140	12
values[1]	607	1			T3	2		T48	10		T39	1
values[2]	729	1			T3	20		T40	3		T27	10
values[3]	766	1			T1	1		T38	6		T46	21
values[4]	642	1			T1	2		T12	14		T40	3
values[5]	760	1			T9	18		T43	1		T61	2
values[6]	3105	1			T6	3		T8	36		T11	2
values[7]	552	1			T9	5		T46	10		T137	12
values[8]	761	1			T3	25		T39	11		T29	17
values[9]	294	1			T44	13		T137	1		T157	1
minimum	16995	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	20		T16	4		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T10	14		T39	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	8		T15	2		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T39	1		T338	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T40	3		T27	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	9		T151	13		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T38	2		T46	11		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T38	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	2		T40	2		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	8		T15	1		T26	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	15		T43	1		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	6		T16	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T6	3		T8	36		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T140	1		T26	14		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	3		T46	6		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	1		T230	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T29	4		T42	7		T167	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	12		T39	8		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T44	13		T168	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T137	1		T157	1		T215	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T9	13		T284	8		T339	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	1		T143	11		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	1		T140	11		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T48	2		T15	3		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T158	13		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T27	9		T51	4		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	11		T151	14		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	3		T46	10		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T137	2		T17	1		T185	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	1		T155	16		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	6		T15	1		T26	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	3		T61	1		T40	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	2		T16	1		T250	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T48	10		T50	11		T25	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T140	4		T26	7		T230	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	2		T46	4		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	11		T230	14		T143	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T42	7		T154	13		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	13		T39	3		T147	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T168	9		T160	16		T88	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T215	8		T248	20		T305	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T9	10		T284	6		T339	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T42	7		T340	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T336	1		T337	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T198	16		T286	2		T341	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T187	5		T194	3		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T143	1		T144	1		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	13		T10	14		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	20		T48	8		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	1		T31	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T38	2		T40	3		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	9		T39	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	11		T61	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T38	1		T137	1		T26	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T40	2		T155	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	1		T12	8		T32	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T9	15		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	7		T16	2		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	13		T40	7		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	1		T152	14		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	3		T46	6		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T137	1		T26	14		T230	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T6	3		T8	36		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T3	12		T39	8		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T42	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T337	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T286	1		T341	9		T342	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T187	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	11		T144	7		T147	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	10		T39	1		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	2		T15	3		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T144	5		T156	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	3		T51	4		T329	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	11		T202	2		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T46	10		T27	9		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T137	2		T26	11		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	1		T155	28		T193	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	6		T17	1		T175	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	3		T61	1		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	3		T16	1		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	10		T40	5		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T140	4		T156	1		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	2		T46	4		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T137	11		T26	7		T230	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T50	11		T25	7		T33	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	13		T39	3		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	1		T16	3		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	1		T39	2		T140	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	3		T15	5		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	2		T39	1		T338	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	1		T27	10		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	12		T151	15		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	5		T46	11		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	1		T38	1		T137	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	2		T40	2		T155	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	7		T15	2		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	4		T43	1		T61	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T15	7		T16	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T6	3		T8	3		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T140	5		T26	8		T230	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	3		T46	5		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T137	12		T230	15		T143	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T29	1		T42	11		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	14		T39	7		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T44	1		T168	10		T160	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T137	1		T157	1		T215	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T9	11		T284	7		T339	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	19		T16	2		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	13		T167	11		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T48	7		T151	4		T311	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T148	11		T158	10		T189	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	2		T167	9		T51	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	8		T151	12		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	10		T155	4		T193	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T32	2		T17	1		T187	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	1		T155	12		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	7		T26	8		T169	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	14		T40	3		T176	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	1		T16	1		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T8	33		T48	12		T28	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T26	13		T230	9		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	2		T46	5		T15	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T230	12		T240	4		T189	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	3		T42	3		T167	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	11		T39	4		T29	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T44	12		T204	2		T226	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T215	15		T248	33		T337	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T9	12		T284	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T42	11		T340	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T336	1		T337	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T198	1		T286	2		T341	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T187	5		T194	3		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T143	12		T144	8		T147	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	11		T10	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	1		T48	3		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	2		T31	1		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	5		T40	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	12		T39	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	11		T61	1		T27	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T38	1		T137	3		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T40	2		T155	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T12	7		T32	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T9	4		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	9		T16	2		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	11		T40	9		T149	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T140	5		T152	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	3		T46	5		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T137	12		T26	8		T230	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T6	3		T8	3		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T3	14		T39	7		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T42	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T337	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T198	15		T286	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T187	4		T320	12		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T147	11		T240	2		T311	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	12		T10	13		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	19		T48	7		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T148	21		T156	6		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	2		T167	9		T51	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	8		T155	10		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	10		T193	7		T249	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	8		T151	12		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	1		T155	16		T193	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	7		T32	2		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	14		T156	4		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	1		T16	1		T238	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T48	12		T40	3		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	13		T157	11		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	2		T46	5		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T26	13		T230	9		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T8	33		T44	12		T28	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	11		T39	4		T29	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28