Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22904

1

T1

2

T2

165

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3184

1

T1

1

T3

2

T9

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20150

1

T1

1

T2

165

T3

2

auto[1]

5938

1

T1

2

T3

45

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	333	1			T12	14		T40	3		T15	2
values[0]	58	1			T31	1		T253	15		T328	31
values[1]	851	1			T3	25		T44	13		T39	1
values[2]	684	1			T9	5		T38	5		T137	1
values[3]	711	1			T40	3		T141	1		T15	13
values[4]	825	1			T1	1		T39	11		T29	3
values[5]	588	1			T3	22		T38	1		T46	21
values[6]	702	1			T9	23		T10	14		T46	10
values[7]	543	1			T1	1		T48	10		T26	20
values[8]	2934	1			T6	3		T8	36		T9	18
values[9]	910	1			T1	1		T10	20		T137	3
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	796	1			T44	13		T39	1		T29	10
values[1]	692	1			T9	5		T38	5		T137	1
values[2]	800	1			T141	1		T15	13		T153	1
values[3]	722	1			T1	1		T38	1		T46	21
values[4]	682	1			T3	22		T39	2		T31	2
values[5]	556	1			T1	1		T9	23		T10	14
values[6]	2944	1			T6	3		T8	36		T11	2
values[7]	580	1			T1	1		T9	18		T48	23
values[8]	914	1			T10	20		T12	14		T137	3
values[9]	186	1			T15	2		T152	14		T154	28
minimum	17216	1			T2	165		T3	25		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T42	1		T202	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T44	13		T39	1		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T15	8		T29	4		T149	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	3		T38	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T141	1		T15	2		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	6		T155	11		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	1		T38	1		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T46	11		T39	8		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	9		T39	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T31	1		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	9		T229	1		T241	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T9	13		T10	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T6	3		T8	36		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	1		T48	8		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T9	15		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	13		T140	1		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	20		T12	8		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T61	1		T40	2		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T15	1		T154	15		T241	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T152	14		T276	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16909	1			T2	165		T3	12		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T31	1		T253	11		T177	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T42	4		T202	2		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T144	7		T187	11		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	10		T149	23		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T9	2		T38	3		T100	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	3		T182	4		T18	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	2		T155	14		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T42	7		T232	6		T255	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	10		T39	3		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	11		T39	1		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T3	1		T151	4		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T26	11		T266	9		T249	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T9	10		T46	4		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T50	11		T25	7		T33	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T48	2		T137	11		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	3		T26	7		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	10		T140	11		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	6		T137	2		T61	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	1		T16	1		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T15	1		T154	13		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T178	14		T316	6		T343	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	13		T40	1		T140	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T328	13		T317	16		T252	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	8		T15	1		T228	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T40	2		T16	4		T151	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T253	15		T190	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T31	1		T328	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	12		T140	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T44	13		T39	1		T29	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	8		T149	2		T193	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	3		T38	2		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T141	1		T15	2		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T40	2		T15	6		T155	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T29	3		T42	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T39	8		T167	8		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	9		T38	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T46	11		T230	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T39	1		T229	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	13		T10	14		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T26	9		T153	1		T51	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T48	8		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T6	3		T8	36		T9	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	1		T48	13		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T10	20		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T61	1		T182	1		T242	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	6		T15	1		T156	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T40	1		T16	1		T151	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T190	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T328	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	13		T140	4		T42	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	7		T187	11		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	10		T149	23		T193	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	2		T38	3		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	3		T144	5		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T40	1		T15	2		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T42	7		T255	3		T189	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	3		T147	15		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	11		T151	14		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	1		T46	10		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	1		T147	12		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	10		T46	4		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T26	11		T51	4		T257	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T48	2		T144	5		T264	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T9	3		T50	11		T25	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	10		T137	11		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T137	2		T61	1		T40	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T182	16		T242	7		T176	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T42	5		T202	3		T156	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T44	1		T39	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T15	12		T29	1		T149	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	3		T38	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T141	1		T15	5		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T15	7		T155	15		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T38	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T46	11		T39	7		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	12		T39	2		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	2		T31	1		T32	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	12		T229	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T9	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T6	3		T8	3		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	1		T48	3		T137	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T9	4		T26	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	11		T140	12		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T10	1		T12	7		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T61	1		T40	3		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T15	2		T154	14		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T152	1		T276	1		T178	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17044	1			T2	165		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T31	1		T253	1		T177	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T193	8		T176	5		T322	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T44	12		T29	9		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	6		T29	3		T156	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	2		T40	2		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T242	7		T240	15		T189	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	1		T155	10		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T29	2		T42	3		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	10		T39	4		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	8		T151	12		T147	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T32	2		T151	13		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	8		T241	8		T249	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	12		T10	13		T46	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T8	33		T28	12		T272	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T48	7		T240	4		T36	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	14		T26	13		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	12		T246	12		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	19		T12	7		T40	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T16	2		T151	4		T193	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T154	14		T241	6		T330	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T152	13		T343	14		T344	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T3	11		T230	9		T169	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T253	10		T177	14		T328	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	7		T15	2		T228	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T40	3		T16	3		T151	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T253	1		T190	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T31	1		T328	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	14		T140	5		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T44	1		T39	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	12		T149	25		T193	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	3		T38	5		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T141	1		T15	5		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	2		T15	7		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T29	1		T42	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T39	7		T167	1		T147	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	12		T38	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	2		T46	11		T230	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	2		T229	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	11		T10	1		T46	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	12		T153	1		T51	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T1	1		T48	3		T144	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T6	3		T8	3		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	1		T48	11		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	1		T10	1		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T61	1		T182	17		T242	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T12	7		T167	9		T156	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T16	2		T151	4		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T253	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T328	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	11		T230	9		T156	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	12		T29	9		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	6		T193	8		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	2		T40	2		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T29	3		T198	15		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	1		T15	1		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	2		T42	3		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T39	4		T167	7		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	8		T151	12		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T46	10		T230	12		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T147	14		T241	8		T249	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	12		T10	13		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T26	8		T51	4		T239	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	7		T240	4		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T8	33		T9	14		T28	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T48	12		T244	12		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	19		T40	3		T26	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T242	13		T176	10		T246	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28