Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22730

1

T1

1

T2

165

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3358

1

T1

2

T3

47

T9

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19890

1

T1

3

T2

165

T3

47

auto[1]

6198

1

T6

3

T8

36

T9

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	232	1			T44	13		T40	3		T144	6
values[0]	89	1			T167	8		T241	5		T176	22
values[1]	817	1			T46	10		T39	11		T61	1
values[2]	560	1			T48	23		T31	1		T144	6
values[3]	739	1			T1	1		T10	14		T46	21
values[4]	514	1			T38	1		T40	15		T149	14
values[5]	2977	1			T3	27		T6	3		T8	36
values[6]	653	1			T26	20		T29	4		T41	1
values[7]	725	1			T137	12		T140	12		T27	10
values[8]	726	1			T1	1		T3	20		T12	14
values[9]	1107	1			T1	1		T9	23		T10	20
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T46	10		T48	23		T39	11
values[1]	468	1			T1	1		T46	21		T29	3
values[2]	698	1			T10	14		T40	15		T15	5
values[3]	2965	1			T3	25		T6	3		T8	36
values[4]	679	1			T3	2		T9	5		T137	3
values[5]	559	1			T26	20		T29	4		T41	1
values[6]	719	1			T1	1		T38	5		T137	12
values[7]	939	1			T3	20		T12	14		T48	10
values[8]	847	1			T1	1		T9	23		T10	20
values[9]	142	1			T246	13		T83	21		T273	2
minimum	17312	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T46	6		T39	8		T15	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	13		T61	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T46	11		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	3		T182	1		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	14		T40	3		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	7		T228	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T6	3		T8	36		T9	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	12		T38	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T202	1		T146	1		T275	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T9	3		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T26	9		T29	4		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T230	13		T276	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T137	1		T140	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T38	2		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	8		T140	1		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	9		T48	8		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T9	13		T10	20		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T43	1		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T246	13		T83	10		T273	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T277	2		T284	12		T307	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16950	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T167	8		T35	1		T189	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T46	4		T39	3		T15	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	10		T18	5		T266	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T46	10		T144	5		T185	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T182	4		T254	10		T231	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	3		T175	1		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	5		T17	1		T155	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T9	3		T50	11		T25	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	13		T39	1		T61	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T202	2		T279	2		T88	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T9	2		T137	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T26	11		T143	11		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T230	14		T250	7		T345	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T137	11		T140	11		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	3		T27	9		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	6		T140	4		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	11		T48	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	10		T40	1		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T16	1		T144	5		T147	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T83	11		T178	13		T281	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T277	2		T284	12		T307	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T189	12		T337	6		T179	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T40	2		T148	12		T242	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	13		T144	1		T311	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T241	5		T176	11		T285	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T167	8		T35	1		T179	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T46	6		T39	8		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T61	1		T32	7		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	1		T185	1		T156	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	13		T31	1		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	1		T10	14		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	3		T228	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	3		T175	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	1		T40	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T6	3		T8	36		T9	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	13		T9	3		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T26	9		T29	4		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T230	13		T167	10		T241	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	1		T140	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	1		T143	1		T274	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	8		T140	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T3	9		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T9	13		T10	20		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	1		T40	2		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T40	1		T242	7		T249	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T144	5		T311	5		T248	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T176	11		T285	7		T286	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T179	4		T252	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	4		T39	3		T15	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T182	4		T18	5		T189	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T144	5		T185	2		T156	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	10		T254	10		T266	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T46	10		T15	3		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	1		T155	16		T248	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T175	1		T182	16		T187	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T40	5		T149	13		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T9	3		T50	11		T25	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	14		T9	2		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T26	11		T249	3		T279	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T230	14		T262	14		T280	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	11		T140	11		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	9		T143	8		T168	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	6		T140	4		T26	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	11		T38	3		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T9	10		T15	1		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	1		T15	2		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T46	5		T39	7		T15	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T48	11		T61	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	1		T46	11		T144	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	1		T182	5		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	1		T40	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	9		T228	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T6	3		T8	3		T9	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	14		T38	1		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T202	3		T146	1		T275	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	2		T9	3		T137	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T26	12		T29	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T230	15		T276	1		T250	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T137	12		T140	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T38	5		T27	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	7		T140	5		T15	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	12		T48	3		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	11		T10	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T43	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T246	1		T83	12		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T277	4		T284	13		T307	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T167	1		T35	1		T189	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	5		T39	4		T15	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T48	12		T32	2		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T46	10		T176	12		T19	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T29	2		T238	20		T253	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	13		T40	2		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	3		T17	1		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T8	33		T9	14		T28	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	11		T42	3		T151	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T253	17		T287	1		T177	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	2		T167	9		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T26	8		T29	3		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T230	12		T253	14		T289	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T166	9		T262	13		T243	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	4		T262	22		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	7		T26	13		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	8		T48	7		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	12		T10	19		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T44	12		T16	1		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T246	12		T83	9		T273	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T284	11		T307	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T241	4		T176	10		T303	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T167	7		T189	10		T337	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T40	3		T148	1		T242	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T44	1		T144	6		T311	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T241	1		T176	12		T285	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T167	1		T35	1		T179	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T46	5		T39	7		T15	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T61	1		T32	5		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T144	6		T185	3		T156	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	11		T31	1		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	1		T10	1		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	1		T228	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T40	1		T175	2		T182	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	1		T40	9		T149	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T6	3		T8	3		T9	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T3	16		T9	3		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T26	12		T29	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T230	15		T167	1		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T137	12		T140	12		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T27	10		T143	9		T274	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	7		T140	5		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T3	12		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T9	11		T10	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	1		T40	2		T15	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T148	11		T242	13		T249	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T44	12		T311	8		T248	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T241	4		T176	10		T285	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T167	7		T179	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T46	5		T39	4		T15	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T32	2		T240	2		T189	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T156	6		T258	10		T19	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	12		T249	7		T231	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	13		T46	10		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T29	2		T17	1		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T40	2		T187	11		T198	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	3		T151	12		T147	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T8	33		T9	14		T28	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	11		T9	2		T42	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T26	8		T29	3		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T230	12		T167	9		T241	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T166	9		T155	10		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T289	12		T288	4		T226	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	7		T26	13		T29	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	8		T48	7		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T9	12		T10	19		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	1		T15	1		T16	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28