Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	2		T44	1		T42	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T43	1		T61	2		T26	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	7		T46	5		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1357	1			T6	3		T8	3		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	7		T40	2		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	6		T61	1		T32	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	1		T39	2		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	1		T182	17		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T137	3		T40	3		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T15	5		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	12		T46	11		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	11		T48	11		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T15	2		T147	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	12		T230	15		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	14		T40	1		T140	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T27	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T40	9		T228	1		T155	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T39	1		T15	12		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T31	1		T153	1		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T39	7		T143	12		T155	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16960	1			T2	165		T4	20		T5	103
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	12		T42	3		T154	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T26	13		T17	1		T215	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	7		T46	5		T48	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1229	1			T8	33		T15	1		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	16		T40	1		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	2		T151	12		T157	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	13		T187	8		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T241	6		T169	8		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T238	4		T231	15		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	9		T187	4		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	8		T46	10		T29	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	12		T48	12		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T147	9		T176	5		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	8		T230	12		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T40	2		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	19		T148	11		T142	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T40	3		T155	12		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	6		T16	1		T166	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T241	8		T258	10		T260	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T39	4		T155	10		T260	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T261	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T250	8		T251	22		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T168	10		T93	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T253	1		T177	2		T259	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	2		T42	16		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	1		T61	2		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	7		T44	1		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T140	12		T15	7		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	7		T149	11		T230	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	6		T137	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	1		T39	2		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	1		T15	5		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	3		T31	1		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	1		T41	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	12		T40	3		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T9	11		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T46	11		T147	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	12		T153	1		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	14		T40	1		T140	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T149	14		T230	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T40	9		T31	1		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T6	3		T8	3		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T251	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T253	14		T177	15		T259	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T42	3		T154	14		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	13		T262	22		T243	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	7		T44	12		T46	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T17	1		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	16		T230	9		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	2		T151	12		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	13		T40	1		T187	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T241	6		T169	8		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T231	15		T19	4		T263	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	9		T187	4		T189	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T3	8		T29	3		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	12		T48	12		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	10		T147	9		T176	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	8		T167	11		T147	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	11		T40	2		T249	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	19		T230	12		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T40	3		T155	12		T156	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1419	1			T8	33		T39	4		T15	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28