Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22654

1

T1

3

T2

165

T3

22

auto[ADC_CTRL_FILTER_COND_OUT]

3434

1

T3

25

T9

23

T10

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19939

1

T1

1

T2

165

T3

22

auto[1]

6149

1

T1

2

T3

25

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	385	1			T48	23		T40	3		T26	20
values[0]	2	1			T228	1		T21	1		-	-
values[1]	476	1			T46	10		T39	11		T137	3
values[2]	3058	1			T1	2		T6	3		T8	36
values[3]	775	1			T140	12		T42	1		T157	12
values[4]	746	1			T1	1		T10	14		T46	21
values[5]	715	1			T3	45		T12	14		T38	5
values[6]	744	1			T10	20		T38	1		T39	2
values[7]	614	1			T61	1		T15	18		T27	10
values[8]	776	1			T44	13		T48	10		T40	3
values[9]	848	1			T3	2		T9	46		T137	1
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	562	1			T1	2		T39	11		T137	3
values[1]	2945	1			T6	3		T8	36		T11	2
values[2]	823	1			T140	12		T26	21		T42	1
values[3]	713	1			T1	1		T10	14		T46	21
values[4]	768	1			T3	45		T10	20		T12	14
values[5]	617	1			T38	1		T39	2		T15	5
values[6]	760	1			T48	10		T61	1		T15	18
values[7]	772	1			T3	2		T9	5		T44	13
values[8]	899	1			T9	41		T137	1		T40	6
values[9]	101	1			T48	23		T17	4		T264	11
minimum	17128	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	2		T39	8		T32	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T137	1		T40	7		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T6	3		T8	36		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	1		T31	1		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T26	14		T42	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T140	1		T18	1		T176	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T137	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	14		T46	11		T154	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	9		T43	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	12		T10	20		T12	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T38	1		T15	2		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	1		T27	1		T230	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T61	1		T15	8		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	8		T144	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T9	3		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	3		T15	6		T16	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	15		T137	1		T147	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	13		T40	4		T26	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T264	1		T189	11		T265	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T48	13		T17	3		T158	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T46	6		T148	3		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	3		T193	7		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T137	2		T40	5		T143	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T50	11		T25	7		T33	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T237	10		T232	11		T176	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	7		T144	5		T266	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T140	11		T18	5		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	11		T149	13		T230	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T46	10		T154	13		T187	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	11		T15	1		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	13		T12	6		T38	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	3		T42	4		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T39	1		T27	9		T230	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	10		T215	8		T232	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	2		T144	7		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T9	2		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	2		T16	1		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T9	3		T147	12		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	10		T40	2		T26	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T264	10		T189	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T48	10		T17	1		T158	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T46	4		T267	1		T268	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T147	15		T264	1		T269	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T48	13		T40	2		T26	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T228	1		T21	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	8		T29	3		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	6		T137	1		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T1	2		T6	3		T8	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	1		T31	2		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T42	1		T157	12		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T140	1		T18	1		T176	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T137	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	14		T46	11		T154	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	9		T43	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	12		T12	8		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T38	1		T167	10		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	20		T39	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T61	1		T15	8		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	1		T230	10		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T44	13		T140	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T48	8		T40	3		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	1		T9	18		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T9	13		T40	2		T16	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T147	12		T264	10		T189	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T48	10		T40	1		T26	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T39	3		T270	13		T271	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T46	4		T137	2		T40	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T50	11		T25	7		T33	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T237	10		T232	11		T176	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T144	5		T266	5		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T140	11		T18	5		T176	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T137	11		T26	7		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	10		T154	13		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	11		T15	4		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	13		T12	6		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T143	9		T51	4		T147	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T39	1		T142	1		T187	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	10		T42	4		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	9		T230	7		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	4		T151	14		T201	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	2		T15	2		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T3	1		T9	5		T249	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T9	10		T40	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	2		T39	7		T32	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T137	3		T40	9		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T6	3		T8	3		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	1		T31	1		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T26	8		T42	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T140	12		T18	6		T176	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	1		T137	12		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	1		T46	11		T154	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	12		T43	1		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	14		T10	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T38	1		T15	5		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	2		T27	10		T230	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T61	1		T15	12		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	3		T144	8		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	2		T9	3		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T40	1		T15	7		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	4		T137	1		T147	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	11		T40	5		T26	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T264	11		T189	13		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T48	11		T17	3		T158	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16995	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T46	5		T148	1		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T39	4		T32	2		T193	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	3		T166	9		T176	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T8	33		T28	12		T272	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T198	15		T176	12		T248	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T26	13		T203	8		T204	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T176	5		T249	7		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	3		T230	12		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	13		T46	10		T154	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	8		T16	1		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	11		T10	19		T12	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T167	9		T51	4		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T230	9		T152	13		T187	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	6		T215	15		T238	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	7		T147	9		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	2		T44	12		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	2		T15	1		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	14		T147	14		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	12		T40	1		T26	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T189	10		T265	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T48	12		T17	1		T158	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T29	2		T241	10		T239	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T46	5		T148	2		T267	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T147	13		T264	11		T269	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	11		T40	3		T26	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T228	1		T21	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	7		T29	1		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	5		T137	3		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	2		T6	3		T8	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	1		T31	2		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T42	1		T157	1		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	12		T18	6		T176	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T137	12		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	1		T46	11		T154	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	12		T43	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	14		T12	7		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T38	1		T167	1		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	1		T39	2		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T61	1		T15	12		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T27	10		T230	8		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T44	1		T140	5		T151	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T48	3		T40	1		T15	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	2		T9	7		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T9	11		T40	2		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T147	14		T269	7		T189	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T48	12		T26	8		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	4		T29	2		T241	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T46	5		T40	3		T148	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T8	33		T28	12		T32	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T166	9		T198	15		T176	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T157	11		T262	13		T204	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T176	5		T249	7		T248	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T26	13		T29	3		T169	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	13		T46	10		T154	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	8		T16	1		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	11		T12	7		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T167	9		T51	4		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	19		T187	8		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	6		T215	15		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T230	9		T152	13		T193	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	12		T151	12		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	7		T40	2		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	16		T167	7		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	12		T40	1		T16	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28