Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22627

1

T1

3

T2

165

T3

22

auto[ADC_CTRL_FILTER_COND_OUT]

3461

1

T3

25

T9

23

T10

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19932

1

T1

1

T2

165

T3

22

auto[1]

6156

1

T1

2

T3

25

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T229	1		T284	14		T290	10
values[0]	35	1			T228	1		T241	7		T271	25
values[1]	459	1			T46	10		T39	11		T137	3
values[2]	3000	1			T1	2		T6	3		T8	36
values[3]	827	1			T140	12		T42	1		T157	12
values[4]	779	1			T1	1		T10	14		T46	21
values[5]	626	1			T3	20		T38	5		T43	1
values[6]	791	1			T3	25		T10	20		T12	14
values[7]	638	1			T61	1		T15	18		T27	10
values[8]	734	1			T44	13		T48	10		T40	3
values[9]	1225	1			T3	2		T9	46		T48	23
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T1	2		T46	10		T39	11
values[1]	2880	1			T6	3		T8	36		T11	2
values[2]	886	1			T140	12		T42	1		T157	1
values[3]	643	1			T1	1		T10	14		T46	21
values[4]	795	1			T3	45		T10	20		T12	14
values[5]	631	1			T38	1		T39	2		T15	5
values[6]	738	1			T48	10		T61	1		T15	26
values[7]	808	1			T3	2		T9	5		T44	13
values[8]	806	1			T9	41		T137	1		T40	6
values[9]	193	1			T48	23		T26	20		T17	4
minimum	16955	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	2		T39	8		T29	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T46	6		T137	1		T40	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T6	3		T8	36		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	1		T31	1		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	1		T157	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T140	1		T266	1		T176	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T137	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	14		T46	11		T154	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	9		T43	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	12		T10	20		T12	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T38	1		T15	2		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	1		T27	1		T230	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T61	1		T15	8		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	8		T15	6		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T9	3		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T40	3		T17	1		T155	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	15		T137	1		T147	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	13		T40	4		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T264	1		T269	8		T189	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T48	13		T26	9		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16829	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T159	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	3		T193	7		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	4		T137	2		T40	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T50	11		T25	7		T33	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T197	13		T237	10		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T144	5		T182	16		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T140	11		T266	5		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	11		T26	7		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T46	10		T154	13		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	11		T15	1		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	13		T12	6		T38	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	3		T42	4		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T39	1		T27	9		T230	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	10		T215	8		T232	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	2		T15	2		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T9	2		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T17	1		T155	26		T248	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T9	3		T147	12		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	10		T40	2		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T264	10		T189	12		T291	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T48	10		T26	11		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T284	8		T290	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T228	1		T241	7		T271	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	8		T29	3		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	6		T137	1		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T1	2		T6	3		T8	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	1		T31	1		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T42	1		T157	12		T293	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	1		T18	1		T266	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T137	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	14		T46	11		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	9		T43	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	2		T61	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T38	1		T16	2		T167	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	12		T10	20		T12	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T61	1		T15	8		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T27	1		T144	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	13		T151	13		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T48	8		T40	3		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T3	1		T9	18		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T9	13		T48	13		T40	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T284	6		T290	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T39	3		T231	9		T270	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T46	4		T137	2		T40	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T50	11		T25	7		T33	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T197	13		T237	10		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T232	2		T257	1		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T140	11		T18	5		T266	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T137	11		T26	7		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	10		T149	10		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	11		T15	4		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	3		T61	1		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	1		T143	9		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	13		T12	6		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	10		T42	4		T187	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T27	9		T144	7		T193	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T151	14		T201	8		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	2		T15	2		T147	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T9	5		T140	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T9	10		T48	10		T40	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	2		T39	7		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	5		T137	3		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T6	3		T8	3		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	1		T31	1		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T42	1		T157	1		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T140	12		T266	6		T176	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T137	12		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	1		T46	11		T154	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	12		T43	1		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	14		T10	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T38	1		T15	5		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	2		T27	10		T230	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T61	1		T15	12		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	3		T15	7		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	2		T9	3		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T40	1		T17	2		T155	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	4		T137	1		T147	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T9	11		T40	5		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T264	11		T269	1		T189	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T48	11		T26	12		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16951	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T159	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T39	4		T29	2		T32	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	5		T40	3		T166	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T8	33		T28	12		T272	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T197	13		T176	12		T248	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T262	13		T203	8		T204	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T176	5		T249	7		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T26	13		T29	3		T230	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T10	13		T46	10		T154	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	8		T16	1		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	11		T10	19		T12	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T167	9		T51	4		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T230	9		T187	8		T171	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	6		T215	15		T238	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	7		T15	1		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	2		T44	12		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	2		T155	14		T240	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	14		T147	14		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	12		T40	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T269	7		T189	10		T161	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T48	12		T26	8		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T294	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T284	7		T290	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T228	1		T241	1		T271	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T39	7		T29	1		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T46	5		T137	3		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T1	2		T6	3		T8	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	1		T31	1		T228	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T42	1		T157	1		T293	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T140	12		T18	6		T266	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T137	12		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T46	11		T149	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	12		T43	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T38	5		T61	2		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T38	1		T16	2		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	14		T10	1		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T61	1		T15	12		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T27	10		T144	8		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	1		T151	15		T201	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T48	3		T40	1		T15	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	2		T9	7		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T9	11		T48	11		T40	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T284	7		T290	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T241	6		T271	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	4		T29	2		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T46	5		T40	3		T148	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T8	33		T28	12		T32	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T166	9		T197	13		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T157	11		T262	13		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T176	5		T249	7		T248	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	13		T29	3		T169	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	13		T46	10		T154	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	8		T230	12		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T29	9		T167	11		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T16	1		T167	9		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	11		T10	19		T12	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	6		T187	4		T215	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T193	7		T242	13		T295	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T44	12		T151	12		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	7		T40	2		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	16		T167	7		T147	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T9	12		T48	12		T40	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28