Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22420

1

T1

3

T2

165

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3668

1

T3

20

T9

18

T38

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19986

1

T1

2

T2

165

T3

22

auto[1]

6102

1

T1

1

T3

25

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	320	1			T10	14		T12	14		T40	3
values[0]	43	1			T238	21		T225	9		T100	12
values[1]	651	1			T48	23		T39	2		T27	10
values[2]	715	1			T3	20		T44	13		T137	12
values[3]	719	1			T9	23		T137	1		T15	5
values[4]	778	1			T10	20		T38	1		T43	1
values[5]	2953	1			T1	1		T6	3		T8	36
values[6]	883	1			T46	21		T15	8		T157	12
values[7]	597	1			T1	1		T3	25		T61	2
values[8]	675	1			T38	5		T40	3		T140	12
values[9]	805	1			T1	1		T3	2		T9	18
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	758	1			T44	13		T48	23		T39	2
values[1]	775	1			T3	20		T61	1		T15	5
values[2]	590	1			T9	23		T10	20		T43	1
values[3]	3175	1			T1	1		T6	3		T8	36
values[4]	668	1			T9	5		T141	1		T29	4
values[5]	705	1			T1	1		T46	21		T15	8
values[6]	765	1			T3	25		T38	5		T61	2
values[7]	553	1			T46	10		T40	3		T140	12
values[8]	795	1			T1	1		T3	2		T9	18
values[9]	210	1			T12	14		T40	3		T149	11
minimum	17094	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T44	13		T48	13		T39	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	1		T27	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T61	1		T15	2		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	9		T31	1		T32	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	13		T10	20		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T43	1		T137	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T1	1		T6	3		T8	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T38	1		T26	23		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	3		T141	1		T29	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	1		T158	11		T194	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T15	6		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T46	11		T157	12		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	12		T61	1		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	2		T16	4		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	6		T40	2		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T140	1		T31	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T3	1		T10	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	15		T48	8		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	8		T253	15		T90	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T40	2		T149	1		T152	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16868	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T168	1		T238	21		T263	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	10		T39	1		T175	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	1		T27	9		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	3		T42	7		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	11		T149	13		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	10		T137	11		T143	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T140	4		T42	4		T230	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T50	11		T137	2		T25	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T26	18		T16	1		T230	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	2		T17	1		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T158	13		T231	9		T88	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	2		T18	5		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	10		T144	5		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	13		T61	1		T15	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	3		T16	1		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T46	4		T40	1		T202	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	11		T187	11		T158	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	1		T40	5		T185	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	3		T48	2		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T12	6		T90	11		T305	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T40	1		T149	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T168	3		T225	8		T100	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	14		T12	8		T253	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T40	2		T149	1		T172	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T238	21		T225	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T48	13		T39	1		T29	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	1		T153	1		T51	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	13		T137	1		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	9		T15	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	13		T15	2		T42	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T137	1		T42	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	20		T137	1		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T38	1		T43	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T1	1		T6	3		T8	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	1		T167	12		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	6		T166	10		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T46	11		T157	12		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T3	12		T61	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T151	14		T17	1		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T40	2		T15	8		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T38	2		T140	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T3	1		T46	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	15		T48	8		T39	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T12	6		T90	11		T305	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T40	1		T149	10		T172	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T225	8		T100	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T48	10		T39	1		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T27	9		T51	4		T147	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T137	11		T156	6		T254	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	11		T15	1		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	10		T15	3		T42	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	4		T143	8		T187	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T137	2		T201	8		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T140	4		T26	18		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T9	2		T50	11		T25	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	14		T249	7		T88	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	2		T18	5		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T46	10		T144	5		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	13		T61	1		T156	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	4		T17	1		T155	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	1		T15	10		T202	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T38	3		T140	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	1		T46	4		T40	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	3		T48	2		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T44	1		T48	11		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	2		T27	10		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T61	1		T15	5		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	12		T31	1		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	11		T10	1		T137	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	1		T137	1		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T1	1		T6	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T38	1		T26	20		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	3		T141	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	1		T158	14		T194	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T15	7		T18	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T46	11		T157	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	14		T61	2		T15	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T38	5		T16	3		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	5		T40	2		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	12		T31	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T3	2		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	4		T48	3		T39	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	7		T253	1		T90	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T40	3		T149	11		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16993	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T168	4		T238	1		T263	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	12		T48	12		T29	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	4		T147	11		T189	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	9		T42	3		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	8		T32	2		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	12		T10	19		T172	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T230	9		T167	9		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T8	33		T40	2		T28	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T26	21		T16	1		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T29	3		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	10		T231	9		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T176	5		T238	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	10		T157	11		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	11		T15	6		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	2		T151	13		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	5		T40	1		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T187	11		T158	12		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	13		T40	3		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	14		T48	7		T39	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	7		T253	14		T90	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T152	13		T226	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T256	2		T226	21		T306	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T238	20		T263	9		T307	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T10	1		T12	7		T253	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T40	3		T149	11		T172	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T238	1		T225	9		T100	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	11		T39	2		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	10		T153	1		T51	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	1		T137	12		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	12		T15	2		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	11		T15	5		T42	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T137	1		T42	5		T143	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	1		T137	3		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T38	1		T43	1		T140	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T1	1		T6	3		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	1		T167	1		T155	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T15	7		T166	1		T18	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T46	11		T157	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	1		T3	14		T61	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T151	5		T17	2		T155	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T40	2		T15	12		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	5		T140	12		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T3	2		T46	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	4		T48	3		T39	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	13		T12	7		T253	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T172	6		T226	8		T251	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T238	20		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	12		T29	2		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T51	4		T147	11		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T44	12		T29	9		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	8		T32	2		T240	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	12		T42	3		T151	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T187	4		T262	12		T248	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	19		T40	2		T167	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T26	21		T16	1		T230	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T8	33		T9	2		T28	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T167	11		T155	10		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	1		T166	9		T198	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T46	10		T157	11		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	11		T238	4		T161	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T151	13		T155	12		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	1		T15	6		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T16	2		T187	11		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T46	5		T40	3		T240	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	14		T48	7		T39	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28