Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22553

1

T1

2

T2

165

T3

47

auto[ADC_CTRL_FILTER_COND_OUT]

3535

1

T1

1

T9

23

T10

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20225

1

T1

2

T2

165

T3

22

auto[1]

5863

1

T1

1

T3

25

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	163	1			T43	1		T61	1		T32	7
values[0]	17	1			T10	14		T286	3		-	-
values[1]	816	1			T44	13		T39	1		T137	1
values[2]	561	1			T3	25		T40	3		T15	2
values[3]	747	1			T3	20		T48	23		T39	11
values[4]	2932	1			T1	1		T6	3		T8	36
values[5]	708	1			T10	20		T140	5		T15	8
values[6]	770	1			T9	23		T12	14		T46	21
values[7]	748	1			T9	18		T38	1		T46	10
values[8]	659	1			T1	2		T9	5		T40	3
values[9]	1018	1			T3	2		T38	5		T137	12
minimum	16949	1			T2	165		T4	20		T5	103

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	677	1			T137	1		T15	18		T29	10
values[1]	589	1			T3	45		T40	3		T15	2
values[2]	686	1			T48	23		T39	11		T26	41
values[3]	3027	1			T1	1		T6	3		T8	36
values[4]	652	1			T10	20		T48	10		T140	5
values[5]	918	1			T9	41		T12	14		T46	31
values[6]	654	1			T1	1		T38	1		T137	3
values[7]	659	1			T1	1		T9	5		T38	5
values[8]	820	1			T3	2		T43	1		T137	12
values[9]	166	1			T145	1		T146	1		T308	1
minimum	17240	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	1		T41	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T137	1		T15	8		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	21		T27	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	2		T15	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	8		T26	14		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T48	13		T26	9		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T1	1		T6	3		T8	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	7		T149	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T140	1		T230	10		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	20		T48	8		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	15		T46	17		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	13		T12	8		T61	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T38	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T137	1		T228	1		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	3		T38	2		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T167	10		T187	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T43	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T137	1		T230	13		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T145	1		T146	1		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T188	1		T100	1		T296	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16929	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T10	14		T39	1		T198	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T155	14		T156	4		T243	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	10		T232	2		T257	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	24		T27	9		T42	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T40	1		T15	1		T154	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	3		T26	7		T182	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	10		T26	11		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T39	1		T50	11		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T40	5		T149	13		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T140	4		T230	7		T248	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	2		T15	2		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	3		T46	14		T151	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	10		T12	6		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T140	11		T147	12		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	2		T201	8		T193	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	2		T38	3		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T187	10		T255	3		T248	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T144	5		T193	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T137	11		T230	14		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T176	2		T262	14		T301	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T100	13		T299	10		T309	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	1		T15	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T242	7		T286	1		T310	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T43	1		T61	1		T32	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T311	1		T289	13		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T10	14		T286	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T44	13		T29	3		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T39	1		T137	1		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	12		T27	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	2		T15	1		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	9		T39	8		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	13		T31	1		T167	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	1		T6	3		T8	36
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	7		T26	9		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	1		T230	10		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	20		T15	6		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T46	11		T141	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	13		T12	8		T48	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	15		T38	1		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T137	1		T61	1		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T9	3		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T228	1		T167	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T38	2		T157	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T137	1		T230	13		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16824	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T262	14		T250	11		T83	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T100	13		T312	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T286	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	1		T42	7		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	10		T154	13		T242	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	13		T27	9		T42	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T40	1		T15	1		T143	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	11		T39	3		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T48	10		T147	12		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T39	1		T50	11		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	5		T26	11		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T140	4		T230	7		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	2		T16	1		T232	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T46	10		T17	1		T182	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	10		T12	6		T48	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	3		T46	4		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	2		T61	1		T201	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	2		T40	1		T149	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T248	20		T244	4		T170	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T38	3		T144	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T137	11		T230	14		T143	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T31	1		T41	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	1		T15	12		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	26		T27	10		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T40	3		T15	2		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	7		T26	8		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	11		T26	12		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T1	1		T6	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	9		T149	14		T143	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T140	5		T230	8		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	1		T48	3		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	4		T46	16		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	11		T12	7		T61	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	1		T38	1		T140	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T137	3		T228	1		T201	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	3		T38	5		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T167	1		T187	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	2		T43	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T137	12		T230	15		T143	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T145	1		T146	1		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T188	1		T100	14		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17007	1			T2	165		T4	20		T5	103
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T10	1		T39	1		T198	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T155	10		T156	4		T239	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	6		T29	9		T148	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	19		T167	11		T148	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T167	7		T154	14		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	4		T26	13		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	12		T26	8		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T8	33		T28	12		T272	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	3		T158	12		T197	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T230	9		T152	13		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	19		T48	7		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	14		T46	15		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	12		T12	7		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T147	9		T269	7		T240	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T193	7		T158	10		T241	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T40	1		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T167	9		T187	12		T241	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T32	2		T157	11		T193	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T230	12		T147	11		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T176	5		T262	22		T313	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T296	10		T299	9		T283	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T44	12		T29	2		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T10	13		T198	15		T242	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T43	1		T61	1		T32	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T311	1		T289	1		T100	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T10	1		T286	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	1		T29	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	1		T137	1		T15	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	14		T27	10		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	3		T15	2		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	12		T39	7		T26	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	11		T31	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	1		T6	3		T8	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T40	9		T26	12		T149	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T140	5		T230	8		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T15	7		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T46	11		T141	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	11		T12	7		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	4		T38	1		T46	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T137	3		T61	2		T201	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T9	3		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T228	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	2		T38	5		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T137	12		T230	15		T143	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T2	165		T4	20		T5	103
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T32	2		T262	22		T298	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T289	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T10	13		T286	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T44	12		T29	2		T16	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	6		T29	9		T154	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	11		T148	2		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T155	12		T289	13		T314	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	8		T39	4		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T48	12		T167	7		T147	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T8	33		T28	12		T272	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	3		T26	8		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T230	9		T151	12		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	19		T15	1		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	10		T17	1		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	12		T12	7		T48	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	14		T46	5		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T156	6		T193	7		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	2		T40	1		T187	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T167	9		T248	31		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T157	11		T142	1		T193	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T230	12		T147	11		T187	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28