Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26088

1

T1

3

T2

165

T3

47

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22768

1

T1

1

T2

165

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3320

1

T1

2

T3

2

T9

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19487

1

T1

3

T2

163

T4

20

auto[1]

6601

1

T2

2

T3

47

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22120

1

T1

3

T2

165

T3

22

auto[1]

3968

1

T3

25

T9

15

T12

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	538	1			T2	2		T5	1		T7	4
values[0]	74	1			T42	5		T243	9		T314	20
values[1]	575	1			T61	1		T16	5		T148	12
values[2]	2926	1			T1	1		T6	3		T8	36
values[3]	632	1			T141	1		T15	18		T41	1
values[4]	749	1			T46	21		T39	3		T27	10
values[5]	728	1			T3	25		T9	18		T44	13
values[6]	774	1			T1	1		T3	20		T9	23
values[7]	656	1			T1	1		T3	2		T12	14
values[8]	522	1			T10	14		T39	11		T137	1
values[9]	1421	1			T10	20		T43	1		T46	10
minimum	16493	1			T2	163		T4	20		T5	102

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T9	5		T61	1		T26	21
values[1]	2934	1			T1	1		T6	3		T8	36
values[2]	571	1			T141	1		T15	18		T27	10
values[3]	821	1			T46	21		T39	3		T31	1
values[4]	666	1			T1	1		T3	45		T9	18
values[5]	863	1			T1	1		T9	23		T38	6
values[6]	497	1			T3	2		T12	14		T61	2
values[7]	645	1			T39	11		T137	1		T140	17
values[8]	1122	1			T10	34		T43	1		T48	10
values[9]	164	1			T46	10		T48	23		T142	7
minimum	16974	1			T2	165		T4	20		T5	103

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

4234

1

T3

19

T8

33

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T61	1		T26	14		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	3		T16	4		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T6	3		T8	36		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T15	1		T182	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T141	1		T15	8		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	1		T187	5		T308	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T31	1		T229	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T46	11		T39	2		T42	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T3	21		T40	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	15		T44	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T9	13		T38	3		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T40	2		T151	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T61	1		T32	7		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	1		T12	8		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	1		T140	2		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	8		T151	14		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T10	34		T48	8		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T43	1		T26	9		T29	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T46	6		T48	13		T18	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T142	7		T315	1		T188	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16837	1			T2	165		T4	20		T5	103
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T26	7		T144	7		T155	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	2		T16	1		T42	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T50	11		T25	7		T33	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	1		T182	24		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	10		T27	9		T201	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T187	4		T232	2		T262	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	1		T144	5		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T46	10		T39	1		T42	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	24		T40	5		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	3		T137	11		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	10		T38	3		T137	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	1		T151	16		T264	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T61	1		T17	1		T266	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T3	1		T12	6		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T140	15		T143	8		T202	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T39	3		T151	4		T154	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	2		T15	3		T193	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T26	11		T149	13		T230	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T46	4		T48	10		T18	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T168	3		T83	1		T316	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T40	1		T15	2		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	476	1			T2	2		T5	1		T7	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T242	8		T257	1		T161	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T251	16		T317	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T42	1		T243	6		T314	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T61	1		T155	11		T238	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	4		T148	12		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T6	3		T8	36		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T9	3		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T141	1		T15	8		T230	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T41	1		T182	1		T187	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	1		T31	1		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T46	11		T39	2		T42	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	12		T40	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	15		T44	13		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T3	9		T9	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T151	13		T228	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T38	1		T61	1		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T3	1		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	14		T137	1		T140	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T39	8		T154	15		T198	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T10	20		T46	6		T48	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	404	1			T43	1		T26	9		T29	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16368	1			T2	163		T4	20		T5	102
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T88	1		T317	20		T318	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T242	7		T319	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T251	21		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T42	4		T243	3		T314	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T155	14		T231	34		T36	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	1		T182	16		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T50	11		T25	7		T26	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	2		T15	1		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	10		T230	7		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T182	8		T187	4		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T27	9		T249	2		T305	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T46	10		T39	1		T42	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	13		T40	5		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	3		T137	11		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	11		T9	10		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T151	14		T264	10		T242	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T61	1		T16	1		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	1		T12	6		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T140	15		T202	2		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	3		T154	13		T257	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T46	4		T48	12		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T26	11		T149	13		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	1		T15	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T61	1		T26	8		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	3		T16	3		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T6	3		T8	3		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	1		T15	2		T182	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	1		T15	12		T27	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	1		T187	5		T308	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	1		T229	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T46	11		T39	3		T42	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T3	26		T40	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	4		T44	1		T137	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	11		T38	6		T137	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	1		T40	3		T151	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T61	2		T32	5		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	2		T12	7		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T137	1		T140	17		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	7		T151	5		T154	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	2		T48	3		T15	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T43	1		T26	12		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T46	5		T48	11		T18	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T142	6		T315	1		T188	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16962	1			T2	165		T4	20		T5	103
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T26	13		T155	10		T238	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	2		T16	2		T148	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T8	33		T28	12		T272	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T158	10		T263	9		T320	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	6		T158	12		T176	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T187	4		T241	6		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T166	2		T90	12		T289	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T46	10		T42	3		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	19		T40	3		T166	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	14		T44	12		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	12		T40	1		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T151	16		T242	13		T169	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T32	2		T17	1		T240	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	7		T40	2		T187	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T152	13		T241	8		T248	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T39	4		T151	13		T154	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	32		T48	7		T29	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T26	8		T29	2		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T46	5		T48	12		T179	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T142	1		T320	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	486	1			T2	2		T5	1		T7	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T242	8		T257	1		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T251	22		T317	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T42	5		T243	4		T314	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T61	1		T155	15		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	3		T148	1		T182	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T6	3		T8	3		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T9	3		T15	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T141	1		T15	12		T230	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T41	1		T182	9		T187	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T27	10		T31	1		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	11		T39	3		T42	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	14		T40	9		T149	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	4		T44	1		T137	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T3	12		T9	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T151	15		T228	1		T264	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T38	1		T61	2		T32	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T3	2		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	1		T137	1		T140	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	7		T154	14		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T10	1		T46	5		T48	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T43	1		T26	12		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T2	163		T4	20		T5	102
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T317	12		T318	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T242	7		T161	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T251	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T243	5		T314	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T155	10		T238	4		T231	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	2		T148	11		T269	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T8	33		T26	13		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	2		T263	9		T321	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	6		T230	9		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T187	4		T158	10		T241	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T166	2		T249	11		T204	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	10		T42	3		T240	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	11		T40	3		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	14		T44	12		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	8		T9	12		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T151	12		T242	13		T240	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	2		T16	1		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	7		T40	2		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	13		T249	7		T322	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T39	4		T154	14		T198	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T10	19		T46	5		T48	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T26	8		T29	2		T230	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21854

1

T1

3

T2

165

T3

28

auto[1]

auto[0]

4234

1

T3

19

T8

33

T9

28