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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.54


Total test records in report: 918
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T794 /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4242385071 Jul 16 07:16:51 PM PDT 24 Jul 16 07:29:22 PM PDT 24 401668650062 ps
T795 /workspace/coverage/default/48.adc_ctrl_stress_all.795936927 Jul 16 07:21:29 PM PDT 24 Jul 16 07:48:14 PM PDT 24 679005949863 ps
T796 /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3610219738 Jul 16 07:21:14 PM PDT 24 Jul 16 07:30:01 PM PDT 24 341791971998 ps
T58 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2733855113 Jul 16 07:11:31 PM PDT 24 Jul 16 07:13:00 PM PDT 24 3839200948 ps
T59 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3082893878 Jul 16 07:11:33 PM PDT 24 Jul 16 07:13:04 PM PDT 24 5606223727 ps
T797 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.66772975 Jul 16 07:11:48 PM PDT 24 Jul 16 07:13:13 PM PDT 24 381471000 ps
T65 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3451261976 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:09 PM PDT 24 435122604 ps
T94 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4032115969 Jul 16 07:11:22 PM PDT 24 Jul 16 07:12:36 PM PDT 24 465341837 ps
T798 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4010407828 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:10 PM PDT 24 306057750 ps
T66 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3474892685 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:08 PM PDT 24 480672189 ps
T799 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2717478133 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:10 PM PDT 24 519902213 ps
T62 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2957593351 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:16 PM PDT 24 8976765058 ps
T63 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1777087604 Jul 16 07:11:42 PM PDT 24 Jul 16 07:13:27 PM PDT 24 4266168282 ps
T128 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4117811680 Jul 16 07:11:21 PM PDT 24 Jul 16 07:12:35 PM PDT 24 538173098 ps
T116 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3036945737 Jul 16 07:11:21 PM PDT 24 Jul 16 07:12:36 PM PDT 24 600567250 ps
T71 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.414768283 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:59 PM PDT 24 414048053 ps
T800 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.302519928 Jul 16 07:11:21 PM PDT 24 Jul 16 07:12:35 PM PDT 24 319433746 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4146281562 Jul 16 07:11:16 PM PDT 24 Jul 16 07:12:16 PM PDT 24 689593585 ps
T801 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3106549973 Jul 16 07:11:51 PM PDT 24 Jul 16 07:13:21 PM PDT 24 353366881 ps
T802 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2483486740 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:10 PM PDT 24 477632561 ps
T803 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2848257516 Jul 16 07:11:39 PM PDT 24 Jul 16 07:13:07 PM PDT 24 315638588 ps
T60 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2149805199 Jul 16 07:11:23 PM PDT 24 Jul 16 07:12:57 PM PDT 24 13844040642 ps
T804 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1645833789 Jul 16 07:11:38 PM PDT 24 Jul 16 07:13:07 PM PDT 24 448202381 ps
T74 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3493708617 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:58 PM PDT 24 758235064 ps
T805 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4124249015 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:08 PM PDT 24 494694343 ps
T64 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2539058526 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:18 PM PDT 24 4296305174 ps
T806 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1976925677 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:59 PM PDT 24 327563632 ps
T95 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.707670870 Jul 16 07:11:21 PM PDT 24 Jul 16 07:12:35 PM PDT 24 595866818 ps
T135 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.478966006 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:35 PM PDT 24 26822469821 ps
T67 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3846723733 Jul 16 07:11:22 PM PDT 24 Jul 16 07:12:37 PM PDT 24 5754810688 ps
T807 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4126178854 Jul 16 07:11:51 PM PDT 24 Jul 16 07:13:18 PM PDT 24 291482313 ps
T808 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.242208639 Jul 16 07:11:40 PM PDT 24 Jul 16 07:13:09 PM PDT 24 369190672 ps
T96 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.21085553 Jul 16 07:11:23 PM PDT 24 Jul 16 07:12:49 PM PDT 24 4521230868 ps
T105 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.169965188 Jul 16 07:11:29 PM PDT 24 Jul 16 07:12:59 PM PDT 24 436296816 ps
T72 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1810017625 Jul 16 07:11:28 PM PDT 24 Jul 16 07:13:01 PM PDT 24 608137829 ps
T809 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1390746084 Jul 16 07:11:45 PM PDT 24 Jul 16 07:13:11 PM PDT 24 377432238 ps
T106 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1851113529 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:21 PM PDT 24 8853297964 ps
T810 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1180211165 Jul 16 07:11:48 PM PDT 24 Jul 16 07:13:19 PM PDT 24 465266730 ps
T73 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1424496800 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:49 PM PDT 24 8682373484 ps
T77 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2596113307 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:16 PM PDT 24 8438110412 ps
T129 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4003700490 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:59 PM PDT 24 354751134 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2594127231 Jul 16 07:11:32 PM PDT 24 Jul 16 07:12:59 PM PDT 24 324105756 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3615417469 Jul 16 07:11:32 PM PDT 24 Jul 16 07:12:59 PM PDT 24 539275612 ps
T813 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.302646867 Jul 16 07:11:34 PM PDT 24 Jul 16 07:13:02 PM PDT 24 368489952 ps
T814 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3658513727 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:59 PM PDT 24 341698776 ps
T815 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.416075441 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:28 PM PDT 24 823458343 ps
T816 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2879398481 Jul 16 07:11:50 PM PDT 24 Jul 16 07:13:14 PM PDT 24 530506575 ps
T817 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2452125557 Jul 16 07:11:36 PM PDT 24 Jul 16 07:13:07 PM PDT 24 559639301 ps
T818 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.743504704 Jul 16 07:11:34 PM PDT 24 Jul 16 07:13:03 PM PDT 24 450513823 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4238370042 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:17 PM PDT 24 1470656520 ps
T78 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1420599900 Jul 16 07:11:13 PM PDT 24 Jul 16 07:12:02 PM PDT 24 645014640 ps
T819 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.185783211 Jul 16 07:11:39 PM PDT 24 Jul 16 07:13:05 PM PDT 24 435879114 ps
T820 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2189090894 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:07 PM PDT 24 373176405 ps
T130 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3495668296 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:58 PM PDT 24 353569885 ps
T119 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1206773483 Jul 16 07:11:28 PM PDT 24 Jul 16 07:13:07 PM PDT 24 10973250826 ps
T821 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.962327983 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:59 PM PDT 24 468047626 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3186204083 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:20 PM PDT 24 4539810240 ps
T132 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2052729941 Jul 16 07:11:27 PM PDT 24 Jul 16 07:12:54 PM PDT 24 4746296942 ps
T120 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1477244726 Jul 16 07:11:20 PM PDT 24 Jul 16 07:13:51 PM PDT 24 37486118404 ps
T822 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.304905449 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:01 PM PDT 24 4299255771 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3465262236 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:21 PM PDT 24 4864061900 ps
T79 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.235742375 Jul 16 07:11:31 PM PDT 24 Jul 16 07:13:00 PM PDT 24 849522259 ps
T824 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1589208255 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:34 PM PDT 24 375119328 ps
T825 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3922895787 Jul 16 07:11:29 PM PDT 24 Jul 16 07:12:58 PM PDT 24 594262108 ps
T826 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.599186264 Jul 16 07:11:38 PM PDT 24 Jul 16 07:13:08 PM PDT 24 382738795 ps
T827 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1815727148 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:28 PM PDT 24 379010923 ps
T828 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1420853743 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:29 PM PDT 24 475252379 ps
T133 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2687419390 Jul 16 07:11:40 PM PDT 24 Jul 16 07:13:26 PM PDT 24 5146663294 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.343298790 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:56 PM PDT 24 377186100 ps
T830 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2324962463 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:10 PM PDT 24 418474547 ps
T831 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2230061202 Jul 16 07:11:33 PM PDT 24 Jul 16 07:13:02 PM PDT 24 470916236 ps
T832 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.66399834 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:00 PM PDT 24 579086497 ps
T134 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1848610901 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:11 PM PDT 24 3005694658 ps
T121 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3803668209 Jul 16 07:11:29 PM PDT 24 Jul 16 07:12:57 PM PDT 24 471892130 ps
T833 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.804881837 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:27 PM PDT 24 793825895 ps
T834 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3314688927 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:07 PM PDT 24 8442441502 ps
T122 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3714105991 Jul 16 07:11:29 PM PDT 24 Jul 16 07:12:58 PM PDT 24 377405525 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.747972738 Jul 16 07:11:32 PM PDT 24 Jul 16 07:13:00 PM PDT 24 579871816 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1357340491 Jul 16 07:11:25 PM PDT 24 Jul 16 07:12:51 PM PDT 24 1152653068 ps
T837 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.285447760 Jul 16 07:11:49 PM PDT 24 Jul 16 07:13:13 PM PDT 24 428136753 ps
T838 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2596061784 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:59 PM PDT 24 816467433 ps
T839 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3105120844 Jul 16 07:11:45 PM PDT 24 Jul 16 07:13:12 PM PDT 24 573356656 ps
T840 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2315634231 Jul 16 07:11:42 PM PDT 24 Jul 16 07:13:24 PM PDT 24 4625447463 ps
T841 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.502746077 Jul 16 07:11:42 PM PDT 24 Jul 16 07:13:22 PM PDT 24 339545421 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1847572137 Jul 16 07:11:36 PM PDT 24 Jul 16 07:13:06 PM PDT 24 288308717 ps
T843 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.647267669 Jul 16 07:11:32 PM PDT 24 Jul 16 07:12:59 PM PDT 24 424659293 ps
T844 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1948042983 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:20 PM PDT 24 4305793730 ps
T123 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3347014193 Jul 16 07:11:32 PM PDT 24 Jul 16 07:12:59 PM PDT 24 557979090 ps
T845 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2339230204 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:07 PM PDT 24 457156415 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.898155887 Jul 16 07:11:16 PM PDT 24 Jul 16 07:12:18 PM PDT 24 470817890 ps
T847 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1424266566 Jul 16 07:11:53 PM PDT 24 Jul 16 07:13:17 PM PDT 24 324521147 ps
T848 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3914978182 Jul 16 07:11:33 PM PDT 24 Jul 16 07:13:03 PM PDT 24 384571503 ps
T849 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.200570567 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:29 PM PDT 24 644732546 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2239751867 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:24 PM PDT 24 2468163363 ps
T851 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1690056999 Jul 16 07:11:31 PM PDT 24 Jul 16 07:13:02 PM PDT 24 4423296771 ps
T852 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2561610408 Jul 16 07:11:29 PM PDT 24 Jul 16 07:13:04 PM PDT 24 4913877499 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.474944987 Jul 16 07:11:18 PM PDT 24 Jul 16 07:12:20 PM PDT 24 1365712809 ps
T125 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2494071228 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:11 PM PDT 24 538904458 ps
T853 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1714526092 Jul 16 07:11:32 PM PDT 24 Jul 16 07:13:00 PM PDT 24 2196996248 ps
T854 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2431854282 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:07 PM PDT 24 4890768458 ps
T855 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2734780435 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:04 PM PDT 24 4481648174 ps
T856 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1616060744 Jul 16 07:11:34 PM PDT 24 Jul 16 07:13:03 PM PDT 24 520722241 ps
T857 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2523725529 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:15 PM PDT 24 4068148684 ps
T126 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2116184671 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:29 PM PDT 24 953761984 ps
T858 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.454178054 Jul 16 07:11:29 PM PDT 24 Jul 16 07:12:59 PM PDT 24 328730872 ps
T127 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3716135649 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:07 PM PDT 24 346960382 ps
T859 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4249421398 Jul 16 07:11:38 PM PDT 24 Jul 16 07:13:10 PM PDT 24 505588854 ps
T346 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3275287300 Jul 16 07:11:33 PM PDT 24 Jul 16 07:13:05 PM PDT 24 4296113236 ps
T860 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2342685930 Jul 16 07:11:34 PM PDT 24 Jul 16 07:13:04 PM PDT 24 747037389 ps
T861 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.265688618 Jul 16 07:11:22 PM PDT 24 Jul 16 07:12:38 PM PDT 24 757260147 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.822150513 Jul 16 07:11:23 PM PDT 24 Jul 16 07:12:50 PM PDT 24 1015977199 ps
T863 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2593441162 Jul 16 07:11:29 PM PDT 24 Jul 16 07:13:08 PM PDT 24 2837125990 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3035628630 Jul 16 07:11:40 PM PDT 24 Jul 16 07:13:09 PM PDT 24 725680519 ps
T865 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.536277645 Jul 16 07:11:42 PM PDT 24 Jul 16 07:13:18 PM PDT 24 308167650 ps
T866 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.587353821 Jul 16 07:11:23 PM PDT 24 Jul 16 07:12:42 PM PDT 24 4833263113 ps
T867 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3775003723 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:30 PM PDT 24 621747766 ps
T868 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2812723649 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:04 PM PDT 24 4629705977 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1094450198 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:58 PM PDT 24 491760453 ps
T870 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3838199725 Jul 16 07:11:40 PM PDT 24 Jul 16 07:13:11 PM PDT 24 468979144 ps
T871 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3513479472 Jul 16 07:11:46 PM PDT 24 Jul 16 07:13:18 PM PDT 24 329738470 ps
T872 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1499100626 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:18 PM PDT 24 4511185060 ps
T873 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3599025225 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:59 PM PDT 24 582229633 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2872949715 Jul 16 07:11:28 PM PDT 24 Jul 16 07:13:01 PM PDT 24 4393088053 ps
T875 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.38435642 Jul 16 07:11:36 PM PDT 24 Jul 16 07:13:07 PM PDT 24 580903467 ps
T876 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.113956362 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:09 PM PDT 24 482379454 ps
T877 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2078003930 Jul 16 07:11:39 PM PDT 24 Jul 16 07:13:10 PM PDT 24 521509815 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2209292137 Jul 16 07:11:18 PM PDT 24 Jul 16 07:12:20 PM PDT 24 844173990 ps
T879 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.868080638 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:18 PM PDT 24 513343184 ps
T880 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1517999873 Jul 16 07:11:36 PM PDT 24 Jul 16 07:13:07 PM PDT 24 513029726 ps
T881 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.699179833 Jul 16 07:11:22 PM PDT 24 Jul 16 07:12:36 PM PDT 24 397688939 ps
T882 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2489349834 Jul 16 07:11:50 PM PDT 24 Jul 16 07:13:13 PM PDT 24 339444806 ps
T80 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.844871791 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:33 PM PDT 24 4667878556 ps
T883 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1645948813 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:24 PM PDT 24 474850793 ps
T884 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.277225131 Jul 16 07:11:44 PM PDT 24 Jul 16 07:13:12 PM PDT 24 381759521 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3677792915 Jul 16 07:11:22 PM PDT 24 Jul 16 07:12:37 PM PDT 24 396604160 ps
T886 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1512094898 Jul 16 07:11:38 PM PDT 24 Jul 16 07:13:07 PM PDT 24 367636059 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.372404141 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:30 PM PDT 24 2291983143 ps
T888 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3724128493 Jul 16 07:11:30 PM PDT 24 Jul 16 07:13:16 PM PDT 24 4550546106 ps
T889 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3945677170 Jul 16 07:11:38 PM PDT 24 Jul 16 07:13:08 PM PDT 24 288587389 ps
T890 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1725970160 Jul 16 07:11:28 PM PDT 24 Jul 16 07:13:03 PM PDT 24 2391521800 ps
T891 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.157074981 Jul 16 07:11:36 PM PDT 24 Jul 16 07:13:18 PM PDT 24 8488595563 ps
T892 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2664875780 Jul 16 07:11:32 PM PDT 24 Jul 16 07:13:00 PM PDT 24 717947710 ps
T893 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.261830267 Jul 16 07:11:39 PM PDT 24 Jul 16 07:13:09 PM PDT 24 313639343 ps
T894 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3894910327 Jul 16 07:11:39 PM PDT 24 Jul 16 07:13:07 PM PDT 24 415386996 ps
T895 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3391610051 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:59 PM PDT 24 400330858 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1126483052 Jul 16 07:11:21 PM PDT 24 Jul 16 07:12:38 PM PDT 24 2331773304 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.809479274 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:29 PM PDT 24 3699023528 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1288789367 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:18 PM PDT 24 500648434 ps
T899 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1598580116 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:28 PM PDT 24 691679758 ps
T900 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1059653291 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:14 PM PDT 24 4792489476 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2840038212 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:59 PM PDT 24 370705898 ps
T902 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4088275679 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:59 PM PDT 24 415712115 ps
T903 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2051681452 Jul 16 07:11:30 PM PDT 24 Jul 16 07:12:59 PM PDT 24 610259535 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3501520234 Jul 16 07:11:31 PM PDT 24 Jul 16 07:13:01 PM PDT 24 365838733 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1129232793 Jul 16 07:11:22 PM PDT 24 Jul 16 07:12:36 PM PDT 24 667655756 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3412455074 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:11 PM PDT 24 521872442 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2279948843 Jul 16 07:11:18 PM PDT 24 Jul 16 07:12:19 PM PDT 24 347534741 ps
T908 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1705213456 Jul 16 07:11:36 PM PDT 24 Jul 16 07:13:05 PM PDT 24 417916481 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2073240988 Jul 16 07:11:34 PM PDT 24 Jul 16 07:13:04 PM PDT 24 487719945 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2217077271 Jul 16 07:11:20 PM PDT 24 Jul 16 07:12:28 PM PDT 24 537465015 ps
T911 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1935420756 Jul 16 07:11:41 PM PDT 24 Jul 16 07:13:19 PM PDT 24 458664005 ps
T912 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2947412702 Jul 16 07:11:37 PM PDT 24 Jul 16 07:13:07 PM PDT 24 544083381 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1986261601 Jul 16 07:11:21 PM PDT 24 Jul 16 07:12:35 PM PDT 24 347768173 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4073428963 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:30 PM PDT 24 748081262 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2624546352 Jul 16 07:11:24 PM PDT 24 Jul 16 07:16:07 PM PDT 24 39450881952 ps
T916 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1161879631 Jul 16 07:11:28 PM PDT 24 Jul 16 07:12:59 PM PDT 24 500203226 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3165885009 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:19 PM PDT 24 689945995 ps
T918 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2102134088 Jul 16 07:11:31 PM PDT 24 Jul 16 07:12:59 PM PDT 24 405453589 ps

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3706593107
Short name T3
Test name
Test status
Simulation time 507721258572 ps
CPU time 221.89 seconds
Started Jul 16 07:21:16 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 201936 kb
Host smart-ce0b6d5b-e913-485a-bea8-44b6ea935de1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706593107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3706593107
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4243735705
Short name T2
Test name
Test status
Simulation time 115661156773 ps
CPU time 564.3 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:28:16 PM PDT 24
Peak memory 202304 kb
Host smart-e5903ba0-5cdf-45c5-9e47-681887d69ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243735705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4243735705
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3726982828
Short name T15
Test name
Test status
Simulation time 967264571556 ps
CPU time 136.85 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:19:35 PM PDT 24
Peak memory 210144 kb
Host smart-e4d94f05-956b-46a2-9a7a-95ca4b5a859e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726982828 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3726982828
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.83511222
Short name T9
Test name
Test status
Simulation time 675381092283 ps
CPU time 346.77 seconds
Started Jul 16 07:21:29 PM PDT 24
Finished Jul 16 07:27:22 PM PDT 24
Peak memory 201900 kb
Host smart-3e37df98-d9fa-4192-8bff-55df4df73024
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83511222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gatin
g.83511222
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3487786869
Short name T39
Test name
Test status
Simulation time 288898245499 ps
CPU time 208.42 seconds
Started Jul 16 07:17:56 PM PDT 24
Finished Jul 16 07:21:41 PM PDT 24
Peak memory 211428 kb
Host smart-c43555a0-aa17-4589-b9a6-3545cfb683a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487786869 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3487786869
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3197917736
Short name T26
Test name
Test status
Simulation time 366870908362 ps
CPU time 212.19 seconds
Started Jul 16 07:17:49 PM PDT 24
Finished Jul 16 07:21:24 PM PDT 24
Peak memory 201900 kb
Host smart-13ec88b6-7200-4c1b-b6a5-ada94ef08c4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197917736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3197917736
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3199091350
Short name T40
Test name
Test status
Simulation time 438080921593 ps
CPU time 463.86 seconds
Started Jul 16 07:16:49 PM PDT 24
Finished Jul 16 07:24:55 PM PDT 24
Peak memory 211632 kb
Host smart-198ba515-1a45-4b09-8869-79edbb9e7a8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199091350 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3199091350
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1837819587
Short name T92
Test name
Test status
Simulation time 258331737709 ps
CPU time 567.65 seconds
Started Jul 16 07:19:04 PM PDT 24
Finished Jul 16 07:29:27 PM PDT 24
Peak memory 211488 kb
Host smart-99699f90-e823-4511-955b-74706c4a28d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837819587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1837819587
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.38976605
Short name T248
Test name
Test status
Simulation time 546254633328 ps
CPU time 1213.3 seconds
Started Jul 16 07:18:03 PM PDT 24
Finished Jul 16 07:38:45 PM PDT 24
Peak memory 201912 kb
Host smart-a58aec76-0a83-468e-8b58-7a298032379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38976605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.38976605
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.162289195
Short name T147
Test name
Test status
Simulation time 499899798508 ps
CPU time 476.82 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 201908 kb
Host smart-4bae26a7-4859-4087-9a65-244f3f6c34fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162289195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.162289195
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4122871480
Short name T155
Test name
Test status
Simulation time 495901693867 ps
CPU time 265.34 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:25:58 PM PDT 24
Peak memory 201892 kb
Host smart-2284128e-b119-48ef-a8c5-5abfcb39630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122871480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4122871480
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.372515765
Short name T48
Test name
Test status
Simulation time 332275815794 ps
CPU time 368.97 seconds
Started Jul 16 07:17:58 PM PDT 24
Finished Jul 16 07:24:29 PM PDT 24
Peak memory 201868 kb
Host smart-a86dad6d-0578-40e3-8ccf-d5697c66c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372515765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.372515765
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2957593351
Short name T62
Test name
Test status
Simulation time 8976765058 ps
CPU time 6.8 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:16 PM PDT 24
Peak memory 201872 kb
Host smart-2c0c2c8c-bfb7-4840-bccb-ee87d3d406be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957593351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2957593351
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.879843334
Short name T29
Test name
Test status
Simulation time 584497226377 ps
CPU time 1379.04 seconds
Started Jul 16 07:21:14 PM PDT 24
Finished Jul 16 07:44:23 PM PDT 24
Peak memory 201856 kb
Host smart-21c3d3f6-02d7-46e7-9a7f-c71a2c4109d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879843334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.879843334
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3206279045
Short name T76
Test name
Test status
Simulation time 404532573 ps
CPU time 0.81 seconds
Started Jul 16 07:17:46 PM PDT 24
Finished Jul 16 07:17:48 PM PDT 24
Peak memory 201680 kb
Host smart-1875269a-8389-49b2-9e84-3fc7eac12599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206279045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3206279045
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2786759586
Short name T262
Test name
Test status
Simulation time 542890701038 ps
CPU time 310.47 seconds
Started Jul 16 07:16:33 PM PDT 24
Finished Jul 16 07:22:17 PM PDT 24
Peak memory 201928 kb
Host smart-a4012c21-6d3f-4c95-996d-9cfdd66feeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786759586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2786759586
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2149805199
Short name T60
Test name
Test status
Simulation time 13844040642 ps
CPU time 20.3 seconds
Started Jul 16 07:11:23 PM PDT 24
Finished Jul 16 07:12:57 PM PDT 24
Peak memory 201752 kb
Host smart-7ecc15c6-8f9d-4d1d-a977-3ab9a66bef83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149805199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2149805199
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2212691335
Short name T249
Test name
Test status
Simulation time 531372348473 ps
CPU time 301.86 seconds
Started Jul 16 07:19:05 PM PDT 24
Finished Jul 16 07:25:02 PM PDT 24
Peak memory 201940 kb
Host smart-e0f9f058-bd94-422d-8f29-3be15985c89d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212691335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2212691335
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.514906890
Short name T253
Test name
Test status
Simulation time 556883880277 ps
CPU time 1256.25 seconds
Started Jul 16 07:18:27 PM PDT 24
Finished Jul 16 07:40:03 PM PDT 24
Peak memory 201960 kb
Host smart-7d67e5d2-d176-4f11-9d92-373f1e4a9e6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514906890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.514906890
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1278287421
Short name T241
Test name
Test status
Simulation time 559440564556 ps
CPU time 1248.51 seconds
Started Jul 16 07:16:28 PM PDT 24
Finished Jul 16 07:37:55 PM PDT 24
Peak memory 201832 kb
Host smart-77fbd675-507f-4d65-9f28-8224e9c844c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278287421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1278287421
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3643851404
Short name T187
Test name
Test status
Simulation time 484299935467 ps
CPU time 905.69 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:32:10 PM PDT 24
Peak memory 201960 kb
Host smart-c260950e-99d9-40f5-88fa-5c3839c37632
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643851404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3643851404
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.235742375
Short name T79
Test name
Test status
Simulation time 849522259 ps
CPU time 2.47 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:13:00 PM PDT 24
Peak memory 210880 kb
Host smart-0c435592-4071-48c5-9eaf-44540254174b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235742375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.235742375
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.603168449
Short name T144
Test name
Test status
Simulation time 478208325988 ps
CPU time 280.36 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:21:44 PM PDT 24
Peak memory 201892 kb
Host smart-4af1c023-e0ab-429e-96be-7f580e3b801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603168449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.603168449
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1521884129
Short name T189
Test name
Test status
Simulation time 337958432177 ps
CPU time 191.19 seconds
Started Jul 16 07:17:11 PM PDT 24
Finished Jul 16 07:20:30 PM PDT 24
Peak memory 201900 kb
Host smart-52a53841-33ad-4d26-8afe-429f2bd0597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521884129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1521884129
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1010335390
Short name T151
Test name
Test status
Simulation time 531973779404 ps
CPU time 579.33 seconds
Started Jul 16 07:19:19 PM PDT 24
Finished Jul 16 07:29:58 PM PDT 24
Peak memory 201844 kb
Host smart-174ad16c-bfed-4cce-b622-d0a3242fbd0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010335390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1010335390
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1527547997
Short name T286
Test name
Test status
Simulation time 370371259662 ps
CPU time 352.84 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:24:40 PM PDT 24
Peak memory 210488 kb
Host smart-4091fabf-5ed5-44eb-89b9-b59d2a105764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527547997 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1527547997
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.194159735
Short name T8
Test name
Test status
Simulation time 601542606826 ps
CPU time 316.3 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:22:22 PM PDT 24
Peak memory 201912 kb
Host smart-e34b2f19-1cd1-4b62-80a4-1ef03aa46529
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194159735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.194159735
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1225126338
Short name T314
Test name
Test status
Simulation time 493408740430 ps
CPU time 1016.62 seconds
Started Jul 16 07:17:12 PM PDT 24
Finished Jul 16 07:34:16 PM PDT 24
Peak memory 201880 kb
Host smart-9850df63-d806-484a-b811-dceaf0c1034d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225126338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1225126338
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2820247331
Short name T168
Test name
Test status
Simulation time 496497375034 ps
CPU time 304.23 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:23:10 PM PDT 24
Peak memory 201932 kb
Host smart-e2dc6708-2018-472b-8333-3f80e03cac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820247331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2820247331
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.897068728
Short name T82
Test name
Test status
Simulation time 8173851733 ps
CPU time 4.64 seconds
Started Jul 16 07:17:40 PM PDT 24
Finished Jul 16 07:17:48 PM PDT 24
Peak memory 217308 kb
Host smart-66a7e9d4-af89-441f-b9e7-fc5857199ee3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897068728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.897068728
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.299134612
Short name T284
Test name
Test status
Simulation time 330854843261 ps
CPU time 375.46 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:26:44 PM PDT 24
Peak memory 201904 kb
Host smart-2dcbd070-f3cf-4f19-b6f5-fc4508af92a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299134612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.299134612
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3623571451
Short name T100
Test name
Test status
Simulation time 480630664349 ps
CPU time 1194.48 seconds
Started Jul 16 07:17:45 PM PDT 24
Finished Jul 16 07:37:40 PM PDT 24
Peak memory 201948 kb
Host smart-c558984a-c1f4-4774-9915-56f169a9a5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623571451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3623571451
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3232309473
Short name T316
Test name
Test status
Simulation time 161900748209 ps
CPU time 199.22 seconds
Started Jul 16 07:19:04 PM PDT 24
Finished Jul 16 07:23:19 PM PDT 24
Peak memory 201920 kb
Host smart-145c0e0f-2f15-469d-bb5e-f496f949a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232309473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3232309473
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2115335622
Short name T281
Test name
Test status
Simulation time 332960465427 ps
CPU time 774.3 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:30:08 PM PDT 24
Peak memory 201888 kb
Host smart-e4a0e31e-a9e1-40bb-a12b-e32870580c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115335622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2115335622
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1857990031
Short name T42
Test name
Test status
Simulation time 519681103952 ps
CPU time 142.28 seconds
Started Jul 16 07:17:45 PM PDT 24
Finished Jul 16 07:20:09 PM PDT 24
Peak memory 210240 kb
Host smart-860d9b81-6fc8-425a-ac0c-d5c739e8a1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857990031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1857990031
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2571924548
Short name T302
Test name
Test status
Simulation time 491267528903 ps
CPU time 1103.85 seconds
Started Jul 16 07:21:03 PM PDT 24
Finished Jul 16 07:39:40 PM PDT 24
Peak memory 201920 kb
Host smart-4d1c9a9c-d9ab-47dd-ad25-944daa037997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571924548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2571924548
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1371430028
Short name T47
Test name
Test status
Simulation time 349149760429 ps
CPU time 1384.05 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:40:21 PM PDT 24
Peak memory 202284 kb
Host smart-ea323bd9-9a49-407c-abec-37ca11811612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371430028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1371430028
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3443098470
Short name T251
Test name
Test status
Simulation time 517114827162 ps
CPU time 1121.12 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:36:17 PM PDT 24
Peak memory 201884 kb
Host smart-623c65f4-50fd-4867-b8ab-bc15d8e6135f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443098470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3443098470
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4212564293
Short name T177
Test name
Test status
Simulation time 584795754034 ps
CPU time 160.94 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:21:03 PM PDT 24
Peak memory 201888 kb
Host smart-6b9cf60e-870a-4adc-bdaa-11df17fbbe39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212564293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4212564293
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1304871642
Short name T242
Test name
Test status
Simulation time 337558577074 ps
CPU time 605.71 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:28:56 PM PDT 24
Peak memory 201868 kb
Host smart-1fbaf92f-9657-493d-bcc0-3ef6f7353e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304871642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1304871642
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1377732338
Short name T330
Test name
Test status
Simulation time 489148122722 ps
CPU time 173.38 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:20:18 PM PDT 24
Peak memory 201824 kb
Host smart-e32b6b71-c3bc-4684-9f86-faf96e960048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377732338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1377732338
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3739587089
Short name T267
Test name
Test status
Simulation time 39111541151 ps
CPU time 129.5 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:19:13 PM PDT 24
Peak memory 210684 kb
Host smart-8704efed-3585-4de2-ae68-d28f660b0870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739587089 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3739587089
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1509863239
Short name T373
Test name
Test status
Simulation time 333809130565 ps
CPU time 327.47 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:23:06 PM PDT 24
Peak memory 201792 kb
Host smart-74fca4c3-6b0b-44c0-9aa1-82f608035125
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509863239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1509863239
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4169180007
Short name T234
Test name
Test status
Simulation time 497440082104 ps
CPU time 1089.5 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:36:14 PM PDT 24
Peak memory 201836 kb
Host smart-6bc175dd-abe4-4625-aae5-f6240f0137a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169180007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4169180007
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.333685932
Short name T167
Test name
Test status
Simulation time 640408790050 ps
CPU time 1399.58 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:42:07 PM PDT 24
Peak memory 201552 kb
Host smart-9faae5a8-184b-4dea-be89-74e2dc75b144
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333685932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.333685932
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3186204083
Short name T131
Test name
Test status
Simulation time 4539810240 ps
CPU time 3.72 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:20 PM PDT 24
Peak memory 201812 kb
Host smart-d4d6500e-ff24-4847-9266-e1c82911887f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186204083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3186204083
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2648890124
Short name T334
Test name
Test status
Simulation time 359691420350 ps
CPU time 220.63 seconds
Started Jul 16 07:17:50 PM PDT 24
Finished Jul 16 07:21:35 PM PDT 24
Peak memory 201984 kb
Host smart-b7852e61-b599-4725-9022-32c763166a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648890124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2648890124
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.990786303
Short name T182
Test name
Test status
Simulation time 494655376327 ps
CPU time 1049.68 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:34:36 PM PDT 24
Peak memory 201820 kb
Host smart-9b8ee147-9b98-4d2b-84c2-04e24ea6aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990786303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.990786303
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1681389777
Short name T328
Test name
Test status
Simulation time 175593727659 ps
CPU time 102.02 seconds
Started Jul 16 07:18:12 PM PDT 24
Finished Jul 16 07:20:30 PM PDT 24
Peak memory 202012 kb
Host smart-ac0e212b-3719-4799-8045-464187dda970
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681389777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1681389777
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2971861005
Short name T224
Test name
Test status
Simulation time 166979208333 ps
CPU time 349.74 seconds
Started Jul 16 07:16:56 PM PDT 24
Finished Jul 16 07:23:04 PM PDT 24
Peak memory 201968 kb
Host smart-101662a2-685d-4a50-936e-2e6783e6983a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971861005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2971861005
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3451261976
Short name T65
Test name
Test status
Simulation time 435122604 ps
CPU time 2.37 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:09 PM PDT 24
Peak memory 201704 kb
Host smart-77e56df2-16bd-4370-9724-6a5b6b94c437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451261976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3451261976
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1506320279
Short name T301
Test name
Test status
Simulation time 166502041198 ps
CPU time 100.73 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:19:02 PM PDT 24
Peak memory 201896 kb
Host smart-6f1c7c37-d8d3-4549-8236-61e70d0acdf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506320279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1506320279
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1337402067
Short name T327
Test name
Test status
Simulation time 347530427685 ps
CPU time 197.92 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:20:22 PM PDT 24
Peak memory 201940 kb
Host smart-7afc0a30-adde-483f-8cd6-25520fa154a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337402067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1337402067
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2778607716
Short name T278
Test name
Test status
Simulation time 345231350627 ps
CPU time 704.34 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:30:35 PM PDT 24
Peak memory 201892 kb
Host smart-05427b53-5449-4cb0-aae0-c54db8ecf948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778607716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2778607716
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1654779833
Short name T337
Test name
Test status
Simulation time 206000881685 ps
CPU time 221.37 seconds
Started Jul 16 07:18:13 PM PDT 24
Finished Jul 16 07:22:30 PM PDT 24
Peak memory 210168 kb
Host smart-36980e6b-60ca-4b69-ab59-618834e1769d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654779833 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1654779833
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.591896746
Short name T137
Test name
Test status
Simulation time 503210503322 ps
CPU time 1108.16 seconds
Started Jul 16 07:18:52 PM PDT 24
Finished Jul 16 07:38:11 PM PDT 24
Peak memory 201888 kb
Host smart-a51e85a8-c76a-4923-8299-4d136337bf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591896746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.591896746
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3724473726
Short name T297
Test name
Test status
Simulation time 328581988654 ps
CPU time 367.82 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:26:44 PM PDT 24
Peak memory 210512 kb
Host smart-165e9de2-b7d5-42c1-aa9e-a30b3ba13b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724473726 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3724473726
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2562081546
Short name T152
Test name
Test status
Simulation time 172784358248 ps
CPU time 362.24 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:27:14 PM PDT 24
Peak memory 201840 kb
Host smart-ba93f408-556f-4988-a0c1-9289b75fc3c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562081546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2562081546
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2291144511
Short name T317
Test name
Test status
Simulation time 669566985792 ps
CPU time 209.63 seconds
Started Jul 16 07:16:56 PM PDT 24
Finished Jul 16 07:20:44 PM PDT 24
Peak memory 201908 kb
Host smart-d9a68ce5-5697-48e1-88e2-c11091788883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291144511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2291144511
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1605658275
Short name T214
Test name
Test status
Simulation time 100492678381 ps
CPU time 345.66 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 202184 kb
Host smart-02008bfe-4dc3-468f-b320-f2877f8bcc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605658275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1605658275
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2638746122
Short name T252
Test name
Test status
Simulation time 1197715996995 ps
CPU time 298.28 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:21:53 PM PDT 24
Peak memory 210268 kb
Host smart-46f70b7c-6d28-4d8f-9259-c84ebddaa6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638746122 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2638746122
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.48691155
Short name T21
Test name
Test status
Simulation time 18888995336 ps
CPU time 22.98 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:18:21 PM PDT 24
Peak memory 210212 kb
Host smart-a8d6a506-d90c-4258-a7dd-ea167257e3c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48691155 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.48691155
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.119306319
Short name T190
Test name
Test status
Simulation time 506422749075 ps
CPU time 196.84 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:21:22 PM PDT 24
Peak memory 201868 kb
Host smart-6168c4c9-982d-47d1-b43e-a118fe9afefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119306319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.119306319
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1561981033
Short name T225
Test name
Test status
Simulation time 162359570096 ps
CPU time 343.22 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:24:38 PM PDT 24
Peak memory 201912 kb
Host smart-4b70ded5-61f5-4c48-99e3-cbbc72434f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561981033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1561981033
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1398737981
Short name T18
Test name
Test status
Simulation time 64633422541 ps
CPU time 170.87 seconds
Started Jul 16 07:21:05 PM PDT 24
Finished Jul 16 07:24:09 PM PDT 24
Peak memory 210528 kb
Host smart-e21da3e9-3e6f-4400-8926-f9f224790f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398737981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1398737981
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3539681105
Short name T148
Test name
Test status
Simulation time 592659040256 ps
CPU time 98.96 seconds
Started Jul 16 07:16:12 PM PDT 24
Finished Jul 16 07:18:38 PM PDT 24
Peak memory 201892 kb
Host smart-90c27cb6-6da5-463d-94a7-fe3cc680f119
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539681105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3539681105
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1334000685
Short name T323
Test name
Test status
Simulation time 170356913942 ps
CPU time 192 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:20:29 PM PDT 24
Peak memory 201900 kb
Host smart-df207505-736e-4eb6-b0b0-48b026eda633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334000685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1334000685
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.185412969
Short name T229
Test name
Test status
Simulation time 165291067918 ps
CPU time 283.67 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:22:05 PM PDT 24
Peak memory 201880 kb
Host smart-7fb7fe96-0e18-4947-b181-9182fb9a9628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185412969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
185412969
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.944876537
Short name T238
Test name
Test status
Simulation time 335879728517 ps
CPU time 362.99 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:23:25 PM PDT 24
Peak memory 201972 kb
Host smart-2d6d73ed-bf79-44e8-8e95-39572190943a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944876537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.944876537
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.302177080
Short name T271
Test name
Test status
Simulation time 322635593316 ps
CPU time 143.51 seconds
Started Jul 16 07:17:32 PM PDT 24
Finished Jul 16 07:19:58 PM PDT 24
Peak memory 201920 kb
Host smart-9066db14-7930-4fa0-af8e-8364d33c4d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302177080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
302177080
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3597838959
Short name T206
Test name
Test status
Simulation time 252232231130 ps
CPU time 879.29 seconds
Started Jul 16 07:18:05 PM PDT 24
Finished Jul 16 07:33:14 PM PDT 24
Peak memory 211564 kb
Host smart-b5179d1d-62d3-4477-b99c-e100a23cf53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597838959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3597838959
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1645853417
Short name T299
Test name
Test status
Simulation time 182682110179 ps
CPU time 406.69 seconds
Started Jul 16 07:18:26 PM PDT 24
Finished Jul 16 07:25:53 PM PDT 24
Peak memory 201904 kb
Host smart-cb7d7d32-7f0b-47f7-9b40-784d717228d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645853417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1645853417
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.4204231687
Short name T208
Test name
Test status
Simulation time 87907510316 ps
CPU time 423.83 seconds
Started Jul 16 07:18:51 PM PDT 24
Finished Jul 16 07:26:46 PM PDT 24
Peak memory 202108 kb
Host smart-bca68d2a-e4c2-4ea8-ab2b-80f5c92d6652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204231687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4204231687
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3637344778
Short name T294
Test name
Test status
Simulation time 353734537992 ps
CPU time 813.34 seconds
Started Jul 16 07:19:07 PM PDT 24
Finished Jul 16 07:33:36 PM PDT 24
Peak memory 201912 kb
Host smart-b260693b-83dc-4e06-92ae-d2f85da62fd0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637344778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3637344778
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2210018242
Short name T259
Test name
Test status
Simulation time 50637593429 ps
CPU time 110.57 seconds
Started Jul 16 07:19:55 PM PDT 24
Finished Jul 16 07:22:36 PM PDT 24
Peak memory 210552 kb
Host smart-96408c04-825a-4ddf-a180-430cab166888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210018242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2210018242
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.712714778
Short name T292
Test name
Test status
Simulation time 494293805432 ps
CPU time 1003.53 seconds
Started Jul 16 07:20:06 PM PDT 24
Finished Jul 16 07:37:33 PM PDT 24
Peak memory 201976 kb
Host smart-4fcd31ac-e3b0-4c6a-b583-cc3b297b0e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712714778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.712714778
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.733077972
Short name T159
Test name
Test status
Simulation time 322034674798 ps
CPU time 108.19 seconds
Started Jul 16 07:16:42 PM PDT 24
Finished Jul 16 07:18:57 PM PDT 24
Peak memory 201912 kb
Host smart-cadefe68-1c93-4480-b2cf-d8a5fa80ca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733077972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.733077972
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2450874774
Short name T243
Test name
Test status
Simulation time 351866542183 ps
CPU time 651.5 seconds
Started Jul 16 07:16:54 PM PDT 24
Finished Jul 16 07:28:06 PM PDT 24
Peak memory 201928 kb
Host smart-961400f4-c2a6-4e95-bbc0-0d36790c25f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450874774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2450874774
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.844871791
Short name T80
Test name
Test status
Simulation time 4667878556 ps
CPU time 6.31 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:33 PM PDT 24
Peak memory 201864 kb
Host smart-004d07da-29f5-40a9-8976-e79c369b8b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844871791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.844871791
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2596113307
Short name T77
Test name
Test status
Simulation time 8438110412 ps
CPU time 9.54 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:16 PM PDT 24
Peak memory 201896 kb
Host smart-36376b30-4379-4d84-a660-aa6d5a39d195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596113307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2596113307
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2539058526
Short name T64
Test name
Test status
Simulation time 4296305174 ps
CPU time 11.86 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201812 kb
Host smart-3f614ab8-0e83-4d17-a1dd-4bc159b60f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539058526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2539058526
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3333977518
Short name T310
Test name
Test status
Simulation time 488951406196 ps
CPU time 266.28 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:21:43 PM PDT 24
Peak memory 201900 kb
Host smart-cb0ab5e0-0592-4604-a048-dc3bfda10d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333977518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3333977518
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2746127073
Short name T781
Test name
Test status
Simulation time 187114852666 ps
CPU time 230.08 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:21:29 PM PDT 24
Peak memory 217808 kb
Host smart-6c2d35b7-c55b-4e43-95bb-d52c82a5d2db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746127073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2746127073
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.432000992
Short name T347
Test name
Test status
Simulation time 85257551806 ps
CPU time 290.33 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:22:56 PM PDT 24
Peak memory 202204 kb
Host smart-94e0bf2b-f0b0-45a0-bab2-ff4ff0327599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432000992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.432000992
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3908659271
Short name T191
Test name
Test status
Simulation time 495261980231 ps
CPU time 152.4 seconds
Started Jul 16 07:18:03 PM PDT 24
Finished Jul 16 07:21:04 PM PDT 24
Peak memory 201904 kb
Host smart-222de62e-f15b-4750-851b-dc3e5b62d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908659271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3908659271
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.864479060
Short name T261
Test name
Test status
Simulation time 487002662456 ps
CPU time 1045.25 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:34:31 PM PDT 24
Peak memory 201920 kb
Host smart-55fefebf-1078-4983-9061-4576f5a32d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864479060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.864479060
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.885936866
Short name T240
Test name
Test status
Simulation time 703537758347 ps
CPU time 1443.47 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:42:45 PM PDT 24
Peak memory 201924 kb
Host smart-219b8fcb-be99-412e-9f85-49220d72d61a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885936866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.885936866
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.332769419
Short name T289
Test name
Test status
Simulation time 346489582864 ps
CPU time 197.63 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:22:43 PM PDT 24
Peak memory 201900 kb
Host smart-0afb293d-1d34-45bb-a1b5-306534a715d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332769419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.332769419
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1196639004
Short name T218
Test name
Test status
Simulation time 254404931159 ps
CPU time 474.72 seconds
Started Jul 16 07:19:07 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 210604 kb
Host smart-ad5f9e64-0f41-4075-9fe7-50fd16d37e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196639004 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1196639004
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3598883735
Short name T320
Test name
Test status
Simulation time 357568939611 ps
CPU time 157.58 seconds
Started Jul 16 07:20:07 PM PDT 24
Finished Jul 16 07:23:29 PM PDT 24
Peak memory 201852 kb
Host smart-f03c5b1f-72a8-447c-8112-9f5e76409258
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598883735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3598883735
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1430749172
Short name T247
Test name
Test status
Simulation time 367227238343 ps
CPU time 791.31 seconds
Started Jul 16 07:16:55 PM PDT 24
Finished Jul 16 07:30:26 PM PDT 24
Peak memory 201976 kb
Host smart-94d6bec4-8110-4d5e-97ab-033616b9a924
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430749172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1430749172
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2116184671
Short name T126
Test name
Test status
Simulation time 953761984 ps
CPU time 3.04 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:29 PM PDT 24
Peak memory 201724 kb
Host smart-cc42b5cd-d261-4982-8d6b-9c01e3ec6aba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116184671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2116184671
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1477244726
Short name T120
Test name
Test status
Simulation time 37486118404 ps
CPU time 84.24 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:13:51 PM PDT 24
Peak memory 201860 kb
Host smart-86424f1e-518a-4ff6-ab98-4e490f181e06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477244726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1477244726
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4146281562
Short name T117
Test name
Test status
Simulation time 689593585 ps
CPU time 1.05 seconds
Started Jul 16 07:11:16 PM PDT 24
Finished Jul 16 07:12:16 PM PDT 24
Peak memory 201504 kb
Host smart-5cf776f7-f0e5-4606-9d47-de9845399243
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146281562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4146281562
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1288789367
Short name T898
Test name
Test status
Simulation time 500648434 ps
CPU time 1.37 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:18 PM PDT 24
Peak memory 201528 kb
Host smart-3c1da59d-81ff-44b4-b426-187f143f6a1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288789367 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1288789367
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.898155887
Short name T846
Test name
Test status
Simulation time 470817890 ps
CPU time 1.75 seconds
Started Jul 16 07:11:16 PM PDT 24
Finished Jul 16 07:12:18 PM PDT 24
Peak memory 201488 kb
Host smart-79891b44-437c-4204-9db8-e2aa6d97de24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898155887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.898155887
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.302519928
Short name T800
Test name
Test status
Simulation time 319433746 ps
CPU time 0.7 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 201632 kb
Host smart-cf23cf7a-f54a-4c16-8c9c-f09c3d96de9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302519928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.302519928
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.372404141
Short name T887
Test name
Test status
Simulation time 2291983143 ps
CPU time 5.23 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:30 PM PDT 24
Peak memory 201592 kb
Host smart-97493d6b-92d9-4a10-bd4b-a214450a8b90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372404141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.372404141
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4073428963
Short name T914
Test name
Test status
Simulation time 748081262 ps
CPU time 3.19 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:30 PM PDT 24
Peak memory 201796 kb
Host smart-2294fb2b-64ba-4d1f-9ee9-25fac34ae53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073428963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4073428963
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1851113529
Short name T106
Test name
Test status
Simulation time 8853297964 ps
CPU time 4.66 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:21 PM PDT 24
Peak memory 201788 kb
Host smart-90c10293-3a32-482b-a3fa-18d393fc4d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851113529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1851113529
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3165885009
Short name T917
Test name
Test status
Simulation time 689945995 ps
CPU time 2.25 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:19 PM PDT 24
Peak memory 201708 kb
Host smart-6890d02c-afe0-45c1-9522-bb80ca1936a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165885009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3165885009
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2624546352
Short name T915
Test name
Test status
Simulation time 39450881952 ps
CPU time 200.61 seconds
Started Jul 16 07:11:24 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 201844 kb
Host smart-527862ef-0fca-4571-9a2a-88d924dcc543
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624546352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2624546352
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.804881837
Short name T833
Test name
Test status
Simulation time 793825895 ps
CPU time 1.51 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:27 PM PDT 24
Peak memory 201480 kb
Host smart-03234922-2cbf-4ce4-9a7e-63913739ae93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804881837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.804881837
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1129232793
Short name T905
Test name
Test status
Simulation time 667655756 ps
CPU time 1.18 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:36 PM PDT 24
Peak memory 201744 kb
Host smart-26fec637-2758-49b4-b06d-5523a6d1b7e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129232793 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1129232793
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1986261601
Short name T913
Test name
Test status
Simulation time 347768173 ps
CPU time 1.05 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 201404 kb
Host smart-d2cda1ca-b08b-42bd-9c7b-9523f0d40dc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986261601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1986261601
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2594127231
Short name T811
Test name
Test status
Simulation time 324105756 ps
CPU time 1.35 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201404 kb
Host smart-d29505cb-904d-484d-8d89-d343d64fa506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594127231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2594127231
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3493708617
Short name T74
Test name
Test status
Simulation time 758235064 ps
CPU time 2.26 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:58 PM PDT 24
Peak memory 201748 kb
Host smart-5ed543b6-bc52-44cc-acc5-c81f5521c2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493708617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3493708617
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3465262236
Short name T823
Test name
Test status
Simulation time 4864061900 ps
CPU time 5.16 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:21 PM PDT 24
Peak memory 201776 kb
Host smart-838cb36d-0359-4e92-868e-e46e9dc1f354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465262236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3465262236
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2073240988
Short name T909
Test name
Test status
Simulation time 487719945 ps
CPU time 1.25 seconds
Started Jul 16 07:11:34 PM PDT 24
Finished Jul 16 07:13:04 PM PDT 24
Peak memory 201568 kb
Host smart-4edd350f-8dc7-4bed-bbb3-02531cec7e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073240988 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2073240988
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2102134088
Short name T918
Test name
Test status
Simulation time 405453589 ps
CPU time 1.04 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201440 kb
Host smart-ff22ce1f-02d3-47d5-bf98-62639424a570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102134088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2102134088
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.343298790
Short name T829
Test name
Test status
Simulation time 377186100 ps
CPU time 1.46 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:56 PM PDT 24
Peak memory 201352 kb
Host smart-2c422dbc-7cd4-404a-a1d1-926945c1c9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343298790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.343298790
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2561610408
Short name T852
Test name
Test status
Simulation time 4913877499 ps
CPU time 6.78 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:13:04 PM PDT 24
Peak memory 201828 kb
Host smart-e4cb1097-abcb-4e2e-a3ab-570f5661b1a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561610408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2561610408
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1810017625
Short name T72
Test name
Test status
Simulation time 608137829 ps
CPU time 3.77 seconds
Started Jul 16 07:11:28 PM PDT 24
Finished Jul 16 07:13:01 PM PDT 24
Peak memory 211036 kb
Host smart-6bb723c5-60eb-48a8-be9f-f32207d58cee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810017625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1810017625
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1059653291
Short name T900
Test name
Test status
Simulation time 4792489476 ps
CPU time 7.29 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:14 PM PDT 24
Peak memory 201784 kb
Host smart-85a463c7-ece1-4a7e-89a6-89fff04c6e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059653291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1059653291
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1616060744
Short name T856
Test name
Test status
Simulation time 520722241 ps
CPU time 1.44 seconds
Started Jul 16 07:11:34 PM PDT 24
Finished Jul 16 07:13:03 PM PDT 24
Peak memory 201568 kb
Host smart-c1069cdf-5134-4094-a63c-03d4d68b0188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616060744 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1616060744
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3347014193
Short name T123
Test name
Test status
Simulation time 557979090 ps
CPU time 1.03 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201480 kb
Host smart-386e4c4f-2e7b-46ca-8769-117174fb6e2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347014193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3347014193
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4088275679
Short name T902
Test name
Test status
Simulation time 415712115 ps
CPU time 1.05 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201404 kb
Host smart-bffe0a1a-3564-4af1-aeeb-9c6bf6c0a2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088275679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4088275679
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2052729941
Short name T132
Test name
Test status
Simulation time 4746296942 ps
CPU time 3.32 seconds
Started Jul 16 07:11:27 PM PDT 24
Finished Jul 16 07:12:54 PM PDT 24
Peak memory 201800 kb
Host smart-2973a3d0-f95c-4ac9-80b3-02433e3be2bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052729941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2052729941
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2664875780
Short name T892
Test name
Test status
Simulation time 717947710 ps
CPU time 2.26 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:13:00 PM PDT 24
Peak memory 210992 kb
Host smart-dc809787-5f04-435b-be67-5d9a75cfa5f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664875780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2664875780
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2872949715
Short name T874
Test name
Test status
Simulation time 4393088053 ps
CPU time 4.13 seconds
Started Jul 16 07:11:28 PM PDT 24
Finished Jul 16 07:13:01 PM PDT 24
Peak memory 201836 kb
Host smart-cd19b5e3-2e69-4c0b-a3c2-e2a5236a1707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872949715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2872949715
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1161879631
Short name T916
Test name
Test status
Simulation time 500203226 ps
CPU time 1.48 seconds
Started Jul 16 07:11:28 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201524 kb
Host smart-35e64571-eae5-4277-87ec-17df7b3ff227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161879631 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1161879631
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3495668296
Short name T130
Test name
Test status
Simulation time 353569885 ps
CPU time 1.53 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:58 PM PDT 24
Peak memory 201480 kb
Host smart-f888b326-a0f5-4f2a-bb40-1fbab65eb43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495668296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3495668296
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1976925677
Short name T806
Test name
Test status
Simulation time 327563632 ps
CPU time 0.98 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201428 kb
Host smart-3c090222-9bac-4663-b5ce-be05513936b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976925677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1976925677
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2431854282
Short name T854
Test name
Test status
Simulation time 4890768458 ps
CPU time 9.45 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201832 kb
Host smart-123c09f5-829d-4181-b638-d0c230562ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431854282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2431854282
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.113956362
Short name T876
Test name
Test status
Simulation time 482379454 ps
CPU time 2.59 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:09 PM PDT 24
Peak memory 201812 kb
Host smart-a6386d83-2224-46f3-8d13-7bcf293682dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113956362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.113956362
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.169965188
Short name T105
Test name
Test status
Simulation time 436296816 ps
CPU time 1.36 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201528 kb
Host smart-b888b03e-e58b-4a09-924a-f7774a7789fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169965188 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.169965188
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4003700490
Short name T129
Test name
Test status
Simulation time 354751134 ps
CPU time 1.51 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201504 kb
Host smart-8856066f-7189-4150-9a7a-81085bc988f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003700490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4003700490
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.962327983
Short name T821
Test name
Test status
Simulation time 468047626 ps
CPU time 1.66 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201428 kb
Host smart-1c2de991-dd4a-4414-be13-909f83054271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962327983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.962327983
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3724128493
Short name T888
Test name
Test status
Simulation time 4550546106 ps
CPU time 18.33 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:16 PM PDT 24
Peak memory 201844 kb
Host smart-f811309f-8a4e-4048-8453-8ba27ec95137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724128493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3724128493
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.747972738
Short name T835
Test name
Test status
Simulation time 579871816 ps
CPU time 1.91 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:13:00 PM PDT 24
Peak memory 201748 kb
Host smart-96686128-6ea8-454e-8153-cb8004956795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747972738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.747972738
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1499100626
Short name T872
Test name
Test status
Simulation time 4511185060 ps
CPU time 12.06 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201188 kb
Host smart-67d0ff5e-a0bd-4f31-b298-c93144ebe15b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499100626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1499100626
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3599025225
Short name T873
Test name
Test status
Simulation time 582229633 ps
CPU time 1.1 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201548 kb
Host smart-2f4220da-5473-4a20-9bc6-01b0017941ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599025225 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3599025225
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2840038212
Short name T901
Test name
Test status
Simulation time 370705898 ps
CPU time 1.65 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201532 kb
Host smart-be6d3a26-7dcb-4d4d-aa54-2913a6f6416e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840038212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2840038212
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3658513727
Short name T814
Test name
Test status
Simulation time 341698776 ps
CPU time 1.02 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201400 kb
Host smart-210aaed3-3445-49c1-ae8f-3a6ecd180e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658513727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3658513727
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2733855113
Short name T58
Test name
Test status
Simulation time 3839200948 ps
CPU time 2.6 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:13:00 PM PDT 24
Peak memory 201708 kb
Host smart-0ff0c109-4bf3-4073-a0dc-a4d86aa8bb12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733855113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2733855113
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1645948813
Short name T883
Test name
Test status
Simulation time 474850793 ps
CPU time 3.19 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:24 PM PDT 24
Peak memory 218088 kb
Host smart-ca229964-61cc-430b-a980-b7d8f21ef8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645948813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1645948813
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1777087604
Short name T63
Test name
Test status
Simulation time 4266168282 ps
CPU time 6.73 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 201872 kb
Host smart-b0fa4747-427e-482a-8f4a-797de6c0b818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777087604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1777087604
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.38435642
Short name T875
Test name
Test status
Simulation time 580903467 ps
CPU time 1.34 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201512 kb
Host smart-08a00918-73e2-4ddc-957a-5f9d4f531639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38435642 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.38435642
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2494071228
Short name T125
Test name
Test status
Simulation time 538904458 ps
CPU time 1.11 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 201520 kb
Host smart-b8acadc0-0450-44f0-b717-9e3c82ee9164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494071228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2494071228
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3914978182
Short name T848
Test name
Test status
Simulation time 384571503 ps
CPU time 1.44 seconds
Started Jul 16 07:11:33 PM PDT 24
Finished Jul 16 07:13:03 PM PDT 24
Peak memory 201384 kb
Host smart-3ab67707-3f4e-4ea7-b3ed-b421440021dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914978182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3914978182
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2523725529
Short name T857
Test name
Test status
Simulation time 4068148684 ps
CPU time 9.03 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:15 PM PDT 24
Peak memory 201180 kb
Host smart-5f2cdd79-cfc5-4d7c-a31d-3d141f4709e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523725529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2523725529
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2315634231
Short name T840
Test name
Test status
Simulation time 4625447463 ps
CPU time 4.17 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:24 PM PDT 24
Peak memory 201840 kb
Host smart-b0879db4-275f-477f-8cea-b47bf6b466f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315634231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2315634231
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2452125557
Short name T817
Test name
Test status
Simulation time 559639301 ps
CPU time 1.21 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201540 kb
Host smart-532c622e-eb2d-4825-b601-f7387f52a4d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452125557 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2452125557
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3716135649
Short name T127
Test name
Test status
Simulation time 346960382 ps
CPU time 0.92 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201500 kb
Host smart-45973ae9-3f90-40f9-b3e7-c6663ee2bb50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716135649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3716135649
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3501520234
Short name T904
Test name
Test status
Simulation time 365838733 ps
CPU time 1.08 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:13:01 PM PDT 24
Peak memory 201368 kb
Host smart-2cc2e928-6660-4bc8-8acc-d077bb15cac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501520234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3501520234
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2687419390
Short name T133
Test name
Test status
Simulation time 5146663294 ps
CPU time 16.88 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 201828 kb
Host smart-c7a23dcf-02db-4f06-9473-d006ff3daa10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687419390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2687419390
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.66399834
Short name T832
Test name
Test status
Simulation time 579086497 ps
CPU time 1.94 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:00 PM PDT 24
Peak memory 201760 kb
Host smart-b37f6df0-280c-4c43-984b-a1a096d30143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66399834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.66399834
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1690056999
Short name T851
Test name
Test status
Simulation time 4423296771 ps
CPU time 3.91 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:13:02 PM PDT 24
Peak memory 201748 kb
Host smart-79efff04-3288-4efd-b331-746ed611991b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690056999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1690056999
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.647267669
Short name T843
Test name
Test status
Simulation time 424659293 ps
CPU time 1.73 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201540 kb
Host smart-05eb0282-9083-4a1f-8707-fce1c3f90649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647267669 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.647267669
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1705213456
Short name T908
Test name
Test status
Simulation time 417916481 ps
CPU time 0.83 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:13:05 PM PDT 24
Peak memory 201456 kb
Host smart-c37ae3a4-c95b-4a74-9709-0b20b7264837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705213456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1705213456
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2339230204
Short name T845
Test name
Test status
Simulation time 457156415 ps
CPU time 1.1 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201388 kb
Host smart-6a1bab9e-e992-41e5-8b80-5b17b31e34ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339230204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2339230204
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1848610901
Short name T134
Test name
Test status
Simulation time 3005694658 ps
CPU time 4.34 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 201632 kb
Host smart-dcae2285-6b91-4c93-90f0-4b0f7473968a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848610901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1848610901
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3474892685
Short name T66
Test name
Test status
Simulation time 480672189 ps
CPU time 1.57 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:08 PM PDT 24
Peak memory 201748 kb
Host smart-3a5ad75a-d0ef-4991-8611-210b3322543e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474892685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3474892685
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2051681452
Short name T903
Test name
Test status
Simulation time 610259535 ps
CPU time 1.02 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201648 kb
Host smart-9a4619dd-94b7-4e9a-9849-e91f6071f42d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051681452 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2051681452
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3391610051
Short name T895
Test name
Test status
Simulation time 400330858 ps
CPU time 1.67 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201584 kb
Host smart-ea4a4b1e-fea1-4e9e-ad72-eaa3938d9c51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391610051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3391610051
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1517999873
Short name T880
Test name
Test status
Simulation time 513029726 ps
CPU time 0.95 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201388 kb
Host smart-afb04baa-805b-4771-b2c7-4869e2114c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517999873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1517999873
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2812723649
Short name T868
Test name
Test status
Simulation time 4629705977 ps
CPU time 7.54 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:04 PM PDT 24
Peak memory 201960 kb
Host smart-c34a90da-21f5-4014-89db-718e29c635ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812723649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2812723649
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3412455074
Short name T906
Test name
Test status
Simulation time 521872442 ps
CPU time 2.65 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 201816 kb
Host smart-ee677579-8d38-4156-9373-b8e892bb12d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412455074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3412455074
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.157074981
Short name T891
Test name
Test status
Simulation time 8488595563 ps
CPU time 11.98 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201752 kb
Host smart-1dc6738d-b52d-4a6b-b518-e50196c72a2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157074981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.157074981
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3035628630
Short name T864
Test name
Test status
Simulation time 725680519 ps
CPU time 1.46 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:09 PM PDT 24
Peak memory 201516 kb
Host smart-4e7770ca-74a7-46ac-8788-4c87bb7e2415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035628630 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3035628630
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1512094898
Short name T886
Test name
Test status
Simulation time 367636059 ps
CPU time 1.12 seconds
Started Jul 16 07:11:38 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 200944 kb
Host smart-fbe141a7-d655-4ae1-b05d-715e6ad81784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512094898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1512094898
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1094450198
Short name T869
Test name
Test status
Simulation time 491760453 ps
CPU time 0.82 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:58 PM PDT 24
Peak memory 201384 kb
Host smart-447e5fbd-3191-4cd7-9cd0-cb20854952db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094450198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1094450198
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2593441162
Short name T863
Test name
Test status
Simulation time 2837125990 ps
CPU time 10.85 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:13:08 PM PDT 24
Peak memory 201756 kb
Host smart-5648769e-81de-4a52-a36d-7ae71e01f5bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593441162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2593441162
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4249421398
Short name T859
Test name
Test status
Simulation time 505588854 ps
CPU time 3.36 seconds
Started Jul 16 07:11:38 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 217248 kb
Host smart-7377498f-df63-481b-8411-764cc7755829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249421398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4249421398
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3314688927
Short name T834
Test name
Test status
Simulation time 8442441502 ps
CPU time 9.83 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201772 kb
Host smart-56bbb7a9-ba8a-4c68-8737-f5529741627a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314688927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3314688927
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2209292137
Short name T878
Test name
Test status
Simulation time 844173990 ps
CPU time 1.7 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:20 PM PDT 24
Peak memory 201644 kb
Host smart-7eaecf24-91f3-4db7-8925-a73b0c74f3f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209292137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2209292137
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1206773483
Short name T119
Test name
Test status
Simulation time 10973250826 ps
CPU time 9.34 seconds
Started Jul 16 07:11:28 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201764 kb
Host smart-f28a25e9-d7d9-4515-a1bf-2861bda90ffc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206773483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1206773483
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1357340491
Short name T836
Test name
Test status
Simulation time 1152653068 ps
CPU time 3.07 seconds
Started Jul 16 07:11:25 PM PDT 24
Finished Jul 16 07:12:51 PM PDT 24
Peak memory 201504 kb
Host smart-55b56310-2e4a-4b45-97fb-05e3683a6866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357340491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1357340491
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.707670870
Short name T95
Test name
Test status
Simulation time 595866818 ps
CPU time 1.48 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 201596 kb
Host smart-157b59f5-be5f-4d07-97a2-d823e9425db2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707670870 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.707670870
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3677792915
Short name T885
Test name
Test status
Simulation time 396604160 ps
CPU time 0.92 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:37 PM PDT 24
Peak memory 201696 kb
Host smart-7f6e6537-259a-432e-96f1-fa2756bc38e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677792915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3677792915
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1815727148
Short name T827
Test name
Test status
Simulation time 379010923 ps
CPU time 1.51 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:28 PM PDT 24
Peak memory 201428 kb
Host smart-7dc5e02a-1e23-49c8-83de-1481e3dc38dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815727148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1815727148
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.809479274
Short name T897
Test name
Test status
Simulation time 3699023528 ps
CPU time 3.47 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:29 PM PDT 24
Peak memory 201832 kb
Host smart-1ee28290-0042-44b6-affb-664c83dd5379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809479274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.809479274
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1420599900
Short name T78
Test name
Test status
Simulation time 645014640 ps
CPU time 1.85 seconds
Started Jul 16 07:11:13 PM PDT 24
Finished Jul 16 07:12:02 PM PDT 24
Peak memory 201756 kb
Host smart-2a471318-1010-4303-89d6-2a0970205d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420599900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1420599900
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2848257516
Short name T803
Test name
Test status
Simulation time 315638588 ps
CPU time 0.79 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201256 kb
Host smart-c11eb42a-e38f-413c-95c1-57c56198bcb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848257516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2848257516
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1390746084
Short name T809
Test name
Test status
Simulation time 377432238 ps
CPU time 0.81 seconds
Started Jul 16 07:11:45 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 201384 kb
Host smart-f0b0bfde-7c80-4021-ae3c-3f3ba01260f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390746084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1390746084
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.242208639
Short name T808
Test name
Test status
Simulation time 369190672 ps
CPU time 1.21 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:09 PM PDT 24
Peak memory 201380 kb
Host smart-d4f79617-c582-4ac9-a335-40da64a865cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242208639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.242208639
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1645833789
Short name T804
Test name
Test status
Simulation time 448202381 ps
CPU time 0.79 seconds
Started Jul 16 07:11:38 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201016 kb
Host smart-0a251333-a6b6-45d1-a64c-986af2ab8ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645833789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1645833789
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3106549973
Short name T801
Test name
Test status
Simulation time 353366881 ps
CPU time 0.71 seconds
Started Jul 16 07:11:51 PM PDT 24
Finished Jul 16 07:13:21 PM PDT 24
Peak memory 201400 kb
Host smart-f9f87f87-ba2a-4be3-bbfa-f6b82651211a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106549973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3106549973
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3513479472
Short name T871
Test name
Test status
Simulation time 329738470 ps
CPU time 0.96 seconds
Started Jul 16 07:11:46 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201432 kb
Host smart-0061b62d-05f7-4f0c-8ae8-553d0f983f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513479472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3513479472
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.261830267
Short name T893
Test name
Test status
Simulation time 313639343 ps
CPU time 1.28 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:09 PM PDT 24
Peak memory 201380 kb
Host smart-8633a86f-3b13-4d4a-ad39-f8f1cfefd6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261830267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.261830267
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2324962463
Short name T830
Test name
Test status
Simulation time 418474547 ps
CPU time 1.58 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 201428 kb
Host smart-948fcc71-c67c-40ff-8374-de6b7dd4ec5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324962463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2324962463
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2717478133
Short name T799
Test name
Test status
Simulation time 519902213 ps
CPU time 1.2 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 201408 kb
Host smart-6a583e87-7cec-4de5-8c5d-98709502d24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717478133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2717478133
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.66772975
Short name T797
Test name
Test status
Simulation time 381471000 ps
CPU time 1.04 seconds
Started Jul 16 07:11:48 PM PDT 24
Finished Jul 16 07:13:13 PM PDT 24
Peak memory 201632 kb
Host smart-d0b0003c-b039-4322-8f8b-080d61100900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66772975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.66772975
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3036945737
Short name T116
Test name
Test status
Simulation time 600567250 ps
CPU time 2.69 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:36 PM PDT 24
Peak memory 201724 kb
Host smart-536bd84a-526f-456e-853d-4f43fe0806c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036945737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3036945737
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.474944987
Short name T124
Test name
Test status
Simulation time 1365712809 ps
CPU time 2.26 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:20 PM PDT 24
Peak memory 201500 kb
Host smart-567eb53c-fc1c-4e50-a84b-1e9718ca8d2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474944987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.474944987
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.416075441
Short name T815
Test name
Test status
Simulation time 823458343 ps
CPU time 1.43 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:28 PM PDT 24
Peak memory 209924 kb
Host smart-c1f35867-32e5-4a07-98be-e9a1bfd88ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416075441 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.416075441
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4117811680
Short name T128
Test name
Test status
Simulation time 538173098 ps
CPU time 1.03 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 201516 kb
Host smart-e3468fa6-7c2d-47fa-a189-500aeb6dc39a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117811680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4117811680
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2279948843
Short name T907
Test name
Test status
Simulation time 347534741 ps
CPU time 1.36 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:19 PM PDT 24
Peak memory 201436 kb
Host smart-4fe20a53-d4c2-4c1c-baa1-63d351270b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279948843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2279948843
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.587353821
Short name T866
Test name
Test status
Simulation time 4833263113 ps
CPU time 4.76 seconds
Started Jul 16 07:11:23 PM PDT 24
Finished Jul 16 07:12:42 PM PDT 24
Peak memory 201776 kb
Host smart-03ec62ce-41e6-40df-a8bb-700cc3c48e5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587353821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.587353821
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.200570567
Short name T849
Test name
Test status
Simulation time 644732546 ps
CPU time 1.83 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:29 PM PDT 24
Peak memory 201776 kb
Host smart-502fca02-30e2-433a-80f0-79be04394f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200570567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.200570567
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.21085553
Short name T96
Test name
Test status
Simulation time 4521230868 ps
CPU time 12.21 seconds
Started Jul 16 07:11:23 PM PDT 24
Finished Jul 16 07:12:49 PM PDT 24
Peak memory 201752 kb
Host smart-7cd1c2fd-3d5c-450b-8f7e-153e48694286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21085553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg
_err.21085553
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2879398481
Short name T816
Test name
Test status
Simulation time 530506575 ps
CPU time 1.77 seconds
Started Jul 16 07:11:50 PM PDT 24
Finished Jul 16 07:13:14 PM PDT 24
Peak memory 201404 kb
Host smart-6ed558d2-9581-45ba-bab2-87eb2152943e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879398481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2879398481
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.502746077
Short name T841
Test name
Test status
Simulation time 339545421 ps
CPU time 1.37 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:22 PM PDT 24
Peak memory 201440 kb
Host smart-251311d8-40d4-480b-82ee-74866d43e970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502746077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.502746077
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.277225131
Short name T884
Test name
Test status
Simulation time 381759521 ps
CPU time 0.83 seconds
Started Jul 16 07:11:44 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 201632 kb
Host smart-c5301d6d-8d47-42bf-bb96-056bac6a002d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277225131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.277225131
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2489349834
Short name T882
Test name
Test status
Simulation time 339444806 ps
CPU time 0.85 seconds
Started Jul 16 07:11:50 PM PDT 24
Finished Jul 16 07:13:13 PM PDT 24
Peak memory 201388 kb
Host smart-42b2738d-c3cd-4f47-ade2-d5bcd9d7700c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489349834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2489349834
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3105120844
Short name T839
Test name
Test status
Simulation time 573356656 ps
CPU time 0.91 seconds
Started Jul 16 07:11:45 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 201392 kb
Host smart-761f9199-31e5-4069-baa0-58b31eac079a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105120844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3105120844
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1180211165
Short name T810
Test name
Test status
Simulation time 465266730 ps
CPU time 1.75 seconds
Started Jul 16 07:11:48 PM PDT 24
Finished Jul 16 07:13:19 PM PDT 24
Peak memory 201364 kb
Host smart-66b1ffef-ffd0-4195-9530-5eaf9b3f9046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180211165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1180211165
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2483486740
Short name T802
Test name
Test status
Simulation time 477632561 ps
CPU time 0.73 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 201464 kb
Host smart-89e16190-c0f6-4e60-9a5e-c87b633bb82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483486740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2483486740
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2078003930
Short name T877
Test name
Test status
Simulation time 521509815 ps
CPU time 1.74 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 201360 kb
Host smart-56fabba0-972e-4013-b38b-48ec5aa69563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078003930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2078003930
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4010407828
Short name T798
Test name
Test status
Simulation time 306057750 ps
CPU time 1.37 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 201440 kb
Host smart-9967e637-5184-4ba0-95a9-eb2129e742f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010407828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4010407828
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2189090894
Short name T820
Test name
Test status
Simulation time 373176405 ps
CPU time 0.83 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201376 kb
Host smart-a5fcd8e1-af7d-47ac-a942-cf0142370b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189090894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2189090894
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1598580116
Short name T899
Test name
Test status
Simulation time 691679758 ps
CPU time 1.59 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:28 PM PDT 24
Peak memory 201688 kb
Host smart-b132de3d-c4c2-4d7f-bae4-4fba2ddde684
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598580116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1598580116
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.478966006
Short name T135
Test name
Test status
Simulation time 26822469821 ps
CPU time 8.11 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 201820 kb
Host smart-4e0f0ead-a528-4553-9c02-d1841da3a09b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478966006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.478966006
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4238370042
Short name T118
Test name
Test status
Simulation time 1470656520 ps
CPU time 1.08 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:17 PM PDT 24
Peak memory 201472 kb
Host smart-0000a403-1fcc-4b23-b3ba-2178311ced5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238370042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4238370042
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4032115969
Short name T94
Test name
Test status
Simulation time 465341837 ps
CPU time 1.02 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:36 PM PDT 24
Peak memory 201520 kb
Host smart-559cf991-c5b6-4727-8c3e-0df119b629d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032115969 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4032115969
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2217077271
Short name T910
Test name
Test status
Simulation time 537465015 ps
CPU time 1.44 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:28 PM PDT 24
Peak memory 201564 kb
Host smart-778cccb9-a153-4dc4-9bdb-2df370540e0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217077271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2217077271
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1589208255
Short name T824
Test name
Test status
Simulation time 375119328 ps
CPU time 1.47 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:34 PM PDT 24
Peak memory 201632 kb
Host smart-9739937e-9b00-4fae-8e61-1e51e9b1a32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589208255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1589208255
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2239751867
Short name T850
Test name
Test status
Simulation time 2468163363 ps
CPU time 8.08 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:24 PM PDT 24
Peak memory 201596 kb
Host smart-4ff430e3-b086-4a52-b0a9-335db8f2fd15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239751867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2239751867
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.822150513
Short name T862
Test name
Test status
Simulation time 1015977199 ps
CPU time 3.2 seconds
Started Jul 16 07:11:23 PM PDT 24
Finished Jul 16 07:12:50 PM PDT 24
Peak memory 209936 kb
Host smart-83469b2a-361b-4fde-b835-89d69b68c9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822150513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.822150513
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3275287300
Short name T346
Test name
Test status
Simulation time 4296113236 ps
CPU time 3.93 seconds
Started Jul 16 07:11:33 PM PDT 24
Finished Jul 16 07:13:05 PM PDT 24
Peak memory 201760 kb
Host smart-031700b5-8d6a-4914-9ca5-9cd2aceae229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275287300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3275287300
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.185783211
Short name T819
Test name
Test status
Simulation time 435879114 ps
CPU time 0.9 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:05 PM PDT 24
Peak memory 201416 kb
Host smart-87e009c1-7266-435a-bf1d-9438c1c63c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185783211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.185783211
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4124249015
Short name T805
Test name
Test status
Simulation time 494694343 ps
CPU time 1.72 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:08 PM PDT 24
Peak memory 201384 kb
Host smart-16797da0-6249-4904-a181-c2283f01e9e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124249015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4124249015
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3838199725
Short name T870
Test name
Test status
Simulation time 468979144 ps
CPU time 1.72 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 201408 kb
Host smart-582c505b-870a-4df8-9210-f99d4f8ce0f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838199725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3838199725
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.599186264
Short name T826
Test name
Test status
Simulation time 382738795 ps
CPU time 1.43 seconds
Started Jul 16 07:11:38 PM PDT 24
Finished Jul 16 07:13:08 PM PDT 24
Peak memory 201444 kb
Host smart-eee35a49-343d-4360-b970-84be25d22188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599186264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.599186264
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4126178854
Short name T807
Test name
Test status
Simulation time 291482313 ps
CPU time 1.29 seconds
Started Jul 16 07:11:51 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201420 kb
Host smart-5b778b3d-4901-4061-bd6a-fe6d33854ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126178854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4126178854
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.536277645
Short name T865
Test name
Test status
Simulation time 308167650 ps
CPU time 1.02 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201424 kb
Host smart-c35bc972-6237-4c2a-9a50-8c8d67abe811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536277645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.536277645
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1424266566
Short name T847
Test name
Test status
Simulation time 324521147 ps
CPU time 1.38 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 201436 kb
Host smart-4c90966b-cfd7-44ac-9f9a-174553243763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424266566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1424266566
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2947412702
Short name T912
Test name
Test status
Simulation time 544083381 ps
CPU time 0.96 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201448 kb
Host smart-480bceb2-b662-4a01-883d-e9a7cbfe6d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947412702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2947412702
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3945677170
Short name T889
Test name
Test status
Simulation time 288587389 ps
CPU time 1.28 seconds
Started Jul 16 07:11:38 PM PDT 24
Finished Jul 16 07:13:08 PM PDT 24
Peak memory 201420 kb
Host smart-dfdad744-f338-4117-b2a8-44a4e2b3da7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945677170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3945677170
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.285447760
Short name T837
Test name
Test status
Simulation time 428136753 ps
CPU time 0.99 seconds
Started Jul 16 07:11:49 PM PDT 24
Finished Jul 16 07:13:13 PM PDT 24
Peak memory 201432 kb
Host smart-832493f3-e395-4e1e-9f07-122767fe6456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285447760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.285447760
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3922895787
Short name T825
Test name
Test status
Simulation time 594262108 ps
CPU time 1.08 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:12:58 PM PDT 24
Peak memory 201536 kb
Host smart-ffabfedb-e05e-46c4-a293-37d79081daff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922895787 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3922895787
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3803668209
Short name T121
Test name
Test status
Simulation time 471892130 ps
CPU time 1.3 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:12:57 PM PDT 24
Peak memory 201476 kb
Host smart-2b7feeed-3e6d-45cd-89cf-39ada012fa47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803668209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3803668209
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.699179833
Short name T881
Test name
Test status
Simulation time 397688939 ps
CPU time 0.72 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:36 PM PDT 24
Peak memory 201384 kb
Host smart-8d79d5ab-0d19-4c5b-a935-06f5caf5093b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699179833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.699179833
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1126483052
Short name T896
Test name
Test status
Simulation time 2331773304 ps
CPU time 4.07 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:38 PM PDT 24
Peak memory 201612 kb
Host smart-911ce96f-0d58-4edf-b622-a56ed0a94d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126483052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1126483052
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.265688618
Short name T861
Test name
Test status
Simulation time 757260147 ps
CPU time 2.02 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:38 PM PDT 24
Peak memory 201756 kb
Host smart-3711d305-ff36-4f0b-a6af-33012fd4d88d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265688618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.265688618
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1424496800
Short name T73
Test name
Test status
Simulation time 8682373484 ps
CPU time 24.3 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:49 PM PDT 24
Peak memory 201800 kb
Host smart-9b74520b-5041-4bcd-b138-caf4b0cf3481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424496800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1424496800
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3894910327
Short name T894
Test name
Test status
Simulation time 415386996 ps
CPU time 0.99 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 201536 kb
Host smart-37eb4391-f753-46f2-bfcc-ed4e9c943c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894910327 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3894910327
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.868080638
Short name T879
Test name
Test status
Simulation time 513343184 ps
CPU time 1.3 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 201504 kb
Host smart-0034b937-de86-4a97-9b2a-95a9718cac10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868080638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.868080638
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1420853743
Short name T828
Test name
Test status
Simulation time 475252379 ps
CPU time 1.21 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:29 PM PDT 24
Peak memory 201484 kb
Host smart-6c2a3bf9-4618-41fd-bf88-5e8181844c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420853743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1420853743
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3082893878
Short name T59
Test name
Test status
Simulation time 5606223727 ps
CPU time 5.85 seconds
Started Jul 16 07:11:33 PM PDT 24
Finished Jul 16 07:13:04 PM PDT 24
Peak memory 201652 kb
Host smart-4e7f3e39-2c72-4d84-b89d-07d0738b2e0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082893878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3082893878
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3775003723
Short name T867
Test name
Test status
Simulation time 621747766 ps
CPU time 2.67 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:30 PM PDT 24
Peak memory 218084 kb
Host smart-bd1fb6ad-7988-42f6-8301-1007f045fbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775003723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3775003723
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3846723733
Short name T67
Test name
Test status
Simulation time 5754810688 ps
CPU time 2.13 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:37 PM PDT 24
Peak memory 201844 kb
Host smart-f03677e0-ab8c-46a7-9a85-bfad812a9fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846723733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3846723733
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3615417469
Short name T812
Test name
Test status
Simulation time 539275612 ps
CPU time 1.51 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201540 kb
Host smart-c108687a-7d4b-4384-ab51-fc4271907371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615417469 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3615417469
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1935420756
Short name T911
Test name
Test status
Simulation time 458664005 ps
CPU time 1.74 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:19 PM PDT 24
Peak memory 201504 kb
Host smart-364f200a-b9e6-4767-9a7e-30150901d0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935420756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1935420756
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.743504704
Short name T818
Test name
Test status
Simulation time 450513823 ps
CPU time 1.15 seconds
Started Jul 16 07:11:34 PM PDT 24
Finished Jul 16 07:13:03 PM PDT 24
Peak memory 201432 kb
Host smart-c2a2a0a2-5b1b-4011-8ecb-fbce718158f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743504704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.743504704
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1714526092
Short name T853
Test name
Test status
Simulation time 2196996248 ps
CPU time 2.76 seconds
Started Jul 16 07:11:32 PM PDT 24
Finished Jul 16 07:13:00 PM PDT 24
Peak memory 201476 kb
Host smart-1eb5b6dc-5fb2-4134-b712-e32d43eec64e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714526092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1714526092
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.414768283
Short name T71
Test name
Test status
Simulation time 414048053 ps
CPU time 1.35 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201816 kb
Host smart-59453a32-59e8-464a-a028-a3ef4b305b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414768283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.414768283
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.304905449
Short name T822
Test name
Test status
Simulation time 4299255771 ps
CPU time 3.04 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:01 PM PDT 24
Peak memory 201808 kb
Host smart-d7d18319-9d29-4946-aeaf-2c7cf8b47b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304905449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.304905449
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2230061202
Short name T831
Test name
Test status
Simulation time 470916236 ps
CPU time 1.16 seconds
Started Jul 16 07:11:33 PM PDT 24
Finished Jul 16 07:13:02 PM PDT 24
Peak memory 201532 kb
Host smart-52110ca6-06dc-46b8-9420-d29d2dc004b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230061202 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2230061202
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3714105991
Short name T122
Test name
Test status
Simulation time 377405525 ps
CPU time 0.86 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:12:58 PM PDT 24
Peak memory 201472 kb
Host smart-4e4416cb-cc08-42a5-a3c1-50c06a265785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714105991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3714105991
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1847572137
Short name T842
Test name
Test status
Simulation time 288308717 ps
CPU time 1.03 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:13:06 PM PDT 24
Peak memory 201388 kb
Host smart-7588c743-b0e7-465a-9f85-4ddac2937e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847572137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1847572137
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1948042983
Short name T844
Test name
Test status
Simulation time 4305793730 ps
CPU time 14.12 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:20 PM PDT 24
Peak memory 201812 kb
Host smart-e99338d2-3ed1-4173-b1eb-df311849dce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948042983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1948042983
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2342685930
Short name T860
Test name
Test status
Simulation time 747037389 ps
CPU time 2.68 seconds
Started Jul 16 07:11:34 PM PDT 24
Finished Jul 16 07:13:04 PM PDT 24
Peak memory 201796 kb
Host smart-2636322f-9568-4164-a9f1-efb78073efdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342685930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2342685930
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2596061784
Short name T838
Test name
Test status
Simulation time 816467433 ps
CPU time 0.98 seconds
Started Jul 16 07:11:31 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201488 kb
Host smart-70d6e65f-eb76-425e-93bb-08a1b05c3a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596061784 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2596061784
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.454178054
Short name T858
Test name
Test status
Simulation time 328730872 ps
CPU time 1.55 seconds
Started Jul 16 07:11:29 PM PDT 24
Finished Jul 16 07:12:59 PM PDT 24
Peak memory 201496 kb
Host smart-893c1031-f8ac-4d8d-bfca-7676464d0a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454178054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.454178054
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.302646867
Short name T813
Test name
Test status
Simulation time 368489952 ps
CPU time 0.84 seconds
Started Jul 16 07:11:34 PM PDT 24
Finished Jul 16 07:13:02 PM PDT 24
Peak memory 201432 kb
Host smart-f2bc2f17-c4cd-4565-8165-7a995cc2eea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302646867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.302646867
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1725970160
Short name T890
Test name
Test status
Simulation time 2391521800 ps
CPU time 6.18 seconds
Started Jul 16 07:11:28 PM PDT 24
Finished Jul 16 07:13:03 PM PDT 24
Peak memory 201608 kb
Host smart-798ef8e7-4245-4127-a3cc-7575b84a496f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725970160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1725970160
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2734780435
Short name T855
Test name
Test status
Simulation time 4481648174 ps
CPU time 6.31 seconds
Started Jul 16 07:11:30 PM PDT 24
Finished Jul 16 07:13:04 PM PDT 24
Peak memory 201772 kb
Host smart-1321bf69-36be-4cf6-9cd3-30768a433c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734780435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2734780435
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2987728977
Short name T697
Test name
Test status
Simulation time 509949508 ps
CPU time 0.79 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:18:08 PM PDT 24
Peak memory 201592 kb
Host smart-adcaa740-4443-4f23-8288-20ca78747515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987728977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2987728977
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2747205934
Short name T668
Test name
Test status
Simulation time 161228280690 ps
CPU time 85.86 seconds
Started Jul 16 07:16:14 PM PDT 24
Finished Jul 16 07:18:26 PM PDT 24
Peak memory 201876 kb
Host smart-358b6551-67eb-485a-b24b-63ec7a148cd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747205934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2747205934
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1541361579
Short name T255
Test name
Test status
Simulation time 270491505305 ps
CPU time 171.5 seconds
Started Jul 16 07:16:13 PM PDT 24
Finished Jul 16 07:19:51 PM PDT 24
Peak memory 201868 kb
Host smart-82ecea9f-0433-42d4-8f94-8c5080b617bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541361579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1541361579
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2869886309
Short name T309
Test name
Test status
Simulation time 489536053361 ps
CPU time 573.72 seconds
Started Jul 16 07:16:14 PM PDT 24
Finished Jul 16 07:26:33 PM PDT 24
Peak memory 201952 kb
Host smart-61af15ce-e464-42ff-b60c-cbd354e504aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869886309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2869886309
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.432449920
Short name T423
Test name
Test status
Simulation time 328344740338 ps
CPU time 759.76 seconds
Started Jul 16 07:16:04 PM PDT 24
Finished Jul 16 07:29:35 PM PDT 24
Peak memory 201916 kb
Host smart-c98f4959-67d2-406d-8a85-52ce5ae3a5ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432449920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.432449920
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3052763011
Short name T153
Test name
Test status
Simulation time 486135138589 ps
CPU time 284.94 seconds
Started Jul 16 07:16:15 PM PDT 24
Finished Jul 16 07:21:45 PM PDT 24
Peak memory 201912 kb
Host smart-eec5f84f-9ce0-4ff9-b50f-ce198b327b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052763011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3052763011
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3535284806
Short name T791
Test name
Test status
Simulation time 495577874091 ps
CPU time 1076.42 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:34:51 PM PDT 24
Peak memory 201916 kb
Host smart-79f08714-8d9a-450a-99db-c2529e49d75e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535284806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3535284806
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.66676320
Short name T467
Test name
Test status
Simulation time 398884449241 ps
CPU time 492.25 seconds
Started Jul 16 07:16:03 PM PDT 24
Finished Jul 16 07:25:07 PM PDT 24
Peak memory 201896 kb
Host smart-dc75809b-0ea7-45a2-b090-9b77d20ca44d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66676320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.66676320
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2121487215
Short name T220
Test name
Test status
Simulation time 95036377304 ps
CPU time 294.83 seconds
Started Jul 16 07:16:14 PM PDT 24
Finished Jul 16 07:21:55 PM PDT 24
Peak memory 202176 kb
Host smart-638d15e3-c0e3-4cfc-ace4-ef6ebaed8861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121487215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2121487215
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2813726852
Short name T390
Test name
Test status
Simulation time 42045863172 ps
CPU time 39.83 seconds
Started Jul 16 07:16:13 PM PDT 24
Finished Jul 16 07:17:39 PM PDT 24
Peak memory 201688 kb
Host smart-9c27d8c3-6cd1-497a-88a2-10633622fa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813726852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2813726852
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2777423623
Short name T667
Test name
Test status
Simulation time 3653104698 ps
CPU time 8.23 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:11 PM PDT 24
Peak memory 201732 kb
Host smart-4714de49-8060-46bd-932a-c7d9256bee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777423623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2777423623
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2961382578
Short name T109
Test name
Test status
Simulation time 5970792389 ps
CPU time 8.36 seconds
Started Jul 16 07:16:19 PM PDT 24
Finished Jul 16 07:17:11 PM PDT 24
Peak memory 201708 kb
Host smart-c1879bda-ee95-4b35-acc9-bbe4189bfced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961382578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2961382578
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1531146487
Short name T203
Test name
Test status
Simulation time 406226048936 ps
CPU time 564.98 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 210360 kb
Host smart-febf6ae8-471e-4f57-bde6-c08459e5c797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531146487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1531146487
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.35926463
Short name T608
Test name
Test status
Simulation time 414382405 ps
CPU time 0.84 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:07 PM PDT 24
Peak memory 201656 kb
Host smart-31629c61-3c05-4694-b132-60c110baaa98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35926463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.35926463
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.846685172
Short name T776
Test name
Test status
Simulation time 168058803274 ps
CPU time 377.14 seconds
Started Jul 16 07:16:21 PM PDT 24
Finished Jul 16 07:23:20 PM PDT 24
Peak memory 201816 kb
Host smart-2d8f556f-6412-4e97-8ddd-9d3a4915801f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846685172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.846685172
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.643517586
Short name T540
Test name
Test status
Simulation time 163515564623 ps
CPU time 57.72 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:18:04 PM PDT 24
Peak memory 201916 kb
Host smart-21224259-502d-4359-b94b-d8b478170df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643517586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.643517586
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3685905520
Short name T554
Test name
Test status
Simulation time 166634732743 ps
CPU time 41.19 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:47 PM PDT 24
Peak memory 201916 kb
Host smart-663e1153-b8a0-48ae-b346-be5872a91db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685905520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3685905520
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1807308707
Short name T546
Test name
Test status
Simulation time 163372535029 ps
CPU time 62.89 seconds
Started Jul 16 07:16:16 PM PDT 24
Finished Jul 16 07:18:03 PM PDT 24
Peak memory 201884 kb
Host smart-62d70b5c-b849-44d9-9f11-e9ec2d02f955
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807308707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1807308707
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.380410418
Short name T227
Test name
Test status
Simulation time 489298179301 ps
CPU time 607.56 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:27:13 PM PDT 24
Peak memory 201992 kb
Host smart-cdebe969-fd9f-4a06-a26f-4c867bd4e504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380410418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.380410418
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3539643168
Short name T623
Test name
Test status
Simulation time 325621386463 ps
CPU time 359.29 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:23:05 PM PDT 24
Peak memory 201928 kb
Host smart-d3421bd3-ffab-4f21-b236-d28e2a76f5d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539643168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3539643168
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3511269853
Short name T591
Test name
Test status
Simulation time 592072774401 ps
CPU time 1085.18 seconds
Started Jul 16 07:16:22 PM PDT 24
Finished Jul 16 07:35:09 PM PDT 24
Peak memory 201960 kb
Host smart-cef94bca-6055-476a-820b-ec4609ab03dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511269853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3511269853
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1781075828
Short name T420
Test name
Test status
Simulation time 84755310016 ps
CPU time 337.71 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:22:44 PM PDT 24
Peak memory 202276 kb
Host smart-f873c37b-88df-4294-aefa-687b4010d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781075828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1781075828
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.692094707
Short name T520
Test name
Test status
Simulation time 42727908356 ps
CPU time 97.65 seconds
Started Jul 16 07:16:21 PM PDT 24
Finished Jul 16 07:18:41 PM PDT 24
Peak memory 201724 kb
Host smart-3f9725a5-1849-4894-8110-97544ba13d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692094707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.692094707
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.787484313
Short name T485
Test name
Test status
Simulation time 2789758438 ps
CPU time 7.71 seconds
Started Jul 16 07:16:22 PM PDT 24
Finished Jul 16 07:17:12 PM PDT 24
Peak memory 201656 kb
Host smart-54a2bf9d-f103-4a41-9eeb-f34e848ee347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787484313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.787484313
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2544040531
Short name T68
Test name
Test status
Simulation time 8145758994 ps
CPU time 18.24 seconds
Started Jul 16 07:16:29 PM PDT 24
Finished Jul 16 07:17:25 PM PDT 24
Peak memory 217116 kb
Host smart-c0eda930-6c81-454a-9aa5-d32def245c97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544040531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2544040531
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3537720173
Short name T714
Test name
Test status
Simulation time 5976650316 ps
CPU time 14.14 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:20 PM PDT 24
Peak memory 201648 kb
Host smart-f2f27fc2-61b9-43e5-9634-2f2de2703fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537720173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3537720173
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3896187481
Short name T12
Test name
Test status
Simulation time 227462865065 ps
CPU time 523.14 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:25:49 PM PDT 24
Peak memory 201964 kb
Host smart-bbb172a9-f41e-4123-b88a-22b4b40e8a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896187481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3896187481
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1492429300
Short name T508
Test name
Test status
Simulation time 33571760744 ps
CPU time 43 seconds
Started Jul 16 07:16:17 PM PDT 24
Finished Jul 16 07:17:44 PM PDT 24
Peak memory 202040 kb
Host smart-81abaaa5-8d1b-47d6-80ae-4bf0cfbcdaf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492429300 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1492429300
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1496634515
Short name T450
Test name
Test status
Simulation time 489529750 ps
CPU time 0.95 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:19 PM PDT 24
Peak memory 201600 kb
Host smart-f01e4ac7-352a-4eff-b229-dff70d08c8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496634515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1496634515
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4101468751
Short name T722
Test name
Test status
Simulation time 331545832354 ps
CPU time 96.29 seconds
Started Jul 16 07:17:08 PM PDT 24
Finished Jul 16 07:18:54 PM PDT 24
Peak memory 201888 kb
Host smart-31c70ff3-2de7-460e-b292-72db96213dba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101468751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4101468751
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4201888122
Short name T557
Test name
Test status
Simulation time 498780494560 ps
CPU time 301.17 seconds
Started Jul 16 07:17:04 PM PDT 24
Finished Jul 16 07:22:18 PM PDT 24
Peak memory 201836 kb
Host smart-27220526-4aac-4ba2-acb2-ae2229279fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201888122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4201888122
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2906726074
Short name T476
Test name
Test status
Simulation time 174675245799 ps
CPU time 373.43 seconds
Started Jul 16 07:17:04 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 201892 kb
Host smart-6bd008a5-bffa-4936-87ec-1594eadfe73e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906726074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2906726074
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.960675602
Short name T628
Test name
Test status
Simulation time 160993843473 ps
CPU time 83.95 seconds
Started Jul 16 07:16:50 PM PDT 24
Finished Jul 16 07:18:36 PM PDT 24
Peak memory 201912 kb
Host smart-8dff96f0-0e06-43d8-8a56-ba62e64c36fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960675602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.960675602
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1837365428
Short name T11
Test name
Test status
Simulation time 327114678064 ps
CPU time 306.99 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:22:21 PM PDT 24
Peak memory 201876 kb
Host smart-51c6b6f2-11df-4d97-aa52-15aa9f968c0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837365428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1837365428
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2581009512
Short name T157
Test name
Test status
Simulation time 386355682676 ps
CPU time 897.56 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:32:14 PM PDT 24
Peak memory 201864 kb
Host smart-94242ef8-e089-4864-a925-569b6cf5ae43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581009512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2581009512
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3853658393
Short name T85
Test name
Test status
Simulation time 389447355416 ps
CPU time 882.99 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:31:59 PM PDT 24
Peak memory 201836 kb
Host smart-dc5bb471-2a88-444c-837c-6c0f55f42729
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853658393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3853658393
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1932414921
Short name T655
Test name
Test status
Simulation time 105555056135 ps
CPU time 576.97 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:26:55 PM PDT 24
Peak memory 202208 kb
Host smart-e9033972-83ad-4b9c-9aea-6f29e1f7155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932414921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1932414921
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1377797089
Short name T521
Test name
Test status
Simulation time 37747614791 ps
CPU time 87.52 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:18:45 PM PDT 24
Peak memory 201688 kb
Host smart-840ba066-e6cc-4bf9-80c2-86349891a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377797089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1377797089
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.751718938
Short name T585
Test name
Test status
Simulation time 3618216971 ps
CPU time 7.63 seconds
Started Jul 16 07:17:12 PM PDT 24
Finished Jul 16 07:17:27 PM PDT 24
Peak memory 201716 kb
Host smart-91bfb622-8e04-4412-b53a-d6df3da66412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751718938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.751718938
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1096975988
Short name T734
Test name
Test status
Simulation time 5920811648 ps
CPU time 14.65 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:17:29 PM PDT 24
Peak memory 201712 kb
Host smart-ae4945ec-ccb9-4424-b933-a5f74b7b783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096975988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1096975988
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2717320632
Short name T563
Test name
Test status
Simulation time 341229231 ps
CPU time 0.82 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:17:17 PM PDT 24
Peak memory 201648 kb
Host smart-946b0c57-66ef-48f1-912e-3aff49f2ed89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717320632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2717320632
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.707214120
Short name T83
Test name
Test status
Simulation time 528480499011 ps
CPU time 221 seconds
Started Jul 16 07:17:10 PM PDT 24
Finished Jul 16 07:20:59 PM PDT 24
Peak memory 201904 kb
Host smart-f7c30e62-7ac4-4d72-adbd-3dcb71037dd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707214120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.707214120
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2763734684
Short name T326
Test name
Test status
Simulation time 246014559881 ps
CPU time 545.94 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:26:24 PM PDT 24
Peak memory 201836 kb
Host smart-1e073519-f2b0-438e-bc18-96ca9e8acc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763734684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2763734684
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.8124437
Short name T205
Test name
Test status
Simulation time 333574012586 ps
CPU time 184.24 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:20:21 PM PDT 24
Peak memory 201920 kb
Host smart-c6151bbb-5d27-4fe4-82f9-dd84efb8b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8124437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.8124437
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1625806932
Short name T468
Test name
Test status
Simulation time 329510183157 ps
CPU time 115.98 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:19:13 PM PDT 24
Peak memory 201916 kb
Host smart-e969c6e6-14e6-4043-9bbd-d46398140a03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625806932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1625806932
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.110940167
Short name T505
Test name
Test status
Simulation time 330821048145 ps
CPU time 678.92 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:28:36 PM PDT 24
Peak memory 201972 kb
Host smart-e200f9c5-c212-41ea-bfa2-7f1c4e16ad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110940167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.110940167
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1439893241
Short name T738
Test name
Test status
Simulation time 330805389641 ps
CPU time 386.79 seconds
Started Jul 16 07:17:12 PM PDT 24
Finished Jul 16 07:23:46 PM PDT 24
Peak memory 201880 kb
Host smart-de9f7c01-eb3d-4027-b56b-05711ce51389
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439893241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1439893241
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3740296649
Short name T457
Test name
Test status
Simulation time 404414481577 ps
CPU time 460.05 seconds
Started Jul 16 07:17:10 PM PDT 24
Finished Jul 16 07:24:58 PM PDT 24
Peak memory 201920 kb
Host smart-32977821-4cd2-4f78-bd8c-ab21989c1eed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740296649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3740296649
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1598888818
Short name T443
Test name
Test status
Simulation time 608467460843 ps
CPU time 1269.03 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:38:26 PM PDT 24
Peak memory 201884 kb
Host smart-588684b5-5e5d-4e32-b3f4-f48cfeb3b6fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598888818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1598888818
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3388258911
Short name T217
Test name
Test status
Simulation time 88473617400 ps
CPU time 295.59 seconds
Started Jul 16 07:17:10 PM PDT 24
Finished Jul 16 07:22:14 PM PDT 24
Peak memory 202208 kb
Host smart-2219f5e1-ea6b-4281-99ec-b5662347c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388258911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3388258911
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.803443544
Short name T550
Test name
Test status
Simulation time 43627632637 ps
CPU time 27.15 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:17:44 PM PDT 24
Peak memory 201692 kb
Host smart-bd9c7bdf-d419-4371-823f-61ef14bd485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803443544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.803443544
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2028259501
Short name T578
Test name
Test status
Simulation time 4389660176 ps
CPU time 5.42 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:23 PM PDT 24
Peak memory 201132 kb
Host smart-04b12f4e-5b30-4edd-816e-66cca94c4595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028259501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2028259501
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2017285673
Short name T773
Test name
Test status
Simulation time 5761866505 ps
CPU time 4.05 seconds
Started Jul 16 07:17:03 PM PDT 24
Finished Jul 16 07:17:20 PM PDT 24
Peak memory 201652 kb
Host smart-8705b54e-3723-4fbb-ac8b-d6b88b8f3b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017285673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2017285673
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3193751917
Short name T288
Test name
Test status
Simulation time 147044681525 ps
CPU time 223.71 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:21:00 PM PDT 24
Peak memory 211568 kb
Host smart-e58c1d41-92a6-4b09-bbdb-c69e10c1c9e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193751917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3193751917
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3602715749
Short name T383
Test name
Test status
Simulation time 525871918 ps
CPU time 1.84 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:20 PM PDT 24
Peak memory 201600 kb
Host smart-6e7250b6-ecb9-4866-9e8b-70356ef64c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602715749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3602715749
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.4071956845
Short name T268
Test name
Test status
Simulation time 499550779521 ps
CPU time 273.93 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:21:52 PM PDT 24
Peak memory 201880 kb
Host smart-9d3d6155-c200-45ce-a861-295e18bd8214
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071956845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.4071956845
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3805131436
Short name T592
Test name
Test status
Simulation time 524321484349 ps
CPU time 1240.96 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:37:58 PM PDT 24
Peak memory 202000 kb
Host smart-0790ca3f-76cf-45ea-9c0c-44900538bce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805131436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3805131436
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.4113733593
Short name T324
Test name
Test status
Simulation time 164217902257 ps
CPU time 99.6 seconds
Started Jul 16 07:17:09 PM PDT 24
Finished Jul 16 07:18:58 PM PDT 24
Peak memory 201856 kb
Host smart-3b5fcec9-9274-4188-91cd-e82e506aab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113733593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.4113733593
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.101471613
Short name T593
Test name
Test status
Simulation time 338788290309 ps
CPU time 210.49 seconds
Started Jul 16 07:17:08 PM PDT 24
Finished Jul 16 07:20:48 PM PDT 24
Peak memory 201952 kb
Host smart-903e229f-213f-4ff7-8014-3fda5bb139b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=101471613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.101471613
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4104391794
Short name T188
Test name
Test status
Simulation time 322297714916 ps
CPU time 191.95 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:20:29 PM PDT 24
Peak memory 201964 kb
Host smart-93e130cf-cf06-4abc-918f-370f59eb25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104391794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4104391794
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3040784
Short name T777
Test name
Test status
Simulation time 163250397320 ps
CPU time 337.1 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:22:54 PM PDT 24
Peak memory 201964 kb
Host smart-0647d33c-07a6-4b10-8c4a-9d69b6fd3e14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.3040784
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.4185605193
Short name T743
Test name
Test status
Simulation time 537602145163 ps
CPU time 1152.85 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:36:30 PM PDT 24
Peak memory 201908 kb
Host smart-cb112145-7bef-4a1c-bb45-716b3f01a0df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185605193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.4185605193
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2697289528
Short name T272
Test name
Test status
Simulation time 204413127417 ps
CPU time 91.06 seconds
Started Jul 16 07:17:05 PM PDT 24
Finished Jul 16 07:18:48 PM PDT 24
Peak memory 201900 kb
Host smart-39fe17b3-0c63-44eb-afb9-82ef6d468dfa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697289528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2697289528
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3335407608
Short name T720
Test name
Test status
Simulation time 115563047903 ps
CPU time 586.04 seconds
Started Jul 16 07:17:10 PM PDT 24
Finished Jul 16 07:27:05 PM PDT 24
Peak memory 202288 kb
Host smart-b23e5fb7-0e54-4cbd-aaaf-74470828de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335407608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3335407608
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.354552872
Short name T393
Test name
Test status
Simulation time 32173009359 ps
CPU time 18.26 seconds
Started Jul 16 07:17:09 PM PDT 24
Finished Jul 16 07:17:37 PM PDT 24
Peak memory 201720 kb
Host smart-e653d801-e228-4f7f-9973-56ac61d2d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354552872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.354552872
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.694162531
Short name T455
Test name
Test status
Simulation time 4944553440 ps
CPU time 7.58 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:25 PM PDT 24
Peak memory 201308 kb
Host smart-8280438f-7a95-4e29-a3d7-7592fa430c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694162531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.694162531
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3209722372
Short name T760
Test name
Test status
Simulation time 5804216484 ps
CPU time 4.22 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:17:21 PM PDT 24
Peak memory 201684 kb
Host smart-2935917c-28ed-4e38-9def-132bda3ebc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209722372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3209722372
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.769994941
Short name T745
Test name
Test status
Simulation time 75969689837 ps
CPU time 15.77 seconds
Started Jul 16 07:17:10 PM PDT 24
Finished Jul 16 07:17:34 PM PDT 24
Peak memory 201964 kb
Host smart-f79dce59-885c-481e-923b-bcfc36d4665e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769994941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
769994941
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.48341405
Short name T586
Test name
Test status
Simulation time 390979022982 ps
CPU time 153.72 seconds
Started Jul 16 07:17:10 PM PDT 24
Finished Jul 16 07:19:52 PM PDT 24
Peak memory 210756 kb
Host smart-bc832998-84dc-4339-b9e7-50d7859a7ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48341405 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.48341405
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3777328313
Short name T498
Test name
Test status
Simulation time 359545000 ps
CPU time 1.43 seconds
Started Jul 16 07:17:20 PM PDT 24
Finished Jul 16 07:17:24 PM PDT 24
Peak memory 201588 kb
Host smart-a260ccd2-aa0d-42e0-95a7-e50608d21474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777328313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3777328313
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.608665549
Short name T185
Test name
Test status
Simulation time 159539737436 ps
CPU time 95.55 seconds
Started Jul 16 07:17:06 PM PDT 24
Finished Jul 16 07:18:53 PM PDT 24
Peak memory 201972 kb
Host smart-4dc9cfe0-643f-41bf-ad72-1600f0fba6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608665549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.608665549
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2114790228
Short name T465
Test name
Test status
Simulation time 161002524743 ps
CPU time 104 seconds
Started Jul 16 07:17:08 PM PDT 24
Finished Jul 16 07:19:02 PM PDT 24
Peak memory 201832 kb
Host smart-fef86d22-869e-4151-9a5b-ddc9d6a6296f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114790228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2114790228
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3696530300
Short name T644
Test name
Test status
Simulation time 492715648231 ps
CPU time 536 seconds
Started Jul 16 07:17:09 PM PDT 24
Finished Jul 16 07:26:14 PM PDT 24
Peak memory 201920 kb
Host smart-76b252f5-533a-4f2c-85dd-b61cb61521f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696530300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3696530300
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3825057623
Short name T165
Test name
Test status
Simulation time 166349690870 ps
CPU time 39.52 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:57 PM PDT 24
Peak memory 201948 kb
Host smart-a87f1c10-d84a-455e-9724-4a1e469e67b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825057623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3825057623
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4228508
Short name T728
Test name
Test status
Simulation time 168424978952 ps
CPU time 400.22 seconds
Started Jul 16 07:17:08 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 201880 kb
Host smart-b472026d-c03a-4749-b8b7-d05b09f83c30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wa
keup.4228508
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3642430473
Short name T726
Test name
Test status
Simulation time 419979080038 ps
CPU time 493.02 seconds
Started Jul 16 07:17:09 PM PDT 24
Finished Jul 16 07:25:31 PM PDT 24
Peak memory 201828 kb
Host smart-ff857353-971d-436d-9e60-eb97772a8e2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642430473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3642430473
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3275449821
Short name T774
Test name
Test status
Simulation time 80057079188 ps
CPU time 310.08 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:22:34 PM PDT 24
Peak memory 202212 kb
Host smart-5f493fc6-793a-4bbb-bf00-117e88eb9594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275449821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3275449821
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.398662354
Short name T539
Test name
Test status
Simulation time 32547357263 ps
CPU time 20.03 seconds
Started Jul 16 07:17:09 PM PDT 24
Finished Jul 16 07:17:38 PM PDT 24
Peak memory 201644 kb
Host smart-61137e3b-4817-4ed1-8110-1fc19c7a5550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398662354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.398662354
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1119634567
Short name T762
Test name
Test status
Simulation time 4063074170 ps
CPU time 2.16 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:19 PM PDT 24
Peak memory 201768 kb
Host smart-77da1a67-1c57-44b5-be6a-48ab9c4eba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119634567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1119634567
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2313819015
Short name T630
Test name
Test status
Simulation time 5755002249 ps
CPU time 3.86 seconds
Started Jul 16 07:17:07 PM PDT 24
Finished Jul 16 07:17:21 PM PDT 24
Peak memory 201704 kb
Host smart-1ca4dcb0-d451-4608-8097-4654af58b354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313819015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2313819015
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3732351601
Short name T677
Test name
Test status
Simulation time 61389763908 ps
CPU time 158.45 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:20:19 PM PDT 24
Peak memory 210464 kb
Host smart-18227674-297d-4f47-978c-09b5dd8b99ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732351601 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3732351601
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2859880343
Short name T565
Test name
Test status
Simulation time 335374544 ps
CPU time 0.77 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:17:22 PM PDT 24
Peak memory 201576 kb
Host smart-00c8e82c-9a6c-438e-84cf-3857d7a5442b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859880343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2859880343
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2322235570
Short name T421
Test name
Test status
Simulation time 167052952116 ps
CPU time 349.75 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:23:11 PM PDT 24
Peak memory 201932 kb
Host smart-beef0a8e-2508-4656-9f56-e80389e25495
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322235570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2322235570
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2318793363
Short name T600
Test name
Test status
Simulation time 164822016510 ps
CPU time 248.65 seconds
Started Jul 16 07:17:21 PM PDT 24
Finished Jul 16 07:21:32 PM PDT 24
Peak memory 201892 kb
Host smart-6c005817-63c0-408d-89ef-fb5ea29c1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318793363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2318793363
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2295125226
Short name T270
Test name
Test status
Simulation time 491417626194 ps
CPU time 860.3 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:31:41 PM PDT 24
Peak memory 201968 kb
Host smart-4f019bc0-e079-4326-8f45-6fde8f0bbeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295125226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2295125226
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2070539536
Short name T636
Test name
Test status
Simulation time 497971194457 ps
CPU time 601.84 seconds
Started Jul 16 07:17:17 PM PDT 24
Finished Jul 16 07:27:22 PM PDT 24
Peak memory 201840 kb
Host smart-9d5a982b-87bc-4322-90c8-82d59c640999
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070539536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2070539536
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1926668558
Short name T654
Test name
Test status
Simulation time 159715951134 ps
CPU time 331.66 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:22:56 PM PDT 24
Peak memory 201868 kb
Host smart-a764e1ac-abfd-419d-bc50-42324954bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926668558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1926668558
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.248397335
Short name T426
Test name
Test status
Simulation time 173387209817 ps
CPU time 192.42 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:20:37 PM PDT 24
Peak memory 201876 kb
Host smart-f95f8997-2fea-4f4a-939f-aadf6c9519bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=248397335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.248397335
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3272556303
Short name T265
Test name
Test status
Simulation time 544946159023 ps
CPU time 258.35 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:21:40 PM PDT 24
Peak memory 201924 kb
Host smart-e9056de6-cef0-4017-8ffc-bf96ded2a6c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272556303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3272556303
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.65067813
Short name T786
Test name
Test status
Simulation time 411408261202 ps
CPU time 917.07 seconds
Started Jul 16 07:17:23 PM PDT 24
Finished Jul 16 07:32:42 PM PDT 24
Peak memory 201764 kb
Host smart-95fe1b75-c6a7-478c-aed9-17180d7a2311
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65067813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.a
dc_ctrl_filters_wakeup_fixed.65067813
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2681555934
Short name T527
Test name
Test status
Simulation time 88856147115 ps
CPU time 272.32 seconds
Started Jul 16 07:17:20 PM PDT 24
Finished Jul 16 07:21:55 PM PDT 24
Peak memory 202276 kb
Host smart-36240a92-90e0-450e-b37f-eb9a83eee1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681555934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2681555934
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.170625492
Short name T685
Test name
Test status
Simulation time 40603548015 ps
CPU time 90.64 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:18:55 PM PDT 24
Peak memory 201700 kb
Host smart-93c42a88-9c38-4d4d-b7ef-2947de9c5f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170625492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.170625492
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.559444494
Short name T460
Test name
Test status
Simulation time 5457337386 ps
CPU time 12.97 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:18:13 PM PDT 24
Peak memory 201628 kb
Host smart-df52b670-1614-4a67-8f57-e49b36a1e380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559444494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.559444494
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3023569292
Short name T482
Test name
Test status
Simulation time 5681434200 ps
CPU time 7.41 seconds
Started Jul 16 07:17:21 PM PDT 24
Finished Jul 16 07:17:31 PM PDT 24
Peak memory 201680 kb
Host smart-81700645-eca1-4efb-8812-d717536cf4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023569292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3023569292
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2377253935
Short name T280
Test name
Test status
Simulation time 174778521636 ps
CPU time 199.68 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:20:41 PM PDT 24
Peak memory 201880 kb
Host smart-d67f265d-e29f-447f-b978-8283a92c73fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377253935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2377253935
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3617542468
Short name T711
Test name
Test status
Simulation time 43873314045 ps
CPU time 60.93 seconds
Started Jul 16 07:17:20 PM PDT 24
Finished Jul 16 07:18:24 PM PDT 24
Peak memory 210596 kb
Host smart-1be83bce-0a4b-4a14-9883-082efd1c7197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617542468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3617542468
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2204647113
Short name T529
Test name
Test status
Simulation time 312478157 ps
CPU time 0.94 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:17:22 PM PDT 24
Peak memory 201636 kb
Host smart-52d93fa2-491c-4d0a-a478-4cfa5c47c4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204647113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2204647113
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2909321176
Short name T610
Test name
Test status
Simulation time 328561374327 ps
CPU time 697.46 seconds
Started Jul 16 07:17:20 PM PDT 24
Finished Jul 16 07:29:00 PM PDT 24
Peak memory 201844 kb
Host smart-86258b86-7d34-49f0-ab3f-0704fe8ad586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909321176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2909321176
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2685222933
Short name T699
Test name
Test status
Simulation time 165738315507 ps
CPU time 56.66 seconds
Started Jul 16 07:17:23 PM PDT 24
Finished Jul 16 07:18:22 PM PDT 24
Peak memory 202080 kb
Host smart-dc3e0641-75f6-4a09-8052-18bc19cfbca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685222933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2685222933
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1184961933
Short name T568
Test name
Test status
Simulation time 165136470427 ps
CPU time 96.83 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:19:02 PM PDT 24
Peak memory 201876 kb
Host smart-6e59cad1-a7c2-4ab9-9adb-ab300b038e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184961933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1184961933
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2971366707
Short name T650
Test name
Test status
Simulation time 502529951300 ps
CPU time 1120.92 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:36:03 PM PDT 24
Peak memory 201892 kb
Host smart-a106edf1-b12b-4321-8520-9539effc187d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971366707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2971366707
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4122477382
Short name T276
Test name
Test status
Simulation time 163361615343 ps
CPU time 349.92 seconds
Started Jul 16 07:17:17 PM PDT 24
Finished Jul 16 07:23:10 PM PDT 24
Peak memory 201944 kb
Host smart-75a445ff-2466-4b6b-b387-0d07270d7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122477382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4122477382
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4081014568
Short name T358
Test name
Test status
Simulation time 329810777897 ps
CPU time 394.69 seconds
Started Jul 16 07:17:24 PM PDT 24
Finished Jul 16 07:24:00 PM PDT 24
Peak memory 201800 kb
Host smart-03128b4e-6536-47df-8ee6-6aa8ded41c25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081014568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4081014568
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2492054359
Short name T269
Test name
Test status
Simulation time 243202783255 ps
CPU time 266.25 seconds
Started Jul 16 07:17:23 PM PDT 24
Finished Jul 16 07:21:51 PM PDT 24
Peak memory 202084 kb
Host smart-cd0e5a05-9223-4c3f-bd21-31a4340a81a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492054359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2492054359
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3127070455
Short name T533
Test name
Test status
Simulation time 193294144451 ps
CPU time 109.37 seconds
Started Jul 16 07:17:20 PM PDT 24
Finished Jul 16 07:19:12 PM PDT 24
Peak memory 201968 kb
Host smart-7282cf2f-2071-41e8-9fd0-4ec46cd37a96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127070455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3127070455
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2519512598
Short name T7
Test name
Test status
Simulation time 122669719502 ps
CPU time 491.19 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:25:36 PM PDT 24
Peak memory 202148 kb
Host smart-24c3711b-8717-4a52-9f0b-b65652227adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519512598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2519512598
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.538193545
Short name T57
Test name
Test status
Simulation time 44168810297 ps
CPU time 102.25 seconds
Started Jul 16 07:17:23 PM PDT 24
Finished Jul 16 07:19:07 PM PDT 24
Peak memory 201892 kb
Host smart-6b67254a-6fcc-47c9-af34-5c4b72f65477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538193545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.538193545
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.279887584
Short name T139
Test name
Test status
Simulation time 3351310870 ps
CPU time 7.87 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:17:32 PM PDT 24
Peak memory 201668 kb
Host smart-e7cd376e-a1eb-48ed-b116-861f3d8c43a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279887584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.279887584
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1691532598
Short name T416
Test name
Test status
Simulation time 5844002875 ps
CPU time 13.35 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:17:38 PM PDT 24
Peak memory 201692 kb
Host smart-11a6608e-c5f8-47b4-b3ca-3a0de0392c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691532598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1691532598
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2945971587
Short name T793
Test name
Test status
Simulation time 61639989040 ps
CPU time 124.02 seconds
Started Jul 16 07:17:22 PM PDT 24
Finished Jul 16 07:19:28 PM PDT 24
Peak memory 210464 kb
Host smart-ab3bd6db-a717-47f5-bd03-e8323702bb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945971587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2945971587
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2380419383
Short name T695
Test name
Test status
Simulation time 518018652 ps
CPU time 1.72 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:17:40 PM PDT 24
Peak memory 201664 kb
Host smart-4a9ae5d4-1639-46ef-b1e8-03ee8a79ae90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380419383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2380419383
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3715980500
Short name T569
Test name
Test status
Simulation time 336196555629 ps
CPU time 184.41 seconds
Started Jul 16 07:17:20 PM PDT 24
Finished Jul 16 07:20:27 PM PDT 24
Peak memory 201968 kb
Host smart-5128c6a9-97fc-4c2a-ada4-5677859427d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715980500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3715980500
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.195970795
Short name T201
Test name
Test status
Simulation time 168736453670 ps
CPU time 351.73 seconds
Started Jul 16 07:17:21 PM PDT 24
Finished Jul 16 07:23:16 PM PDT 24
Peak memory 201916 kb
Host smart-19e0ee50-0806-4b2c-bea8-7bd3778d47d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195970795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.195970795
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2824443698
Short name T631
Test name
Test status
Simulation time 336805117129 ps
CPU time 816.35 seconds
Started Jul 16 07:17:23 PM PDT 24
Finished Jul 16 07:31:02 PM PDT 24
Peak memory 201784 kb
Host smart-b164d2e8-ee60-44c8-b700-31fa5dac57e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824443698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2824443698
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1310838216
Short name T648
Test name
Test status
Simulation time 168328825263 ps
CPU time 180.88 seconds
Started Jul 16 07:17:25 PM PDT 24
Finished Jul 16 07:20:27 PM PDT 24
Peak memory 201900 kb
Host smart-d015aec4-f4ab-4243-917d-331f70a6c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310838216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1310838216
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2370346053
Short name T502
Test name
Test status
Simulation time 168092306107 ps
CPU time 376.93 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:23:38 PM PDT 24
Peak memory 201880 kb
Host smart-a2a10517-c3d8-41be-8de4-7ba99747e16a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370346053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2370346053
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3908131508
Short name T686
Test name
Test status
Simulation time 600343523577 ps
CPU time 662.61 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:28:24 PM PDT 24
Peak memory 201876 kb
Host smart-445d2eb4-6c0d-4bd4-a9d6-a1d598d0ae1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908131508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3908131508
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3798432857
Short name T755
Test name
Test status
Simulation time 100704779026 ps
CPU time 476.27 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:25:18 PM PDT 24
Peak memory 202292 kb
Host smart-6a694e88-9c2f-42eb-b228-167dc40852a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798432857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3798432857
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1110341491
Short name T691
Test name
Test status
Simulation time 23960460832 ps
CPU time 54.5 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:18:17 PM PDT 24
Peak memory 201656 kb
Host smart-3fb60f74-1434-41d2-b110-e78ccde0b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110341491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1110341491
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.256915625
Short name T725
Test name
Test status
Simulation time 3379566785 ps
CPU time 4.99 seconds
Started Jul 16 07:17:21 PM PDT 24
Finished Jul 16 07:17:29 PM PDT 24
Peak memory 201684 kb
Host smart-955f56a6-90cb-420a-9a36-4a000bca7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256915625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.256915625
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3455112611
Short name T456
Test name
Test status
Simulation time 5943885547 ps
CPU time 14.29 seconds
Started Jul 16 07:17:18 PM PDT 24
Finished Jul 16 07:17:35 PM PDT 24
Peak memory 201672 kb
Host smart-5cf22fb2-1c3a-43be-8c9c-657c230e1153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455112611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3455112611
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.191408837
Short name T756
Test name
Test status
Simulation time 170824206025 ps
CPU time 118.05 seconds
Started Jul 16 07:17:39 PM PDT 24
Finished Jul 16 07:19:40 PM PDT 24
Peak memory 201892 kb
Host smart-488dadbd-a44e-40d5-9539-c06d40efc960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191408837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
191408837
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.14697191
Short name T342
Test name
Test status
Simulation time 18098050113 ps
CPU time 52.14 seconds
Started Jul 16 07:17:19 PM PDT 24
Finished Jul 16 07:18:14 PM PDT 24
Peak memory 210544 kb
Host smart-426bccb8-9f2e-49be-b854-12b67a121ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14697191 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.14697191
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3589876940
Short name T780
Test name
Test status
Simulation time 350933825 ps
CPU time 0.86 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:17:38 PM PDT 24
Peak memory 201568 kb
Host smart-d9a36dc5-cdbf-4ab3-9bf5-5f39debab833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589876940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3589876940
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3804841732
Short name T90
Test name
Test status
Simulation time 164135551813 ps
CPU time 194.08 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:20:51 PM PDT 24
Peak memory 201892 kb
Host smart-e1a92d6a-dc78-4ef1-b4ac-8b672bcafbf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804841732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3804841732
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3799660426
Short name T176
Test name
Test status
Simulation time 495370295474 ps
CPU time 301.78 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:22:45 PM PDT 24
Peak memory 201908 kb
Host smart-5cbdbdaa-b168-4dff-ae04-8292249d8cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799660426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3799660426
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2161199061
Short name T199
Test name
Test status
Simulation time 326328057224 ps
CPU time 183.83 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:20:42 PM PDT 24
Peak memory 202160 kb
Host smart-04f6c178-2357-4329-82e1-34ce0ee3cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161199061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2161199061
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.309115106
Short name T673
Test name
Test status
Simulation time 326367340106 ps
CPU time 395.7 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:24:15 PM PDT 24
Peak memory 201968 kb
Host smart-8594a702-f6ac-4879-bcec-cb5534c5b8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309115106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.309115106
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4000636614
Short name T422
Test name
Test status
Simulation time 161257178397 ps
CPU time 361.58 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 201864 kb
Host smart-2ac3f15b-e76d-470b-870d-a32babd4de59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000636614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4000636614
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1330699416
Short name T161
Test name
Test status
Simulation time 368941007959 ps
CPU time 890.26 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:32:28 PM PDT 24
Peak memory 201832 kb
Host smart-1722fc30-d864-47d1-9c5c-fa093cf4ff5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330699416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1330699416
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1029424787
Short name T779
Test name
Test status
Simulation time 602078478941 ps
CPU time 218.21 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:21:14 PM PDT 24
Peak memory 201840 kb
Host smart-a9c369d5-cc5b-4551-8766-7a346229bdb0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029424787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1029424787
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3132043219
Short name T402
Test name
Test status
Simulation time 83521024731 ps
CPU time 407.96 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:24:31 PM PDT 24
Peak memory 202272 kb
Host smart-28c33df0-4100-4a12-bd1d-bd6364483f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132043219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3132043219
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.564543464
Short name T451
Test name
Test status
Simulation time 36079650092 ps
CPU time 38.79 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:18:16 PM PDT 24
Peak memory 201672 kb
Host smart-48908afd-dc6f-4985-a163-4296ff73b6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564543464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.564543464
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4213059547
Short name T519
Test name
Test status
Simulation time 3023507397 ps
CPU time 7.41 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:17:51 PM PDT 24
Peak memory 201728 kb
Host smart-9e363119-146e-43fe-9358-2a2b2a681f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213059547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4213059547
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2214651488
Short name T363
Test name
Test status
Simulation time 5553503284 ps
CPU time 12.6 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:17:49 PM PDT 24
Peak memory 201704 kb
Host smart-3f23cdac-8ebc-4cb7-948c-e5b8b0c7b1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214651488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2214651488
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1883952098
Short name T35
Test name
Test status
Simulation time 329910057378 ps
CPU time 98.68 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:19:14 PM PDT 24
Peak memory 201908 kb
Host smart-e1362442-58ad-4d2a-bb47-586462f1c076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883952098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1883952098
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.996632392
Short name T215
Test name
Test status
Simulation time 407009352911 ps
CPU time 296.74 seconds
Started Jul 16 07:17:32 PM PDT 24
Finished Jul 16 07:22:30 PM PDT 24
Peak memory 210592 kb
Host smart-05d5b00d-8d32-4192-9a64-2bdbe5b86bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996632392 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.996632392
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1987292978
Short name T746
Test name
Test status
Simulation time 314036338 ps
CPU time 0.98 seconds
Started Jul 16 07:17:39 PM PDT 24
Finished Jul 16 07:17:42 PM PDT 24
Peak memory 201588 kb
Host smart-1fa5030d-b514-41ef-b227-224b2f95aae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987292978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1987292978
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.939345071
Short name T322
Test name
Test status
Simulation time 176842523450 ps
CPU time 106.55 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:19:23 PM PDT 24
Peak memory 201932 kb
Host smart-ca6c8a98-c357-477d-8c70-ea8a331d3456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939345071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.939345071
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.748928023
Short name T160
Test name
Test status
Simulation time 173557748444 ps
CPU time 206.65 seconds
Started Jul 16 07:17:31 PM PDT 24
Finished Jul 16 07:21:00 PM PDT 24
Peak memory 201908 kb
Host smart-619eea8c-0869-4c83-b46d-cb8f30a5c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748928023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.748928023
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2296601497
Short name T580
Test name
Test status
Simulation time 503190486952 ps
CPU time 837.96 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:31:39 PM PDT 24
Peak memory 201836 kb
Host smart-e0452e8d-291b-4a17-9c8a-8985d64169ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296601497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2296601497
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4218429742
Short name T180
Test name
Test status
Simulation time 496398102377 ps
CPU time 295.99 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:22:34 PM PDT 24
Peak memory 201832 kb
Host smart-402be3a9-ee3f-43ea-906b-508ae28aee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218429742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4218429742
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.683783148
Short name T547
Test name
Test status
Simulation time 169103370811 ps
CPU time 364.6 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:23:48 PM PDT 24
Peak memory 201640 kb
Host smart-efcc8d3d-37ae-4f74-af55-856c6f54ea06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=683783148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.683783148
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.907634574
Short name T169
Test name
Test status
Simulation time 664513604269 ps
CPU time 259.53 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:21:55 PM PDT 24
Peak memory 201908 kb
Host smart-866af884-f2fd-46c5-9387-6020df0b556f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907634574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.907634574
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4044675148
Short name T522
Test name
Test status
Simulation time 598150225832 ps
CPU time 332.89 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:23:14 PM PDT 24
Peak memory 201972 kb
Host smart-22663676-b2d0-40a1-8d00-0d9d3bd08174
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044675148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4044675148
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.730994415
Short name T652
Test name
Test status
Simulation time 64767118418 ps
CPU time 258.19 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:21:56 PM PDT 24
Peak memory 202236 kb
Host smart-50353ee6-098e-444b-aa6d-703a6abf4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730994415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.730994415
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2238086396
Short name T361
Test name
Test status
Simulation time 27153003775 ps
CPU time 52.17 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:18:32 PM PDT 24
Peak memory 201660 kb
Host smart-e91be768-5a08-4b8e-a008-b6389fc48158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238086396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2238086396
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3219218650
Short name T400
Test name
Test status
Simulation time 5030474458 ps
CPU time 10.46 seconds
Started Jul 16 07:17:33 PM PDT 24
Finished Jul 16 07:17:45 PM PDT 24
Peak memory 201728 kb
Host smart-3a4a4a43-97f9-4d93-add6-58f9d9016602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219218650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3219218650
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3711302084
Short name T474
Test name
Test status
Simulation time 6194301232 ps
CPU time 13.45 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:17:49 PM PDT 24
Peak memory 201656 kb
Host smart-c512d08f-0d58-45de-ba7d-c6ac230fedab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711302084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3711302084
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.404173776
Short name T23
Test name
Test status
Simulation time 72912382726 ps
CPU time 105.08 seconds
Started Jul 16 07:17:31 PM PDT 24
Finished Jul 16 07:19:18 PM PDT 24
Peak memory 210604 kb
Host smart-7047c4c9-f5ac-4244-9fe9-7b1e9867d31c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404173776 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.404173776
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.424916643
Short name T772
Test name
Test status
Simulation time 309164808 ps
CPU time 1 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:17:37 PM PDT 24
Peak memory 201604 kb
Host smart-1270102c-be67-4896-b9ff-5fe4e021a48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424916643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.424916643
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2756963558
Short name T175
Test name
Test status
Simulation time 213780806667 ps
CPU time 14.95 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:17:58 PM PDT 24
Peak memory 201880 kb
Host smart-7d14548d-672a-4af3-a2fa-cacee03193e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756963558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2756963558
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.113611113
Short name T170
Test name
Test status
Simulation time 345902965372 ps
CPU time 835.9 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:31:35 PM PDT 24
Peak memory 202088 kb
Host smart-67728bc2-9b45-4e75-a56d-368a4624f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113611113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.113611113
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2804773100
Short name T143
Test name
Test status
Simulation time 501112477579 ps
CPU time 230.62 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:21:32 PM PDT 24
Peak memory 201916 kb
Host smart-bbd9a725-48fe-4a32-8564-c082d738c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804773100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2804773100
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.416952199
Short name T503
Test name
Test status
Simulation time 485294060775 ps
CPU time 268.28 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:22:04 PM PDT 24
Peak memory 201820 kb
Host smart-4b54abd8-3439-4e0a-921d-8466127bc618
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=416952199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.416952199
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.208891005
Short name T275
Test name
Test status
Simulation time 161995427461 ps
CPU time 338.34 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:23:17 PM PDT 24
Peak memory 201912 kb
Host smart-61f1d648-c75c-413c-85f9-b2cc1947cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208891005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.208891005
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2847411292
Short name T445
Test name
Test status
Simulation time 170913271186 ps
CPU time 56.72 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:18:37 PM PDT 24
Peak memory 201852 kb
Host smart-ec64a07c-8eed-4441-8fe8-11e702decfe9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847411292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2847411292
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1370729864
Short name T512
Test name
Test status
Simulation time 567791360452 ps
CPU time 301.35 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:22:44 PM PDT 24
Peak memory 201844 kb
Host smart-eceec7c5-784c-43ae-ba1a-43cbae17784b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370729864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1370729864
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2345135175
Short name T447
Test name
Test status
Simulation time 199244189110 ps
CPU time 107.47 seconds
Started Jul 16 07:17:31 PM PDT 24
Finished Jul 16 07:19:20 PM PDT 24
Peak memory 201864 kb
Host smart-ff94080e-59dd-42fe-94b6-c65da8938540
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345135175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2345135175
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3292447483
Short name T348
Test name
Test status
Simulation time 115745295776 ps
CPU time 437.43 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:24:54 PM PDT 24
Peak memory 202140 kb
Host smart-a06b9542-55ae-4a4e-b280-7b0fb647dcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292447483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3292447483
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2189825105
Short name T138
Test name
Test status
Simulation time 38092596820 ps
CPU time 84.04 seconds
Started Jul 16 07:17:35 PM PDT 24
Finished Jul 16 07:19:01 PM PDT 24
Peak memory 201700 kb
Host smart-ce9d8290-fb94-4da9-82db-73aaea6ab1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189825105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2189825105
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.794030348
Short name T493
Test name
Test status
Simulation time 3926574235 ps
CPU time 2.89 seconds
Started Jul 16 07:17:39 PM PDT 24
Finished Jul 16 07:17:44 PM PDT 24
Peak memory 201664 kb
Host smart-60d5c04c-48aa-4044-ac20-7a216132b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794030348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.794030348
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3426103084
Short name T115
Test name
Test status
Simulation time 5993636703 ps
CPU time 14.02 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:17:53 PM PDT 24
Peak memory 201652 kb
Host smart-06f42b41-cd81-4256-a905-b152fbb5daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426103084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3426103084
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3604747737
Short name T104
Test name
Test status
Simulation time 213081987547 ps
CPU time 471.57 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:25:30 PM PDT 24
Peak memory 201892 kb
Host smart-f562cecc-3662-4fd4-b513-658d56f875e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604747737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3604747737
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.319856298
Short name T439
Test name
Test status
Simulation time 443535561 ps
CPU time 0.86 seconds
Started Jul 16 07:16:24 PM PDT 24
Finished Jul 16 07:17:05 PM PDT 24
Peak memory 201576 kb
Host smart-ff20b090-4687-40ff-a444-9360794a6729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319856298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.319856298
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1760889795
Short name T233
Test name
Test status
Simulation time 515138942733 ps
CPU time 1112.83 seconds
Started Jul 16 07:16:24 PM PDT 24
Finished Jul 16 07:35:37 PM PDT 24
Peak memory 201836 kb
Host smart-8a424dc5-859c-4cdb-a982-df008b949bec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760889795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1760889795
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1137989841
Short name T724
Test name
Test status
Simulation time 502548492133 ps
CPU time 1152.2 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 201896 kb
Host smart-18341cc0-ac6d-499f-881c-013c09d0514d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137989841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1137989841
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1549800868
Short name T31
Test name
Test status
Simulation time 496032252995 ps
CPU time 1109.73 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:35:35 PM PDT 24
Peak memory 201920 kb
Host smart-35ee26e8-e7fa-4a01-92f7-2d0e4ec8e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549800868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1549800868
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.213496811
Short name T380
Test name
Test status
Simulation time 327856710420 ps
CPU time 789.03 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:30:15 PM PDT 24
Peak memory 201912 kb
Host smart-9b7363ed-7fd4-47b6-953c-316add92b365
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=213496811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.213496811
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1777907427
Short name T782
Test name
Test status
Simulation time 415195218331 ps
CPU time 266.96 seconds
Started Jul 16 07:16:29 PM PDT 24
Finished Jul 16 07:21:33 PM PDT 24
Peak memory 201892 kb
Host smart-19fc4bbd-3fd5-47c3-9f3e-12d773eda287
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777907427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1777907427
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3366126591
Short name T618
Test name
Test status
Simulation time 136477728208 ps
CPU time 661.15 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:28:05 PM PDT 24
Peak memory 202224 kb
Host smart-fc452fd7-bb01-44a6-9c18-01485b59be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366126591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3366126591
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2665448726
Short name T701
Test name
Test status
Simulation time 43124037476 ps
CPU time 25.8 seconds
Started Jul 16 07:16:28 PM PDT 24
Finished Jul 16 07:17:32 PM PDT 24
Peak memory 201708 kb
Host smart-7b6fbd4d-a38c-4391-b1a0-3761cdab0725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665448726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2665448726
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3951014598
Short name T374
Test name
Test status
Simulation time 4761676523 ps
CPU time 9.7 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:16 PM PDT 24
Peak memory 201732 kb
Host smart-2eefc2cf-89fb-4445-b214-6fdc28beb599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951014598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3951014598
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1631449888
Short name T70
Test name
Test status
Simulation time 8047114572 ps
CPU time 17.92 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:24 PM PDT 24
Peak memory 218228 kb
Host smart-1115eadc-90f3-4410-8ec3-e3e15120711a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631449888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1631449888
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3311927012
Short name T462
Test name
Test status
Simulation time 5860369462 ps
CPU time 10.44 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:16 PM PDT 24
Peak memory 201712 kb
Host smart-c18fd16f-460d-4fa2-93fb-254cf1af2753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311927012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3311927012
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.214699564
Short name T729
Test name
Test status
Simulation time 420919422 ps
CPU time 0.86 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:17:44 PM PDT 24
Peak memory 201684 kb
Host smart-2ad9c0e2-4496-4ca4-b0cf-da0c2923c6e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214699564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.214699564
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1376444510
Short name T277
Test name
Test status
Simulation time 496461547188 ps
CPU time 453.06 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:25:11 PM PDT 24
Peak memory 201844 kb
Host smart-a84d9388-9dec-4c93-bccd-32737cd501c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376444510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1376444510
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1999097258
Short name T282
Test name
Test status
Simulation time 166041313205 ps
CPU time 388.78 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:24:10 PM PDT 24
Peak memory 201916 kb
Host smart-dc931532-af4b-42de-9b38-6cf27c170710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999097258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1999097258
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3863996100
Short name T237
Test name
Test status
Simulation time 490366839310 ps
CPU time 542.58 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:26:42 PM PDT 24
Peak memory 201820 kb
Host smart-6c6ac978-c338-441c-bf37-145c1a981485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863996100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3863996100
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3149530226
Short name T555
Test name
Test status
Simulation time 327150163554 ps
CPU time 766.07 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:30:29 PM PDT 24
Peak memory 201920 kb
Host smart-7454f274-6890-44d5-a6bb-9589156d4099
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149530226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3149530226
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.934089403
Short name T638
Test name
Test status
Simulation time 326081697803 ps
CPU time 358.86 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 201760 kb
Host smart-16111a01-f8ea-4462-9525-2a21a03d45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934089403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.934089403
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3432513584
Short name T705
Test name
Test status
Simulation time 167341859916 ps
CPU time 31.07 seconds
Started Jul 16 07:17:34 PM PDT 24
Finished Jul 16 07:18:07 PM PDT 24
Peak memory 201816 kb
Host smart-0708f393-3d79-4a4e-bdeb-534f2ed6ebc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432513584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3432513584
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.626588227
Short name T44
Test name
Test status
Simulation time 180997107078 ps
CPU time 418.99 seconds
Started Jul 16 07:17:42 PM PDT 24
Finished Jul 16 07:24:43 PM PDT 24
Peak memory 201984 kb
Host smart-99e89095-f943-467d-bf91-bb174552c134
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626588227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.626588227
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2862825870
Short name T435
Test name
Test status
Simulation time 196405583482 ps
CPU time 446.49 seconds
Started Jul 16 07:17:32 PM PDT 24
Finished Jul 16 07:25:01 PM PDT 24
Peak memory 201896 kb
Host smart-f54c29e4-67f0-4a86-9ac8-c42d60dfe4bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862825870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2862825870
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1391298939
Short name T492
Test name
Test status
Simulation time 56163309928 ps
CPU time 197.9 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:20:56 PM PDT 24
Peak memory 202208 kb
Host smart-bcae4910-f5ad-4a56-8a31-0ea520aef19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391298939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1391298939
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.28116418
Short name T397
Test name
Test status
Simulation time 38017962677 ps
CPU time 83 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:19:03 PM PDT 24
Peak memory 201724 kb
Host smart-24eb3806-d484-4408-a316-873b11990be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28116418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.28116418
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2223545201
Short name T52
Test name
Test status
Simulation time 4671751833 ps
CPU time 3.1 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:17:43 PM PDT 24
Peak memory 201888 kb
Host smart-2a3daeb1-e1a8-47eb-8c7b-591b1d19e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223545201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2223545201
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1416541738
Short name T354
Test name
Test status
Simulation time 5861910863 ps
CPU time 8.6 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:17:52 PM PDT 24
Peak memory 201740 kb
Host smart-fae5ff1a-423c-49e8-8c92-df50764af33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416541738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1416541738
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2960331153
Short name T61
Test name
Test status
Simulation time 362808484996 ps
CPU time 59.07 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:18:40 PM PDT 24
Peak memory 201908 kb
Host smart-83d83ade-8d8d-4774-9966-e75140109d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960331153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2960331153
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1364227321
Short name T678
Test name
Test status
Simulation time 388339224298 ps
CPU time 158.7 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:20:20 PM PDT 24
Peak memory 210236 kb
Host smart-edb9aec3-d19f-46a9-92c0-45f0a5285c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364227321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1364227321
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2447847264
Short name T401
Test name
Test status
Simulation time 359247084 ps
CPU time 1.46 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:18:09 PM PDT 24
Peak memory 201588 kb
Host smart-56a79753-4fa3-4884-82c8-b92a0d578514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447847264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2447847264
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1088342565
Short name T446
Test name
Test status
Simulation time 159897945857 ps
CPU time 84.27 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:19:04 PM PDT 24
Peak memory 201964 kb
Host smart-788c8127-1d03-4f1d-80ec-4465ed48091e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088342565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1088342565
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4066121056
Short name T713
Test name
Test status
Simulation time 157571587138 ps
CPU time 180.1 seconds
Started Jul 16 07:17:41 PM PDT 24
Finished Jul 16 07:20:43 PM PDT 24
Peak memory 201840 kb
Host smart-1cf87772-599a-4a88-8d0d-d28b297f5a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066121056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4066121056
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2706247819
Short name T434
Test name
Test status
Simulation time 487909014893 ps
CPU time 271.04 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:22:11 PM PDT 24
Peak memory 201892 kb
Host smart-f32ef839-6a6e-4e26-9fe6-54c7a3ac223b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706247819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2706247819
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.204480156
Short name T703
Test name
Test status
Simulation time 483188354308 ps
CPU time 266.33 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:22:06 PM PDT 24
Peak memory 201832 kb
Host smart-cc5b0e3b-3433-4a30-a977-f44a15aad1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204480156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.204480156
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4275401539
Short name T419
Test name
Test status
Simulation time 497221352187 ps
CPU time 187.42 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:20:48 PM PDT 24
Peak memory 201908 kb
Host smart-3dfc879d-cfb7-45f4-aaac-a645fe3af96a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275401539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4275401539
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.4120229509
Short name T295
Test name
Test status
Simulation time 166093768115 ps
CPU time 399.17 seconds
Started Jul 16 07:17:36 PM PDT 24
Finished Jul 16 07:24:17 PM PDT 24
Peak memory 201896 kb
Host smart-e18c818e-d1e7-4c6d-918c-367568d5adec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120229509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.4120229509
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.816221718
Short name T507
Test name
Test status
Simulation time 417189943912 ps
CPU time 60.59 seconds
Started Jul 16 07:17:37 PM PDT 24
Finished Jul 16 07:18:40 PM PDT 24
Peak memory 201900 kb
Host smart-194816d4-5932-49b8-856b-db57a8ca3531
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816221718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.816221718
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2799839564
Short name T56
Test name
Test status
Simulation time 84133978303 ps
CPU time 358.61 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 202288 kb
Host smart-5b865847-60fc-4f69-b018-bf4095585dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799839564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2799839564
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2032592155
Short name T376
Test name
Test status
Simulation time 39703837034 ps
CPU time 22.85 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:18:50 PM PDT 24
Peak memory 201696 kb
Host smart-27633712-0b0e-4d7a-98bc-088e132e4eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032592155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2032592155
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.416227697
Short name T523
Test name
Test status
Simulation time 4708093105 ps
CPU time 3.64 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:17:54 PM PDT 24
Peak memory 201736 kb
Host smart-2b276147-b433-42aa-9688-07f17e721e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416227697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.416227697
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3743900648
Short name T662
Test name
Test status
Simulation time 6008867482 ps
CPU time 14.37 seconds
Started Jul 16 07:17:38 PM PDT 24
Finished Jul 16 07:17:55 PM PDT 24
Peak memory 201716 kb
Host smart-93063f13-9e34-40ea-a10f-ac241b527bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743900648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3743900648
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1295292672
Short name T114
Test name
Test status
Simulation time 204077237582 ps
CPU time 209.52 seconds
Started Jul 16 07:17:47 PM PDT 24
Finished Jul 16 07:21:19 PM PDT 24
Peak memory 201892 kb
Host smart-03c50f46-1de3-4ad3-a17e-993ff4ac1bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295292672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1295292672
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1973636684
Short name T102
Test name
Test status
Simulation time 596035591 ps
CPU time 0.75 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:18:23 PM PDT 24
Peak memory 201664 kb
Host smart-5cdbfb5e-abe1-47a0-888e-fa9518142de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973636684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1973636684
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3721805297
Short name T778
Test name
Test status
Simulation time 493018821538 ps
CPU time 763.71 seconds
Started Jul 16 07:17:47 PM PDT 24
Finished Jul 16 07:30:33 PM PDT 24
Peak memory 201960 kb
Host smart-8f650612-929a-4aca-a3b7-0a11892e75c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721805297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3721805297
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3089402121
Short name T704
Test name
Test status
Simulation time 168455796907 ps
CPU time 181.06 seconds
Started Jul 16 07:17:44 PM PDT 24
Finished Jul 16 07:20:47 PM PDT 24
Peak memory 201928 kb
Host smart-308386d7-ecd6-47ff-b6c7-6b7ea9b334ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089402121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3089402121
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2092884863
Short name T25
Test name
Test status
Simulation time 165542307814 ps
CPU time 355.03 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:23:51 PM PDT 24
Peak memory 201808 kb
Host smart-f565e1a7-14a5-43c5-9e70-007fb4fa3b76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092884863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2092884863
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3410764010
Short name T315
Test name
Test status
Simulation time 338164271238 ps
CPU time 788.09 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:31:08 PM PDT 24
Peak memory 201868 kb
Host smart-3b3a7b87-45bd-4f59-8f9b-fb1ce76bdb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410764010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3410764010
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.930531519
Short name T6
Test name
Test status
Simulation time 497116709090 ps
CPU time 253.78 seconds
Started Jul 16 07:17:55 PM PDT 24
Finished Jul 16 07:22:27 PM PDT 24
Peak memory 201884 kb
Host smart-60b00794-2af4-4f1e-ae83-5d0e7e92d101
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930531519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.930531519
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1070973269
Short name T744
Test name
Test status
Simulation time 368135460435 ps
CPU time 391.21 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 201636 kb
Host smart-3ea5ecc7-7dc0-400a-8428-13553b9c74e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070973269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1070973269
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2667858842
Short name T700
Test name
Test status
Simulation time 407635930331 ps
CPU time 816.75 seconds
Started Jul 16 07:17:46 PM PDT 24
Finished Jul 16 07:31:24 PM PDT 24
Peak memory 201872 kb
Host smart-d33bceaf-b46d-4593-b858-1e285101fbfe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667858842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2667858842
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2245614235
Short name T111
Test name
Test status
Simulation time 76026890437 ps
CPU time 297.49 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:23:05 PM PDT 24
Peak memory 202264 kb
Host smart-80300715-bd40-4f5b-8af1-0e71dcf71916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245614235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2245614235
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3765487165
Short name T364
Test name
Test status
Simulation time 25400869799 ps
CPU time 62.18 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:19:06 PM PDT 24
Peak memory 201676 kb
Host smart-024e2266-cef3-486e-92d3-a7db327fc694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765487165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3765487165
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.290816103
Short name T688
Test name
Test status
Simulation time 5010318747 ps
CPU time 13.59 seconds
Started Jul 16 07:17:49 PM PDT 24
Finished Jul 16 07:18:05 PM PDT 24
Peak memory 201680 kb
Host smart-b750a5e4-3b25-443a-b2c5-47a4377a2f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290816103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.290816103
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3370442504
Short name T739
Test name
Test status
Simulation time 5824099761 ps
CPU time 14.38 seconds
Started Jul 16 07:17:46 PM PDT 24
Finished Jul 16 07:18:02 PM PDT 24
Peak memory 201704 kb
Host smart-faf056bc-54ca-4dac-9400-37f893aa4664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370442504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3370442504
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3728327272
Short name T537
Test name
Test status
Simulation time 422591167081 ps
CPU time 1176.76 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:37:38 PM PDT 24
Peak memory 210440 kb
Host smart-cf683c90-c900-459f-8042-60286a0498ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728327272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3728327272
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.542260151
Short name T19
Test name
Test status
Simulation time 85554397776 ps
CPU time 44.76 seconds
Started Jul 16 07:17:47 PM PDT 24
Finished Jul 16 07:18:34 PM PDT 24
Peak memory 211296 kb
Host smart-336b56f2-661d-4b90-a771-b32991459100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542260151 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.542260151
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2715727740
Short name T231
Test name
Test status
Simulation time 557988474685 ps
CPU time 669.98 seconds
Started Jul 16 07:17:46 PM PDT 24
Finished Jul 16 07:28:58 PM PDT 24
Peak memory 201908 kb
Host smart-d0c846c4-6535-4732-99a1-3b8e43d5695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715727740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2715727740
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.208630244
Short name T396
Test name
Test status
Simulation time 161156211146 ps
CPU time 354.8 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 201852 kb
Host smart-618b5621-b586-4b12-b488-2bb848dfe2d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=208630244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.208630244
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4242808703
Short name T749
Test name
Test status
Simulation time 162060200257 ps
CPU time 341.93 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 201872 kb
Host smart-6f813513-dd58-4df3-b007-40204164175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242808703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4242808703
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1629806135
Short name T646
Test name
Test status
Simulation time 485604093228 ps
CPU time 587.35 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:27:44 PM PDT 24
Peak memory 201808 kb
Host smart-692d8c4c-0b73-4020-b445-813cfa0ee84b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629806135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1629806135
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.744828834
Short name T162
Test name
Test status
Simulation time 189409580099 ps
CPU time 246.94 seconds
Started Jul 16 07:17:53 PM PDT 24
Finished Jul 16 07:22:15 PM PDT 24
Peak memory 201848 kb
Host smart-e486511d-7694-4eac-8723-42142dfd5e71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744828834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.744828834
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.641071179
Short name T112
Test name
Test status
Simulation time 203827617948 ps
CPU time 31.37 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:18:21 PM PDT 24
Peak memory 201928 kb
Host smart-e0f9f932-1342-489f-84bf-b10b811c61b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641071179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.641071179
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2062603027
Short name T609
Test name
Test status
Simulation time 103815247036 ps
CPU time 539.61 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:27:26 PM PDT 24
Peak memory 202296 kb
Host smart-d034a53e-85f8-4c1b-abb7-ddca93283fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062603027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2062603027
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2873019473
Short name T491
Test name
Test status
Simulation time 43748137883 ps
CPU time 26.22 seconds
Started Jul 16 07:17:50 PM PDT 24
Finished Jul 16 07:18:20 PM PDT 24
Peak memory 201676 kb
Host smart-fb454050-5989-4a88-b05d-30f6c3cf51e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873019473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2873019473
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1251789655
Short name T562
Test name
Test status
Simulation time 2934236431 ps
CPU time 6.96 seconds
Started Jul 16 07:17:58 PM PDT 24
Finished Jul 16 07:18:29 PM PDT 24
Peak memory 201720 kb
Host smart-99568f15-db3f-4628-a6ed-1a0533b85a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251789655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1251789655
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3019947695
Short name T509
Test name
Test status
Simulation time 5855812921 ps
CPU time 13.71 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:18:04 PM PDT 24
Peak memory 201712 kb
Host smart-6d2dd15d-caf6-4c58-bf45-b03253d9331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019947695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3019947695
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.994349991
Short name T36
Test name
Test status
Simulation time 165149748949 ps
CPU time 97.14 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:19:59 PM PDT 24
Peak memory 201904 kb
Host smart-06591b81-61a8-4a65-8f0c-d65b0c4ab05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994349991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
994349991
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2119473539
Short name T245
Test name
Test status
Simulation time 54683847262 ps
CPU time 34.95 seconds
Started Jul 16 07:17:44 PM PDT 24
Finished Jul 16 07:18:20 PM PDT 24
Peak memory 210392 kb
Host smart-a6031951-8cb9-4f6f-9c32-028559d7f8f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119473539 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2119473539
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.260465441
Short name T454
Test name
Test status
Simulation time 479328034 ps
CPU time 1.47 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:18:03 PM PDT 24
Peak memory 201464 kb
Host smart-4ac46b8d-9a42-401a-966c-9aad13cbc896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260465441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.260465441
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.347424673
Short name T530
Test name
Test status
Simulation time 359535594675 ps
CPU time 112.36 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:20:15 PM PDT 24
Peak memory 201908 kb
Host smart-df26f7aa-b9b7-49a0-a126-d4eca865f992
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347424673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.347424673
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3995422407
Short name T343
Test name
Test status
Simulation time 335635361883 ps
CPU time 376.72 seconds
Started Jul 16 07:17:55 PM PDT 24
Finished Jul 16 07:24:30 PM PDT 24
Peak memory 201936 kb
Host smart-b622523e-94ba-49ed-bf7b-7004523061ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995422407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3995422407
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1487476190
Short name T526
Test name
Test status
Simulation time 319067514230 ps
CPU time 180.02 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:20:56 PM PDT 24
Peak memory 201824 kb
Host smart-e5c6796c-ebf9-47c8-ad43-2fee34ab06fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487476190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1487476190
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3639909613
Short name T643
Test name
Test status
Simulation time 331139799783 ps
CPU time 180.75 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:21:02 PM PDT 24
Peak memory 201708 kb
Host smart-d12b181f-76e8-4a9e-8a01-66ddd48d7a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639909613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3639909613
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2586719837
Short name T625
Test name
Test status
Simulation time 332311422713 ps
CPU time 225.68 seconds
Started Jul 16 07:17:46 PM PDT 24
Finished Jul 16 07:21:33 PM PDT 24
Peak memory 201868 kb
Host smart-c846fd1c-e020-457a-b6c0-6bfb825018e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586719837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2586719837
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.384194682
Short name T10
Test name
Test status
Simulation time 375922415903 ps
CPU time 323.85 seconds
Started Jul 16 07:17:50 PM PDT 24
Finished Jul 16 07:23:18 PM PDT 24
Peak memory 201868 kb
Host smart-4e0ed90c-9f66-4d45-8947-f7e96b1dfcf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384194682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.384194682
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4093911308
Short name T427
Test name
Test status
Simulation time 195033392485 ps
CPU time 451.45 seconds
Started Jul 16 07:17:47 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 201928 kb
Host smart-90d78323-7fd6-4995-8e45-5e570c1c867d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093911308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4093911308
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1016920004
Short name T418
Test name
Test status
Simulation time 94465459481 ps
CPU time 485.48 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:25:55 PM PDT 24
Peak memory 201780 kb
Host smart-723fcaf7-18f9-4cde-8581-cfea37b2ec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016920004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1016920004
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1297509807
Short name T356
Test name
Test status
Simulation time 31763563036 ps
CPU time 4.63 seconds
Started Jul 16 07:17:47 PM PDT 24
Finished Jul 16 07:17:54 PM PDT 24
Peak memory 201712 kb
Host smart-739b4474-2f9a-40f4-af08-56291e778cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297509807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1297509807
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2734016844
Short name T676
Test name
Test status
Simulation time 4147939733 ps
CPU time 2.82 seconds
Started Jul 16 07:17:47 PM PDT 24
Finished Jul 16 07:17:51 PM PDT 24
Peak memory 201700 kb
Host smart-636b8d7c-5454-4d08-ba53-650af316e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734016844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2734016844
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.616623366
Short name T386
Test name
Test status
Simulation time 6158932342 ps
CPU time 8.33 seconds
Started Jul 16 07:17:50 PM PDT 24
Finished Jul 16 07:18:01 PM PDT 24
Peak memory 201684 kb
Host smart-570f8225-dc45-409c-8c9a-7ea91d6ed084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616623366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.616623366
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1079220080
Short name T232
Test name
Test status
Simulation time 591759601805 ps
CPU time 492.68 seconds
Started Jul 16 07:17:50 PM PDT 24
Finished Jul 16 07:26:07 PM PDT 24
Peak memory 202140 kb
Host smart-9c67bf8f-f6b3-4e83-bcd0-82015885d381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079220080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1079220080
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3598513438
Short name T424
Test name
Test status
Simulation time 503138283 ps
CPU time 1.26 seconds
Started Jul 16 07:18:03 PM PDT 24
Finished Jul 16 07:18:33 PM PDT 24
Peak memory 201648 kb
Host smart-7bfb3288-5d0f-4391-864b-3fecb09b7a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598513438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3598513438
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3927039743
Short name T768
Test name
Test status
Simulation time 161397878022 ps
CPU time 127.14 seconds
Started Jul 16 07:17:54 PM PDT 24
Finished Jul 16 07:20:16 PM PDT 24
Peak memory 201908 kb
Host smart-060c06be-bc9c-444b-91db-ee8ee3aa79f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927039743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3927039743
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3707171513
Short name T300
Test name
Test status
Simulation time 185755535500 ps
CPU time 115.12 seconds
Started Jul 16 07:17:54 PM PDT 24
Finished Jul 16 07:20:04 PM PDT 24
Peak memory 201900 kb
Host smart-cd1f30c2-0b7f-4d97-a47c-4298f7d27e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707171513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3707171513
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.474752948
Short name T621
Test name
Test status
Simulation time 495980221354 ps
CPU time 97.31 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:20:00 PM PDT 24
Peak memory 201888 kb
Host smart-430201fe-b310-4b16-8437-be7e92d39e46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=474752948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.474752948
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2234772927
Short name T639
Test name
Test status
Simulation time 489943986325 ps
CPU time 1058.21 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:35:34 PM PDT 24
Peak memory 201880 kb
Host smart-703fbc1d-2da0-4292-bbb9-a4a9b0a89b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234772927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2234772927
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3586776673
Short name T174
Test name
Test status
Simulation time 167851491574 ps
CPU time 99.63 seconds
Started Jul 16 07:17:55 PM PDT 24
Finished Jul 16 07:19:50 PM PDT 24
Peak memory 201860 kb
Host smart-d3887f42-90d7-4ed0-8ffc-3e727b6343c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586776673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3586776673
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.919525076
Short name T718
Test name
Test status
Simulation time 371053293809 ps
CPU time 738.75 seconds
Started Jul 16 07:17:46 PM PDT 24
Finished Jul 16 07:30:07 PM PDT 24
Peak memory 201920 kb
Host smart-7485b92a-836c-404b-944f-52fe48f7695c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919525076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.919525076
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2599516275
Short name T629
Test name
Test status
Simulation time 586632425040 ps
CPU time 1363.48 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:40:43 PM PDT 24
Peak memory 201856 kb
Host smart-c06089c9-c547-4934-b24b-93bd610df757
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599516275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2599516275
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2366431122
Short name T388
Test name
Test status
Simulation time 47830620686 ps
CPU time 11.07 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:18:37 PM PDT 24
Peak memory 201720 kb
Host smart-5b4637a6-4578-4224-9530-96d9a1ea8075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366431122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2366431122
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1825779970
Short name T384
Test name
Test status
Simulation time 4935801016 ps
CPU time 8.03 seconds
Started Jul 16 07:17:54 PM PDT 24
Finished Jul 16 07:18:17 PM PDT 24
Peak memory 201704 kb
Host smart-cb72d875-acb7-416e-96af-ea4fc88c3c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825779970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1825779970
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1427680591
Short name T651
Test name
Test status
Simulation time 6064995879 ps
CPU time 2.64 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:17:53 PM PDT 24
Peak memory 201688 kb
Host smart-621704ea-4b33-4d50-abd7-484ed8e25908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427680591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1427680591
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1211447368
Short name T442
Test name
Test status
Simulation time 6453615328 ps
CPU time 15.56 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:18:44 PM PDT 24
Peak memory 201700 kb
Host smart-3dbd7e30-561e-45f9-8cd5-03191b75a62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211447368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1211447368
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4245651598
Short name T626
Test name
Test status
Simulation time 148249811556 ps
CPU time 152.3 seconds
Started Jul 16 07:17:54 PM PDT 24
Finished Jul 16 07:20:42 PM PDT 24
Peak memory 210592 kb
Host smart-e9dd6274-6f10-4e86-a018-191f8c5c4f56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245651598 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.4245651598
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4169806864
Short name T355
Test name
Test status
Simulation time 367181249 ps
CPU time 0.72 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:18:30 PM PDT 24
Peak memory 201640 kb
Host smart-d67593e4-9f86-492a-a690-98bc871db02a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169806864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4169806864
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.32408473
Short name T256
Test name
Test status
Simulation time 336638694276 ps
CPU time 177.43 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:21:27 PM PDT 24
Peak memory 201900 kb
Host smart-ef5d9713-9eeb-426d-8ced-53da4034cc4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32408473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gatin
g.32408473
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2644330104
Short name T149
Test name
Test status
Simulation time 335920112141 ps
CPU time 381.52 seconds
Started Jul 16 07:17:49 PM PDT 24
Finished Jul 16 07:24:14 PM PDT 24
Peak memory 201916 kb
Host smart-93d396d8-b850-4739-8f11-0dd703d5dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644330104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2644330104
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3416256472
Short name T513
Test name
Test status
Simulation time 332347614350 ps
CPU time 184.32 seconds
Started Jul 16 07:18:03 PM PDT 24
Finished Jul 16 07:21:36 PM PDT 24
Peak memory 201872 kb
Host smart-2daa6f37-bbde-46a5-85cf-735206d4a2fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416256472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3416256472
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.162371714
Short name T576
Test name
Test status
Simulation time 497023547308 ps
CPU time 586.47 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:28:16 PM PDT 24
Peak memory 201948 kb
Host smart-35489fbd-b729-49a1-91f3-c20f6a95371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162371714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.162371714
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1141889667
Short name T87
Test name
Test status
Simulation time 167436003520 ps
CPU time 31.18 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:18:22 PM PDT 24
Peak memory 201828 kb
Host smart-b0bc4644-fb4e-4bde-a3d7-b974e2e925f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141889667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1141889667
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1960608467
Short name T171
Test name
Test status
Simulation time 360841123689 ps
CPU time 185.26 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:21:02 PM PDT 24
Peak memory 201912 kb
Host smart-1bffa59b-3669-4154-a63d-e37d60708f0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960608467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1960608467
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2441094305
Short name T472
Test name
Test status
Simulation time 591506234836 ps
CPU time 1050.77 seconds
Started Jul 16 07:17:56 PM PDT 24
Finished Jul 16 07:35:46 PM PDT 24
Peak memory 201904 kb
Host smart-1e2ebc74-e4b1-494a-82ad-28e715386b1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441094305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2441094305
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1178629556
Short name T753
Test name
Test status
Simulation time 119849556667 ps
CPU time 516.75 seconds
Started Jul 16 07:17:56 PM PDT 24
Finished Jul 16 07:26:52 PM PDT 24
Peak memory 202204 kb
Host smart-66029b94-cabc-4a7f-b169-6c41f083695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178629556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1178629556
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.930696067
Short name T664
Test name
Test status
Simulation time 44383712117 ps
CPU time 100.38 seconds
Started Jul 16 07:17:56 PM PDT 24
Finished Jul 16 07:19:56 PM PDT 24
Peak memory 201724 kb
Host smart-0cae4279-31b9-48d3-a943-71ce6edf7a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930696067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.930696067
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3782072138
Short name T518
Test name
Test status
Simulation time 4326837523 ps
CPU time 3.23 seconds
Started Jul 16 07:17:55 PM PDT 24
Finished Jul 16 07:18:16 PM PDT 24
Peak memory 201712 kb
Host smart-e42caf6b-3a32-49d6-b98d-475122fe4de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782072138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3782072138
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1381245870
Short name T196
Test name
Test status
Simulation time 6113475175 ps
CPU time 2.19 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:18:24 PM PDT 24
Peak memory 201712 kb
Host smart-e1d2e479-2eb3-4886-837e-2aa3083be875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381245870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1381245870
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1075577607
Short name T285
Test name
Test status
Simulation time 433704276555 ps
CPU time 239.7 seconds
Started Jul 16 07:17:55 PM PDT 24
Finished Jul 16 07:22:12 PM PDT 24
Peak memory 201900 kb
Host smart-0c9938a7-1050-4990-8b12-fb4a02f02dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075577607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1075577607
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2043507055
Short name T392
Test name
Test status
Simulation time 424885256 ps
CPU time 1.58 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:18:49 PM PDT 24
Peak memory 201508 kb
Host smart-9eae9304-6430-4446-bb5f-90049c79f37f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043507055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2043507055
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3657020964
Short name T335
Test name
Test status
Simulation time 528765816845 ps
CPU time 942.53 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:34:10 PM PDT 24
Peak memory 201672 kb
Host smart-29043b1c-2449-4b1b-870f-ca4318ab1829
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657020964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3657020964
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4068859613
Short name T710
Test name
Test status
Simulation time 335079411029 ps
CPU time 399.6 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:24:30 PM PDT 24
Peak memory 201876 kb
Host smart-ba3f0dbd-43cd-4e6d-b416-dd5f0da05575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068859613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4068859613
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3938276642
Short name T50
Test name
Test status
Simulation time 168432364500 ps
CPU time 99.78 seconds
Started Jul 16 07:18:04 PM PDT 24
Finished Jul 16 07:20:14 PM PDT 24
Peak memory 201888 kb
Host smart-dcd48c37-1a90-4121-9c2f-29890815137f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938276642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3938276642
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2067065318
Short name T635
Test name
Test status
Simulation time 486574156114 ps
CPU time 1064.09 seconds
Started Jul 16 07:17:48 PM PDT 24
Finished Jul 16 07:35:35 PM PDT 24
Peak memory 201868 kb
Host smart-23b7f8be-aac4-46a1-bde0-7e9ee3220b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067065318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2067065318
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3600816985
Short name T751
Test name
Test status
Simulation time 493537778146 ps
CPU time 326.63 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:23:54 PM PDT 24
Peak memory 201752 kb
Host smart-0cbd7e5d-281e-4d96-879a-a0dee3a2f13a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600816985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3600816985
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3424027800
Short name T246
Test name
Test status
Simulation time 164694540083 ps
CPU time 383.73 seconds
Started Jul 16 07:17:52 PM PDT 24
Finished Jul 16 07:24:26 PM PDT 24
Peak memory 201828 kb
Host smart-33392c49-441b-4c85-8ddf-caea082da17a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424027800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3424027800
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2563282865
Short name T86
Test name
Test status
Simulation time 604797045778 ps
CPU time 322.72 seconds
Started Jul 16 07:18:03 PM PDT 24
Finished Jul 16 07:23:55 PM PDT 24
Peak memory 201892 kb
Host smart-663fa720-fa9c-4e28-bd2e-aa1256ee0265
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563282865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2563282865
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.357455097
Short name T54
Test name
Test status
Simulation time 131833456404 ps
CPU time 686.28 seconds
Started Jul 16 07:17:58 PM PDT 24
Finished Jul 16 07:29:46 PM PDT 24
Peak memory 202332 kb
Host smart-8cda4f87-6f64-42f0-9da6-a4c64dd97531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357455097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.357455097
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2101018994
Short name T382
Test name
Test status
Simulation time 34339734170 ps
CPU time 20.9 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:18:43 PM PDT 24
Peak memory 201716 kb
Host smart-fabc4426-e0a1-4124-b551-590915657962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101018994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2101018994
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.946618982
Short name T436
Test name
Test status
Simulation time 3900000141 ps
CPU time 2.67 seconds
Started Jul 16 07:18:04 PM PDT 24
Finished Jul 16 07:18:37 PM PDT 24
Peak memory 201732 kb
Host smart-7494c908-46da-4ae3-aa34-970bd5af428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946618982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.946618982
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2064006915
Short name T391
Test name
Test status
Simulation time 5976384477 ps
CPU time 4.72 seconds
Started Jul 16 07:17:51 PM PDT 24
Finished Jul 16 07:18:03 PM PDT 24
Peak memory 201644 kb
Host smart-ff9113a8-94c2-4fa2-b2a9-2ac0d744689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064006915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2064006915
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2035202275
Short name T750
Test name
Test status
Simulation time 419102784 ps
CPU time 1.03 seconds
Started Jul 16 07:18:05 PM PDT 24
Finished Jul 16 07:18:36 PM PDT 24
Peak memory 201660 kb
Host smart-43cc4598-6c2c-49e9-b735-d9d247d4401d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035202275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2035202275
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1249148889
Short name T179
Test name
Test status
Simulation time 332451788588 ps
CPU time 163.01 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:21:09 PM PDT 24
Peak memory 201912 kb
Host smart-77cf6e8e-accb-40e3-9a08-912f3f2cc59c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249148889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1249148889
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.33799383
Short name T709
Test name
Test status
Simulation time 191347792142 ps
CPU time 118.08 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:20:25 PM PDT 24
Peak memory 201924 kb
Host smart-02b19663-faf8-4461-ba88-f690fd8656b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33799383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.33799383
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3851577331
Short name T536
Test name
Test status
Simulation time 164704158055 ps
CPU time 363.08 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:24:31 PM PDT 24
Peak memory 201968 kb
Host smart-3c7b9451-4bba-4a51-87e0-613434223242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851577331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3851577331
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.4122493009
Short name T619
Test name
Test status
Simulation time 168725601880 ps
CPU time 106.9 seconds
Started Jul 16 07:17:58 PM PDT 24
Finished Jul 16 07:20:07 PM PDT 24
Peak memory 201884 kb
Host smart-fdc8f1c4-1b97-438c-8c64-6390c74cd0b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122493009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.4122493009
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2334955653
Short name T340
Test name
Test status
Simulation time 322383590189 ps
CPU time 172.67 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:21:19 PM PDT 24
Peak memory 201908 kb
Host smart-6576aa94-6341-4271-8d1e-99656a13790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334955653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2334955653
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.472695703
Short name T399
Test name
Test status
Simulation time 328013432179 ps
CPU time 182.32 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:21:28 PM PDT 24
Peak memory 201892 kb
Host smart-5f6fe22c-7256-4da3-a4e5-4fa109515d90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=472695703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.472695703
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2249711908
Short name T615
Test name
Test status
Simulation time 202349879762 ps
CPU time 456.07 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:26:23 PM PDT 24
Peak memory 201780 kb
Host smart-4cefd12a-59a7-42fc-b870-8f75d71a4ab3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249711908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2249711908
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1065879638
Short name T55
Test name
Test status
Simulation time 92236144655 ps
CPU time 472.33 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:26:22 PM PDT 24
Peak memory 202280 kb
Host smart-c9077b5e-8a74-4d1a-86bc-2b7a0a897a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065879638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1065879638
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.458526898
Short name T461
Test name
Test status
Simulation time 41894756070 ps
CPU time 90.17 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:19:58 PM PDT 24
Peak memory 201700 kb
Host smart-af1b0a34-04d9-4e3d-b09f-bfacc6d348ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458526898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.458526898
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1357354318
Short name T480
Test name
Test status
Simulation time 3221388463 ps
CPU time 8.09 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:18:36 PM PDT 24
Peak memory 201720 kb
Host smart-5f9b9159-e301-42a6-aa12-3fe8566c1139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357354318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1357354318
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.391148555
Short name T370
Test name
Test status
Simulation time 5906299953 ps
CPU time 13.43 seconds
Started Jul 16 07:18:07 PM PDT 24
Finished Jul 16 07:18:52 PM PDT 24
Peak memory 201632 kb
Host smart-895f4f81-dddd-4eda-a748-6ad209fc0f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391148555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.391148555
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3839999387
Short name T599
Test name
Test status
Simulation time 176509272599 ps
CPU time 104.82 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:20:32 PM PDT 24
Peak memory 201816 kb
Host smart-511799b7-f9d0-4dea-adc9-b36c27cec81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839999387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3839999387
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1227729859
Short name T20
Test name
Test status
Simulation time 17666766848 ps
CPU time 45.84 seconds
Started Jul 16 07:18:07 PM PDT 24
Finished Jul 16 07:19:25 PM PDT 24
Peak memory 210456 kb
Host smart-78437ab5-4e40-45ea-994d-9cab62b690ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227729859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1227729859
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1041868208
Short name T766
Test name
Test status
Simulation time 306320607 ps
CPU time 0.96 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:18:23 PM PDT 24
Peak memory 201644 kb
Host smart-97abae3c-d07a-43e5-b2e0-9a76468bd8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041868208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1041868208
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3615883485
Short name T740
Test name
Test status
Simulation time 330280026897 ps
CPU time 383.33 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:24:53 PM PDT 24
Peak memory 201876 kb
Host smart-26ee2eb7-ec4f-4f47-aa43-efb1f531b33b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615883485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3615883485
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3233732415
Short name T495
Test name
Test status
Simulation time 163694884814 ps
CPU time 78.85 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:19:46 PM PDT 24
Peak memory 201828 kb
Host smart-a00ed71b-0592-4f9b-9dd1-41ce53b8bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233732415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3233732415
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3912840587
Short name T767
Test name
Test status
Simulation time 489201394639 ps
CPU time 1060.96 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:36:03 PM PDT 24
Peak memory 201912 kb
Host smart-b7a76081-231e-438d-a51d-a197886ff91a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912840587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3912840587
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1681835886
Short name T737
Test name
Test status
Simulation time 335034438710 ps
CPU time 696.81 seconds
Started Jul 16 07:17:58 PM PDT 24
Finished Jul 16 07:29:59 PM PDT 24
Peak memory 201964 kb
Host smart-78ba55d2-5081-42c1-8b7f-dbf051653629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681835886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1681835886
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.771396160
Short name T665
Test name
Test status
Simulation time 156249511450 ps
CPU time 282.48 seconds
Started Jul 16 07:18:08 PM PDT 24
Finished Jul 16 07:23:22 PM PDT 24
Peak memory 201820 kb
Host smart-4a411d87-fd78-481d-a90f-7da9362540d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=771396160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.771396160
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2643272012
Short name T607
Test name
Test status
Simulation time 196810047342 ps
CPU time 115.36 seconds
Started Jul 16 07:18:02 PM PDT 24
Finished Jul 16 07:20:25 PM PDT 24
Peak memory 201924 kb
Host smart-1f073286-a04f-4ed8-9b2e-7bc613767178
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643272012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2643272012
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1292037237
Short name T617
Test name
Test status
Simulation time 74703913522 ps
CPU time 388.99 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:24:58 PM PDT 24
Peak memory 202212 kb
Host smart-d50cd7b4-cf28-4354-9370-2e771d17fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292037237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1292037237
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1118747367
Short name T49
Test name
Test status
Simulation time 45661943770 ps
CPU time 23.78 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:18:51 PM PDT 24
Peak memory 201720 kb
Host smart-be29b98e-7cf0-47be-acd0-4d1e36c99983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118747367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1118747367
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3444057600
Short name T438
Test name
Test status
Simulation time 4891354307 ps
CPU time 12.08 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:18:34 PM PDT 24
Peak memory 201652 kb
Host smart-4d1a18c8-8538-481e-8ec5-342aeb95dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444057600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3444057600
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.410474716
Short name T353
Test name
Test status
Simulation time 5604040310 ps
CPU time 3.61 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:18:26 PM PDT 24
Peak memory 201896 kb
Host smart-ef0fa9e3-f1d4-4c12-b1a0-65424bc4f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410474716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.410474716
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2664435301
Short name T258
Test name
Test status
Simulation time 358660862291 ps
CPU time 125.11 seconds
Started Jul 16 07:18:05 PM PDT 24
Finished Jul 16 07:20:40 PM PDT 24
Peak memory 201888 kb
Host smart-c5b9b6b6-8d3d-4920-bc57-bd5ed6644aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664435301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2664435301
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2616343827
Short name T38
Test name
Test status
Simulation time 37683264928 ps
CPU time 86.18 seconds
Started Jul 16 07:18:07 PM PDT 24
Finished Jul 16 07:20:05 PM PDT 24
Peak memory 210136 kb
Host smart-7c869a80-3696-4369-b453-71112995c766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616343827 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2616343827
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1469825766
Short name T573
Test name
Test status
Simulation time 479811413 ps
CPU time 0.68 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:17:05 PM PDT 24
Peak memory 201652 kb
Host smart-8e8b81e4-8522-4344-9ac7-48e6b00ef808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469825766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1469825766
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1314299733
Short name T156
Test name
Test status
Simulation time 517867401224 ps
CPU time 188.13 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:20:14 PM PDT 24
Peak memory 201924 kb
Host smart-47a8871b-c893-4051-957d-0124f250d69a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314299733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1314299733
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3635907887
Short name T351
Test name
Test status
Simulation time 164119844897 ps
CPU time 117 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:19:03 PM PDT 24
Peak memory 201940 kb
Host smart-ce0127fd-4ab2-4815-a1a4-d0c5d032b30e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635907887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3635907887
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4118861707
Short name T338
Test name
Test status
Simulation time 161525134243 ps
CPU time 171 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:19:55 PM PDT 24
Peak memory 201880 kb
Host smart-abc583a2-ea69-46bd-82eb-ec5c0fee3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118861707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4118861707
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.461106631
Short name T510
Test name
Test status
Simulation time 486062249554 ps
CPU time 1180.28 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:36:44 PM PDT 24
Peak memory 201792 kb
Host smart-72d99ef9-b967-4cba-85f6-dae11e13459f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=461106631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.461106631
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2330114649
Short name T163
Test name
Test status
Simulation time 174596375554 ps
CPU time 193.91 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:20:18 PM PDT 24
Peak memory 201964 kb
Host smart-22aeed51-87e8-4b49-ad97-a222244178ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330114649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2330114649
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2533530210
Short name T471
Test name
Test status
Simulation time 409583656494 ps
CPU time 930.83 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:32:35 PM PDT 24
Peak memory 201872 kb
Host smart-b366ace7-42ff-428e-a62a-50e3416813d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533530210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2533530210
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.151900821
Short name T207
Test name
Test status
Simulation time 124429570452 ps
CPU time 434.74 seconds
Started Jul 16 07:16:28 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 202236 kb
Host smart-13e907f6-ec1a-4469-8c13-01de300283ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151900821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.151900821
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.477471708
Short name T789
Test name
Test status
Simulation time 36280713055 ps
CPU time 21.72 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:17:27 PM PDT 24
Peak memory 201672 kb
Host smart-b041c573-bcbd-4545-a0d0-5c6bb5b32834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477471708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.477471708
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1818908308
Short name T4
Test name
Test status
Simulation time 5220657784 ps
CPU time 2.49 seconds
Started Jul 16 07:16:29 PM PDT 24
Finished Jul 16 07:17:09 PM PDT 24
Peak memory 201632 kb
Host smart-31af5bfe-fbfb-4527-83aa-20cea06be5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818908308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1818908308
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.797353795
Short name T69
Test name
Test status
Simulation time 4172846280 ps
CPU time 8.66 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:15 PM PDT 24
Peak memory 217276 kb
Host smart-dac7bc07-ea50-4efe-986b-b5268c834fe1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797353795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.797353795
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1881618045
Short name T444
Test name
Test status
Simulation time 5871737279 ps
CPU time 14.4 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:17:19 PM PDT 24
Peak memory 201684 kb
Host smart-60555747-76dc-4983-8174-9f49d7370b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881618045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1881618045
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3944758217
Short name T318
Test name
Test status
Simulation time 652839912730 ps
CPU time 191.95 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:20:18 PM PDT 24
Peak memory 201904 kb
Host smart-6f3f68fa-0848-43f2-8248-fe0b170eb64d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944758217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3944758217
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3150290229
Short name T787
Test name
Test status
Simulation time 121755246634 ps
CPU time 72.54 seconds
Started Jul 16 07:16:28 PM PDT 24
Finished Jul 16 07:18:18 PM PDT 24
Peak memory 210296 kb
Host smart-a3b15083-fcff-41fb-acbf-a40bc7eee64a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150290229 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3150290229
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2619697313
Short name T627
Test name
Test status
Simulation time 380294658 ps
CPU time 0.74 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:18:52 PM PDT 24
Peak memory 201604 kb
Host smart-8c5b3363-84f5-4072-ab47-41489236ea77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619697313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2619697313
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.475609150
Short name T307
Test name
Test status
Simulation time 525306371216 ps
CPU time 853.51 seconds
Started Jul 16 07:18:07 PM PDT 24
Finished Jul 16 07:32:52 PM PDT 24
Peak memory 201872 kb
Host smart-1196546a-2617-4f0d-bf5e-57a64677825a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475609150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.475609150
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4199384644
Short name T298
Test name
Test status
Simulation time 166548281610 ps
CPU time 346.47 seconds
Started Jul 16 07:17:57 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 201924 kb
Host smart-6ec50ef7-d688-4415-b9f3-cdac7abe4006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199384644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4199384644
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.522212802
Short name T319
Test name
Test status
Simulation time 493846939722 ps
CPU time 105.13 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:20:13 PM PDT 24
Peak memory 201824 kb
Host smart-0e501d1e-ac12-4249-8c9b-dcd0bcd79b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522212802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.522212802
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4070374560
Short name T575
Test name
Test status
Simulation time 323644174238 ps
CPU time 746.78 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:30:49 PM PDT 24
Peak memory 201872 kb
Host smart-f4abbd58-d5d2-4892-b998-efe9ff31d4df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070374560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4070374560
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2570581699
Short name T515
Test name
Test status
Simulation time 164612416867 ps
CPU time 345.55 seconds
Started Jul 16 07:17:59 PM PDT 24
Finished Jul 16 07:24:08 PM PDT 24
Peak memory 201880 kb
Host smart-26da5566-3514-4809-a9e3-a9cf2dd0ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570581699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2570581699
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3391630312
Short name T13
Test name
Test status
Simulation time 502191724328 ps
CPU time 539.76 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:27:26 PM PDT 24
Peak memory 201844 kb
Host smart-f6dc8349-ed32-491a-b8ca-d75ebb6ddd1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391630312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3391630312
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.821691190
Short name T478
Test name
Test status
Simulation time 613327051950 ps
CPU time 390.19 seconds
Started Jul 16 07:18:04 PM PDT 24
Finished Jul 16 07:25:05 PM PDT 24
Peak memory 201868 kb
Host smart-f99e8d24-8cd5-4a10-badd-9ef6fdcda370
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821691190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.821691190
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2526195996
Short name T490
Test name
Test status
Simulation time 71502266858 ps
CPU time 260.31 seconds
Started Jul 16 07:18:00 PM PDT 24
Finished Jul 16 07:22:47 PM PDT 24
Peak memory 202268 kb
Host smart-a6683704-f97e-4453-9838-d883b6241a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526195996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2526195996
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4171559487
Short name T496
Test name
Test status
Simulation time 44310150992 ps
CPU time 100.36 seconds
Started Jul 16 07:18:11 PM PDT 24
Finished Jul 16 07:20:28 PM PDT 24
Peak memory 201332 kb
Host smart-bfb01ff1-a85f-4e69-8f8c-6f84874af44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171559487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4171559487
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1655540551
Short name T484
Test name
Test status
Simulation time 2738865212 ps
CPU time 2.27 seconds
Started Jul 16 07:18:07 PM PDT 24
Finished Jul 16 07:18:41 PM PDT 24
Peak memory 201624 kb
Host smart-f766a8c5-b083-43e8-8682-bfa3ef189029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655540551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1655540551
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2777838091
Short name T417
Test name
Test status
Simulation time 5843354744 ps
CPU time 13.9 seconds
Started Jul 16 07:18:01 PM PDT 24
Finished Jul 16 07:18:42 PM PDT 24
Peak memory 201688 kb
Host smart-b2bd0d8f-3825-47aa-9e24-83c75012f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777838091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2777838091
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3777901743
Short name T690
Test name
Test status
Simulation time 383758935 ps
CPU time 1.09 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:18:56 PM PDT 24
Peak memory 201640 kb
Host smart-bbf15767-191b-4050-ba33-8176d715c398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777901743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3777901743
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3843411154
Short name T304
Test name
Test status
Simulation time 166951398975 ps
CPU time 350.72 seconds
Started Jul 16 07:18:21 PM PDT 24
Finished Jul 16 07:24:50 PM PDT 24
Peak memory 201864 kb
Host smart-a332c86b-60b1-4c47-ab57-9a66788857bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843411154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3843411154
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2040468969
Short name T88
Test name
Test status
Simulation time 491872893433 ps
CPU time 292.89 seconds
Started Jul 16 07:18:14 PM PDT 24
Finished Jul 16 07:23:44 PM PDT 24
Peak memory 201916 kb
Host smart-bd58cc47-d6c1-4a72-8ec4-faf19c09eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040468969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2040468969
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2251215941
Short name T375
Test name
Test status
Simulation time 501104379393 ps
CPU time 1185.31 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:38:40 PM PDT 24
Peak memory 201832 kb
Host smart-ca5c7980-d279-474b-b58a-4e3035b90715
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251215941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2251215941
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1208842392
Short name T164
Test name
Test status
Simulation time 492742976323 ps
CPU time 183.56 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:21:55 PM PDT 24
Peak memory 201932 kb
Host smart-86ce2e90-2206-491a-a4f0-0e511b26e13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208842392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1208842392
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1596077668
Short name T614
Test name
Test status
Simulation time 162976898753 ps
CPU time 379.41 seconds
Started Jul 16 07:18:17 PM PDT 24
Finished Jul 16 07:25:15 PM PDT 24
Peak memory 201832 kb
Host smart-8f833e0e-5959-4f4f-a6d0-0c8edcbd4366
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596077668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1596077668
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3384686118
Short name T790
Test name
Test status
Simulation time 613027653749 ps
CPU time 201.42 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:22:16 PM PDT 24
Peak memory 201916 kb
Host smart-b915da0d-7385-42a8-982d-7b66a899732a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384686118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3384686118
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.665774447
Short name T596
Test name
Test status
Simulation time 585942977001 ps
CPU time 262.77 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:23:18 PM PDT 24
Peak memory 201852 kb
Host smart-b312e92c-4b3a-482a-9b76-baa190d7cfcc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665774447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.665774447
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.327990593
Short name T222
Test name
Test status
Simulation time 122718628350 ps
CPU time 688.74 seconds
Started Jul 16 07:18:14 PM PDT 24
Finished Jul 16 07:30:19 PM PDT 24
Peak memory 202216 kb
Host smart-5b99f98d-f462-4516-a1fb-fa6d259f8089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327990593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.327990593
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3399701064
Short name T581
Test name
Test status
Simulation time 24045747530 ps
CPU time 57.17 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:19:48 PM PDT 24
Peak memory 201632 kb
Host smart-a6fe35c8-c660-49c7-8cc1-52534be5721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399701064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3399701064
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1926979519
Short name T535
Test name
Test status
Simulation time 5608898331 ps
CPU time 12.7 seconds
Started Jul 16 07:18:14 PM PDT 24
Finished Jul 16 07:19:03 PM PDT 24
Peak memory 201712 kb
Host smart-cb13cead-463f-43ed-92d5-ee1c0b5a5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926979519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1926979519
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.61375035
Short name T764
Test name
Test status
Simulation time 5555061176 ps
CPU time 12.65 seconds
Started Jul 16 07:18:17 PM PDT 24
Finished Jul 16 07:19:08 PM PDT 24
Peak memory 201712 kb
Host smart-5efbe471-9c4a-45cb-965f-966137cf8b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61375035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.61375035
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3816645659
Short name T470
Test name
Test status
Simulation time 416903922585 ps
CPU time 344.43 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:24:36 PM PDT 24
Peak memory 201912 kb
Host smart-18e801a9-8e18-49c0-a4d9-635713c0c4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816645659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3816645659
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1590576995
Short name T41
Test name
Test status
Simulation time 98924410054 ps
CPU time 355.72 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:24:50 PM PDT 24
Peak memory 217352 kb
Host smart-ae15f1a6-4d45-42ea-801e-57ee69bb1737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590576995 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1590576995
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2587885367
Short name T415
Test name
Test status
Simulation time 474916277 ps
CPU time 0.92 seconds
Started Jul 16 07:18:24 PM PDT 24
Finished Jul 16 07:19:04 PM PDT 24
Peak memory 201588 kb
Host smart-b3bc5c7d-4416-4aa8-baca-d9630dbba360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587885367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2587885367
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4236029943
Short name T669
Test name
Test status
Simulation time 163356013060 ps
CPU time 2.63 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:18:53 PM PDT 24
Peak memory 201808 kb
Host smart-3e60ca95-15a8-4f00-817c-70163a51ef0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236029943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4236029943
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4227960807
Short name T385
Test name
Test status
Simulation time 163972689662 ps
CPU time 90 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:20:21 PM PDT 24
Peak memory 201904 kb
Host smart-f7623d31-76e7-49e6-a5a9-e7eb6fd2b2b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227960807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4227960807
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2405204873
Short name T274
Test name
Test status
Simulation time 330781290361 ps
CPU time 183.11 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:21:54 PM PDT 24
Peak memory 201896 kb
Host smart-51d06774-f970-41a2-9099-c34d4d613056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405204873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2405204873
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1444755791
Short name T696
Test name
Test status
Simulation time 330895477075 ps
CPU time 538.32 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:27:49 PM PDT 24
Peak memory 201796 kb
Host smart-f3cbe2c4-20f8-45d8-ac50-b50053ae29e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444755791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1444755791
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.855102832
Short name T166
Test name
Test status
Simulation time 379787100814 ps
CPU time 457.66 seconds
Started Jul 16 07:18:17 PM PDT 24
Finished Jul 16 07:26:33 PM PDT 24
Peak memory 201888 kb
Host smart-5d1bf35d-2c3f-4956-9935-032ce40406ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855102832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.855102832
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1200137990
Short name T403
Test name
Test status
Simulation time 592003427691 ps
CPU time 691.64 seconds
Started Jul 16 07:18:13 PM PDT 24
Finished Jul 16 07:30:22 PM PDT 24
Peak memory 201904 kb
Host smart-6d088ab2-3f7c-4cd1-822c-7c30d30f498b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200137990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1200137990
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2905249651
Short name T589
Test name
Test status
Simulation time 24149741943 ps
CPU time 15.67 seconds
Started Jul 16 07:18:17 PM PDT 24
Finished Jul 16 07:19:11 PM PDT 24
Peak memory 201720 kb
Host smart-d862464b-d8b0-4215-b7ed-c325b68de89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905249651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2905249651
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1421634382
Short name T616
Test name
Test status
Simulation time 4654807919 ps
CPU time 2.39 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:18:56 PM PDT 24
Peak memory 201720 kb
Host smart-2c6c506e-abf2-493a-a719-26262b71bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421634382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1421634382
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2678830995
Short name T758
Test name
Test status
Simulation time 6053132136 ps
CPU time 4.59 seconds
Started Jul 16 07:18:21 PM PDT 24
Finished Jul 16 07:19:03 PM PDT 24
Peak memory 201652 kb
Host smart-367acc51-f43a-454d-bebf-71f77e86c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678830995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2678830995
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1041450776
Short name T570
Test name
Test status
Simulation time 31978384138 ps
CPU time 18.6 seconds
Started Jul 16 07:18:16 PM PDT 24
Finished Jul 16 07:19:13 PM PDT 24
Peak memory 201708 kb
Host smart-be705ae0-e8fa-4ab5-b268-253d8c172680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041450776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1041450776
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2970046027
Short name T24
Test name
Test status
Simulation time 417766225198 ps
CPU time 481.28 seconds
Started Jul 16 07:18:15 PM PDT 24
Finished Jul 16 07:26:52 PM PDT 24
Peak memory 210508 kb
Host smart-af834510-b65a-4da7-9358-ec259a11108e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970046027 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2970046027
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2196197808
Short name T754
Test name
Test status
Simulation time 407437773 ps
CPU time 1.43 seconds
Started Jul 16 07:18:28 PM PDT 24
Finished Jul 16 07:19:10 PM PDT 24
Peak memory 201676 kb
Host smart-e909e942-8cc0-4bea-a3ab-6676afd0ad10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196197808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2196197808
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.491312127
Short name T494
Test name
Test status
Simulation time 175325444555 ps
CPU time 92.18 seconds
Started Jul 16 07:18:25 PM PDT 24
Finished Jul 16 07:20:36 PM PDT 24
Peak memory 201992 kb
Host smart-99d619f0-8320-4302-88cc-e1b169c29f0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491312127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.491312127
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4112931135
Short name T108
Test name
Test status
Simulation time 168513426306 ps
CPU time 399.3 seconds
Started Jul 16 07:18:26 PM PDT 24
Finished Jul 16 07:25:45 PM PDT 24
Peak memory 202144 kb
Host smart-1a2459c2-b28a-46fb-9261-058c54fd351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112931135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4112931135
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3018720524
Short name T389
Test name
Test status
Simulation time 162372765802 ps
CPU time 392.18 seconds
Started Jul 16 07:18:25 PM PDT 24
Finished Jul 16 07:25:36 PM PDT 24
Peak memory 201908 kb
Host smart-08bc87ab-8fd0-45c8-ad44-421d9a4af7f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018720524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3018720524
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2910014746
Short name T146
Test name
Test status
Simulation time 483683785285 ps
CPU time 1052.49 seconds
Started Jul 16 07:18:25 PM PDT 24
Finished Jul 16 07:36:36 PM PDT 24
Peak memory 201916 kb
Host smart-37f1ac6c-0e72-488c-bba5-b0f02ae70305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910014746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2910014746
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2448133814
Short name T595
Test name
Test status
Simulation time 494429373698 ps
CPU time 1157.78 seconds
Started Jul 16 07:18:28 PM PDT 24
Finished Jul 16 07:38:28 PM PDT 24
Peak memory 201828 kb
Host smart-7b4f6b07-db72-4269-bfff-1e50f22134c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448133814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2448133814
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1733322499
Short name T331
Test name
Test status
Simulation time 169963066639 ps
CPU time 385.05 seconds
Started Jul 16 07:18:26 PM PDT 24
Finished Jul 16 07:25:31 PM PDT 24
Peak memory 201924 kb
Host smart-ebe4f708-33ee-4776-a6a9-67f8a0f1504d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733322499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1733322499
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.340266081
Short name T406
Test name
Test status
Simulation time 397538780816 ps
CPU time 466.05 seconds
Started Jul 16 07:18:23 PM PDT 24
Finished Jul 16 07:26:48 PM PDT 24
Peak memory 201932 kb
Host smart-620ed4e3-82ea-4c7f-8f30-a5d32ed0c137
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340266081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.340266081
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.79996890
Short name T552
Test name
Test status
Simulation time 85964966280 ps
CPU time 338.01 seconds
Started Jul 16 07:18:32 PM PDT 24
Finished Jul 16 07:24:54 PM PDT 24
Peak memory 202176 kb
Host smart-dd68f418-4a58-431e-a2ce-b52f5e07956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79996890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.79996890
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3754484379
Short name T543
Test name
Test status
Simulation time 39621342438 ps
CPU time 95.9 seconds
Started Jul 16 07:18:28 PM PDT 24
Finished Jul 16 07:20:44 PM PDT 24
Peak memory 201664 kb
Host smart-a8f8ef26-5484-4f65-bced-179043a27ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754484379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3754484379
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.200761759
Short name T733
Test name
Test status
Simulation time 4318004506 ps
CPU time 10.93 seconds
Started Jul 16 07:18:25 PM PDT 24
Finished Jul 16 07:19:15 PM PDT 24
Peak memory 201724 kb
Host smart-e3685062-5824-4d28-befb-4b727a48d206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200761759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.200761759
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.519319183
Short name T532
Test name
Test status
Simulation time 5823543154 ps
CPU time 12.79 seconds
Started Jul 16 07:18:27 PM PDT 24
Finished Jul 16 07:19:19 PM PDT 24
Peak memory 201740 kb
Host smart-98108c1b-a923-4b83-9c76-766c91ec88d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519319183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.519319183
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.396339829
Short name T333
Test name
Test status
Simulation time 463139934679 ps
CPU time 1268.02 seconds
Started Jul 16 07:18:25 PM PDT 24
Finished Jul 16 07:40:14 PM PDT 24
Peak memory 210368 kb
Host smart-8b1ec7c7-ab64-4a05-932d-6f9adb1e056d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396339829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
396339829
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4238201818
Short name T283
Test name
Test status
Simulation time 209687850957 ps
CPU time 243.75 seconds
Started Jul 16 07:18:25 PM PDT 24
Finished Jul 16 07:23:07 PM PDT 24
Peak memory 210240 kb
Host smart-50ad4997-671a-4e6d-a0e3-c32f7c984705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238201818 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4238201818
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1051461462
Short name T551
Test name
Test status
Simulation time 356010398 ps
CPU time 1.3 seconds
Started Jul 16 07:18:50 PM PDT 24
Finished Jul 16 07:19:41 PM PDT 24
Peak memory 201592 kb
Host smart-f5a83950-be78-4472-b20a-25ddc83e18fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051461462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1051461462
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.100836211
Short name T344
Test name
Test status
Simulation time 349247647625 ps
CPU time 430.04 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:26:35 PM PDT 24
Peak memory 201948 kb
Host smart-a500cb26-a39d-47ef-a74b-3d9bb81b6ba5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100836211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.100836211
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3661186041
Short name T291
Test name
Test status
Simulation time 521865053738 ps
CPU time 289.58 seconds
Started Jul 16 07:18:49 PM PDT 24
Finished Jul 16 07:24:29 PM PDT 24
Peak memory 201840 kb
Host smart-0c086973-e050-418b-8f31-6765176b8b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661186041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3661186041
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2082346954
Short name T250
Test name
Test status
Simulation time 486608794365 ps
CPU time 1083.2 seconds
Started Jul 16 07:18:33 PM PDT 24
Finished Jul 16 07:37:19 PM PDT 24
Peak memory 201816 kb
Host smart-a684e39d-de7c-4da7-a1c0-f73e378b860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082346954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2082346954
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4064807324
Short name T598
Test name
Test status
Simulation time 327587991060 ps
CPU time 281.76 seconds
Started Jul 16 07:18:28 PM PDT 24
Finished Jul 16 07:23:51 PM PDT 24
Peak memory 201816 kb
Host smart-09b5efa6-f8c5-4d7e-ab61-2cf27eccc27f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064807324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4064807324
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1873672674
Short name T308
Test name
Test status
Simulation time 493764661128 ps
CPU time 282.96 seconds
Started Jul 16 07:18:27 PM PDT 24
Finished Jul 16 07:23:49 PM PDT 24
Peak memory 202148 kb
Host smart-de27be5a-bf41-47fb-80df-4011bcd8e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873672674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1873672674
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.400117422
Short name T647
Test name
Test status
Simulation time 485462561779 ps
CPU time 1141.88 seconds
Started Jul 16 07:18:28 PM PDT 24
Finished Jul 16 07:38:12 PM PDT 24
Peak memory 201940 kb
Host smart-f9ca3951-21bc-4aed-b39a-c3502d4e0caa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=400117422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.400117422
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1679698559
Short name T430
Test name
Test status
Simulation time 205681242580 ps
CPU time 416.7 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:26:22 PM PDT 24
Peak memory 201908 kb
Host smart-10e58603-4b9a-493c-865e-2f4e96a2b18e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679698559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1679698559
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1782656188
Short name T500
Test name
Test status
Simulation time 67578130513 ps
CPU time 385.22 seconds
Started Jul 16 07:18:40 PM PDT 24
Finished Jul 16 07:25:51 PM PDT 24
Peak memory 202280 kb
Host smart-4f6d1147-3874-400c-8cc7-77b4c09a48dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782656188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1782656188
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3184839141
Short name T574
Test name
Test status
Simulation time 40914909707 ps
CPU time 5.75 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:19:31 PM PDT 24
Peak memory 201720 kb
Host smart-9a6b1709-5655-4b4d-8b1c-6b6777f9194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184839141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3184839141
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.62708705
Short name T441
Test name
Test status
Simulation time 4129375047 ps
CPU time 5.17 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:19:30 PM PDT 24
Peak memory 201696 kb
Host smart-80e1e9b4-46c3-4b9a-9786-ffdc070317e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62708705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.62708705
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4248643265
Short name T624
Test name
Test status
Simulation time 5617225743 ps
CPU time 14.28 seconds
Started Jul 16 07:18:27 PM PDT 24
Finished Jul 16 07:19:23 PM PDT 24
Peak memory 201616 kb
Host smart-79f49180-42bd-469e-9233-63e1983fd827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248643265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4248643265
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4142555642
Short name T641
Test name
Test status
Simulation time 469041953023 ps
CPU time 1396.51 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:42:42 PM PDT 24
Peak memory 218548 kb
Host smart-c83b2996-e57b-4668-aea2-94715d028d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142555642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4142555642
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.296217806
Short name T51
Test name
Test status
Simulation time 167068132567 ps
CPU time 178.12 seconds
Started Jul 16 07:18:50 PM PDT 24
Finished Jul 16 07:22:36 PM PDT 24
Peak memory 217724 kb
Host smart-3811cee8-6ec4-4142-9cff-215ca2bf6ca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296217806 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.296217806
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.4134463964
Short name T499
Test name
Test status
Simulation time 378200161 ps
CPU time 1.46 seconds
Started Jul 16 07:18:58 PM PDT 24
Finished Jul 16 07:19:51 PM PDT 24
Peak memory 201668 kb
Host smart-5d921073-8df1-457c-9b12-b74707b1c029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134463964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4134463964
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1795026189
Short name T113
Test name
Test status
Simulation time 169650041866 ps
CPU time 321.61 seconds
Started Jul 16 07:18:48 PM PDT 24
Finished Jul 16 07:25:01 PM PDT 24
Peak memory 201844 kb
Host smart-19506acc-8751-42cb-ab26-f41dc7ff3474
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795026189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1795026189
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1100469862
Short name T279
Test name
Test status
Simulation time 165205278900 ps
CPU time 189.64 seconds
Started Jul 16 07:18:51 PM PDT 24
Finished Jul 16 07:22:52 PM PDT 24
Peak memory 201896 kb
Host smart-08ea9c74-9eb9-4ce2-819a-8d4dfad7a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100469862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1100469862
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.489556967
Short name T305
Test name
Test status
Simulation time 497243132197 ps
CPU time 222.64 seconds
Started Jul 16 07:18:48 PM PDT 24
Finished Jul 16 07:23:22 PM PDT 24
Peak memory 201828 kb
Host smart-1e2d729b-3652-47b6-868f-f53cbad08755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489556967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.489556967
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1324126463
Short name T184
Test name
Test status
Simulation time 489007500179 ps
CPU time 278.32 seconds
Started Jul 16 07:18:38 PM PDT 24
Finished Jul 16 07:24:04 PM PDT 24
Peak memory 201852 kb
Host smart-7c09a2cb-18a1-4529-a51b-4295d0e08b30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324126463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1324126463
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.26765487
Short name T293
Test name
Test status
Simulation time 335222987445 ps
CPU time 479.17 seconds
Started Jul 16 07:18:39 PM PDT 24
Finished Jul 16 07:27:25 PM PDT 24
Peak memory 201912 kb
Host smart-73f1a50d-8ecf-4b37-b462-d9c670088751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26765487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.26765487
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4025619986
Short name T763
Test name
Test status
Simulation time 156430059655 ps
CPU time 94.91 seconds
Started Jul 16 07:18:37 PM PDT 24
Finished Jul 16 07:20:59 PM PDT 24
Peak memory 201876 kb
Host smart-b4e78375-c3a6-43ba-a0cf-1a6bb51eb27d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025619986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4025619986
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1127929425
Short name T150
Test name
Test status
Simulation time 202714665413 ps
CPU time 36.91 seconds
Started Jul 16 07:18:49 PM PDT 24
Finished Jul 16 07:20:15 PM PDT 24
Peak memory 201828 kb
Host smart-4f0488c6-1b36-446e-b5ee-4abbf874c2c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127929425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1127929425
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.982987401
Short name T103
Test name
Test status
Simulation time 122823201520 ps
CPU time 438.41 seconds
Started Jul 16 07:18:51 PM PDT 24
Finished Jul 16 07:27:01 PM PDT 24
Peak memory 202224 kb
Host smart-cfe88a0d-2c59-4696-9038-755697055c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982987401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.982987401
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2115852311
Short name T479
Test name
Test status
Simulation time 34658246723 ps
CPU time 78.16 seconds
Started Jul 16 07:18:52 PM PDT 24
Finished Jul 16 07:21:00 PM PDT 24
Peak memory 201724 kb
Host smart-50847d91-e6c9-4eb4-81dc-5d53fcb2b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115852311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2115852311
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3394134699
Short name T675
Test name
Test status
Simulation time 3756139696 ps
CPU time 9.72 seconds
Started Jul 16 07:19:43 PM PDT 24
Finished Jul 16 07:20:48 PM PDT 24
Peak memory 201644 kb
Host smart-73a75850-ea53-4143-afb7-0fc680ade362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394134699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3394134699
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.874460538
Short name T469
Test name
Test status
Simulation time 5742328093 ps
CPU time 13.11 seconds
Started Jul 16 07:18:39 PM PDT 24
Finished Jul 16 07:19:38 PM PDT 24
Peak memory 201656 kb
Host smart-1e0a5f4d-f5d1-4968-a348-79bd71f51bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874460538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.874460538
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2282228922
Short name T264
Test name
Test status
Simulation time 161965188920 ps
CPU time 29.86 seconds
Started Jul 16 07:18:52 PM PDT 24
Finished Jul 16 07:20:11 PM PDT 24
Peak memory 201920 kb
Host smart-698d40be-1136-4c98-aa4e-999782bc5ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282228922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2282228922
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.726189698
Short name T34
Test name
Test status
Simulation time 7308590989 ps
CPU time 19.05 seconds
Started Jul 16 07:18:52 PM PDT 24
Finished Jul 16 07:20:02 PM PDT 24
Peak memory 201784 kb
Host smart-89ed8a3b-b38a-41bb-8d62-2a174828b958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726189698 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.726189698
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2174468349
Short name T75
Test name
Test status
Simulation time 402645765 ps
CPU time 0.88 seconds
Started Jul 16 07:19:04 PM PDT 24
Finished Jul 16 07:19:55 PM PDT 24
Peak memory 201620 kb
Host smart-9eee8966-7dbf-4984-883d-cc223407675c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174468349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2174468349
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1380961788
Short name T321
Test name
Test status
Simulation time 350767931706 ps
CPU time 199.1 seconds
Started Jul 16 07:18:58 PM PDT 24
Finished Jul 16 07:23:08 PM PDT 24
Peak memory 201976 kb
Host smart-35097f06-7353-4b4c-9a05-4cae4a100a21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380961788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1380961788
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1071130741
Short name T325
Test name
Test status
Simulation time 552456183647 ps
CPU time 337.4 seconds
Started Jul 16 07:18:57 PM PDT 24
Finished Jul 16 07:25:26 PM PDT 24
Peak memory 201840 kb
Host smart-bc26484d-6a55-4ab3-a94f-0e3f0dc485ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071130741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1071130741
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1412080047
Short name T579
Test name
Test status
Simulation time 495313560985 ps
CPU time 237.73 seconds
Started Jul 16 07:18:53 PM PDT 24
Finished Jul 16 07:23:42 PM PDT 24
Peak memory 201888 kb
Host smart-8fe3da92-d104-405d-bbcf-d4cbf71fb74a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412080047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1412080047
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1445522841
Short name T228
Test name
Test status
Simulation time 483675683707 ps
CPU time 260.34 seconds
Started Jul 16 07:18:57 PM PDT 24
Finished Jul 16 07:24:09 PM PDT 24
Peak memory 201928 kb
Host smart-222d9e46-800e-4df5-86ab-3f60b60e17e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445522841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1445522841
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1015884863
Short name T433
Test name
Test status
Simulation time 164701277279 ps
CPU time 55.26 seconds
Started Jul 16 07:18:52 PM PDT 24
Finished Jul 16 07:20:38 PM PDT 24
Peak memory 201856 kb
Host smart-4fe8993e-a974-46f2-a6a5-905ab0602da4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015884863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1015884863
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2948061955
Short name T736
Test name
Test status
Simulation time 188216955263 ps
CPU time 275.25 seconds
Started Jul 16 07:18:57 PM PDT 24
Finished Jul 16 07:24:21 PM PDT 24
Peak memory 201912 kb
Host smart-e2c96c2b-3611-4ab9-8974-48877ac7b6b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948061955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2948061955
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3171084167
Short name T658
Test name
Test status
Simulation time 381533998607 ps
CPU time 66.21 seconds
Started Jul 16 07:18:57 PM PDT 24
Finished Jul 16 07:20:53 PM PDT 24
Peak memory 201900 kb
Host smart-a83facff-7489-4572-a5d4-8e58a235ee79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171084167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3171084167
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3445075024
Short name T561
Test name
Test status
Simulation time 44212377066 ps
CPU time 50.36 seconds
Started Jul 16 07:18:57 PM PDT 24
Finished Jul 16 07:20:39 PM PDT 24
Peak memory 201636 kb
Host smart-7a144908-1cf5-4bda-8daa-b5c05f9b6355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445075024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3445075024
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.130087603
Short name T411
Test name
Test status
Simulation time 5188940198 ps
CPU time 11.9 seconds
Started Jul 16 07:18:51 PM PDT 24
Finished Jul 16 07:19:54 PM PDT 24
Peak memory 201660 kb
Host smart-b9a2697a-a488-4217-8f9e-a067dcbb2509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130087603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.130087603
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.227555050
Short name T606
Test name
Test status
Simulation time 6010944312 ps
CPU time 4.75 seconds
Started Jul 16 07:18:50 PM PDT 24
Finished Jul 16 07:19:47 PM PDT 24
Peak memory 201644 kb
Host smart-a3cee771-f4cd-4d9e-a58a-3fbc07397577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227555050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.227555050
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3801325588
Short name T53
Test name
Test status
Simulation time 173147264547 ps
CPU time 464.63 seconds
Started Jul 16 07:19:05 PM PDT 24
Finished Jul 16 07:27:44 PM PDT 24
Peak memory 202212 kb
Host smart-82cab544-0506-4613-b6b3-8ddae6cbcadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801325588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3801325588
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3208591500
Short name T694
Test name
Test status
Simulation time 329881599 ps
CPU time 1.29 seconds
Started Jul 16 07:19:06 PM PDT 24
Finished Jul 16 07:20:01 PM PDT 24
Peak memory 201640 kb
Host smart-e8eb9450-14e4-41c6-a158-6ed7704c615a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208591500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3208591500
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4007185439
Short name T748
Test name
Test status
Simulation time 361566900214 ps
CPU time 760.6 seconds
Started Jul 16 07:19:05 PM PDT 24
Finished Jul 16 07:32:40 PM PDT 24
Peak memory 201908 kb
Host smart-699e756f-79a7-4d3e-9dad-7c71a3fc1dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007185439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4007185439
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4198963944
Short name T409
Test name
Test status
Simulation time 334158230593 ps
CPU time 724.45 seconds
Started Jul 16 07:19:06 PM PDT 24
Finished Jul 16 07:32:07 PM PDT 24
Peak memory 202084 kb
Host smart-36ec5ea3-ec0d-4f9c-851c-c970546e7719
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198963944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4198963944
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.790227844
Short name T1
Test name
Test status
Simulation time 493504603209 ps
CPU time 293.99 seconds
Started Jul 16 07:19:06 PM PDT 24
Finished Jul 16 07:24:55 PM PDT 24
Peak memory 201892 kb
Host smart-39c76171-977a-4c55-8144-0bff49a91e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790227844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.790227844
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1837868570
Short name T663
Test name
Test status
Simulation time 165203295599 ps
CPU time 57.37 seconds
Started Jul 16 07:19:04 PM PDT 24
Finished Jul 16 07:20:57 PM PDT 24
Peak memory 201892 kb
Host smart-f94bf360-ade2-4537-8e81-eff99e4b772e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837868570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1837868570
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1111720540
Short name T556
Test name
Test status
Simulation time 419031440468 ps
CPU time 218.19 seconds
Started Jul 16 07:19:06 PM PDT 24
Finished Jul 16 07:23:41 PM PDT 24
Peak memory 201920 kb
Host smart-1aefb56b-7fbc-4b16-95b8-bde0d3b970c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111720540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1111720540
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1626077179
Short name T223
Test name
Test status
Simulation time 116939134601 ps
CPU time 465.81 seconds
Started Jul 16 07:19:05 PM PDT 24
Finished Jul 16 07:27:46 PM PDT 24
Peak memory 202452 kb
Host smart-0a72794c-8604-4723-88ea-e7f5040b7eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626077179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1626077179
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1637104409
Short name T545
Test name
Test status
Simulation time 34757071555 ps
CPU time 18.67 seconds
Started Jul 16 07:19:05 PM PDT 24
Finished Jul 16 07:20:18 PM PDT 24
Peak memory 201704 kb
Host smart-7787750b-a927-4d86-bc93-50d3c5171bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637104409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1637104409
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3792083264
Short name T99
Test name
Test status
Simulation time 3382585900 ps
CPU time 2.52 seconds
Started Jul 16 07:19:06 PM PDT 24
Finished Jul 16 07:20:04 PM PDT 24
Peak memory 201696 kb
Host smart-ffc9b584-5f41-411d-a26f-572f87cb4fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792083264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3792083264
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3972614212
Short name T683
Test name
Test status
Simulation time 6185193840 ps
CPU time 3.93 seconds
Started Jul 16 07:19:05 PM PDT 24
Finished Jul 16 07:20:04 PM PDT 24
Peak memory 201676 kb
Host smart-3797b591-0215-49fb-b71a-27d1bdbd0313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972614212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3972614212
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3935463260
Short name T216
Test name
Test status
Simulation time 127829906411 ps
CPU time 495.4 seconds
Started Jul 16 07:19:07 PM PDT 24
Finished Jul 16 07:28:18 PM PDT 24
Peak memory 202156 kb
Host smart-1b49db22-2e5b-40da-a203-cfa11ddb6998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935463260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3935463260
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2603993849
Short name T192
Test name
Test status
Simulation time 499185238 ps
CPU time 1.65 seconds
Started Jul 16 07:19:20 PM PDT 24
Finished Jul 16 07:20:20 PM PDT 24
Peak memory 201588 kb
Host smart-74f23e4f-229c-42a5-ace2-2af9013483de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603993849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2603993849
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2599817861
Short name T178
Test name
Test status
Simulation time 335324503922 ps
CPU time 47.46 seconds
Started Jul 16 07:19:17 PM PDT 24
Finished Jul 16 07:21:05 PM PDT 24
Peak memory 201912 kb
Host smart-b43b31be-7627-49a4-8c26-a3f53e8f8451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599817861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2599817861
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1070886789
Short name T33
Test name
Test status
Simulation time 326340183493 ps
CPU time 169.28 seconds
Started Jul 16 07:19:16 PM PDT 24
Finished Jul 16 07:23:01 PM PDT 24
Peak memory 201880 kb
Host smart-2365cd36-3c4a-483d-b498-1808e9430a92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070886789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1070886789
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4283000866
Short name T336
Test name
Test status
Simulation time 169424141025 ps
CPU time 68.04 seconds
Started Jul 16 07:19:18 PM PDT 24
Finished Jul 16 07:21:26 PM PDT 24
Peak memory 201912 kb
Host smart-7b70f7e6-14a3-44b4-865f-18acea8ebfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283000866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4283000866
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3528200564
Short name T544
Test name
Test status
Simulation time 160560246982 ps
CPU time 27.24 seconds
Started Jul 16 07:19:19 PM PDT 24
Finished Jul 16 07:20:44 PM PDT 24
Peak memory 201876 kb
Host smart-79ef11bc-0d07-43d1-a5d6-2a6ac562886c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528200564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3528200564
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2277536048
Short name T313
Test name
Test status
Simulation time 186965560362 ps
CPU time 394.04 seconds
Started Jul 16 07:19:18 PM PDT 24
Finished Jul 16 07:26:52 PM PDT 24
Peak memory 201924 kb
Host smart-cfccc202-9e63-4a8b-bedf-f340d7fbbd27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277536048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2277536048
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3331989431
Short name T360
Test name
Test status
Simulation time 391545550208 ps
CPU time 480.68 seconds
Started Jul 16 07:19:17 PM PDT 24
Finished Jul 16 07:28:18 PM PDT 24
Peak memory 201872 kb
Host smart-472b8f82-ac98-4ea5-a345-994f74a4cfd5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331989431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3331989431
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3100956352
Short name T211
Test name
Test status
Simulation time 125823194660 ps
CPU time 550.48 seconds
Started Jul 16 07:19:16 PM PDT 24
Finished Jul 16 07:29:27 PM PDT 24
Peak memory 202228 kb
Host smart-0908acf0-eae7-4238-b82e-c85e827d7dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100956352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3100956352
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3312912270
Short name T645
Test name
Test status
Simulation time 45658334069 ps
CPU time 24.3 seconds
Started Jul 16 07:19:19 PM PDT 24
Finished Jul 16 07:20:43 PM PDT 24
Peak memory 201716 kb
Host smart-93e8dee4-5e80-4136-824b-29c9afb98c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312912270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3312912270
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4275031387
Short name T452
Test name
Test status
Simulation time 3588002363 ps
CPU time 4.99 seconds
Started Jul 16 07:19:19 PM PDT 24
Finished Jul 16 07:20:24 PM PDT 24
Peak memory 201660 kb
Host smart-df85d1f8-8cee-4927-ac77-e3b810257d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275031387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4275031387
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3321174910
Short name T410
Test name
Test status
Simulation time 6047756038 ps
CPU time 13.97 seconds
Started Jul 16 07:19:19 PM PDT 24
Finished Jul 16 07:20:32 PM PDT 24
Peak memory 201728 kb
Host smart-e993ed9e-7ad1-4c1c-b8da-d00b47656007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321174910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3321174910
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1091233018
Short name T464
Test name
Test status
Simulation time 207235900553 ps
CPU time 232.63 seconds
Started Jul 16 07:19:18 PM PDT 24
Finished Jul 16 07:24:11 PM PDT 24
Peak memory 201884 kb
Host smart-460d41a6-7077-429d-a6ca-2406bdf0c07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091233018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1091233018
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1909942068
Short name T765
Test name
Test status
Simulation time 119558064795 ps
CPU time 167.44 seconds
Started Jul 16 07:19:19 PM PDT 24
Finished Jul 16 07:23:04 PM PDT 24
Peak memory 210544 kb
Host smart-b1109e04-16c7-46f4-8e55-d613c504a6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909942068 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1909942068
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1101692863
Short name T784
Test name
Test status
Simulation time 489251891 ps
CPU time 0.87 seconds
Started Jul 16 07:19:34 PM PDT 24
Finished Jul 16 07:20:33 PM PDT 24
Peak memory 201672 kb
Host smart-e6accba2-cfd4-451e-a1a5-99211cd944c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101692863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1101692863
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1446281463
Short name T413
Test name
Test status
Simulation time 177255781612 ps
CPU time 107 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:22:16 PM PDT 24
Peak memory 201972 kb
Host smart-500566c0-bdf9-4930-bdc7-5b819a69e242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446281463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1446281463
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2414596603
Short name T637
Test name
Test status
Simulation time 340229098009 ps
CPU time 426.45 seconds
Started Jul 16 07:19:33 PM PDT 24
Finished Jul 16 07:27:38 PM PDT 24
Peak memory 201992 kb
Host smart-78d7b1c9-2b89-41c9-8943-b5e0d011e7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414596603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2414596603
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1749790078
Short name T341
Test name
Test status
Simulation time 330044615899 ps
CPU time 781.6 seconds
Started Jul 16 07:19:31 PM PDT 24
Finished Jul 16 07:33:32 PM PDT 24
Peak memory 201964 kb
Host smart-88f3033d-5a90-4e29-b1a9-6738f72166db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749790078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1749790078
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2582450070
Short name T459
Test name
Test status
Simulation time 493157054449 ps
CPU time 322.31 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:25:51 PM PDT 24
Peak memory 201928 kb
Host smart-8613290f-a471-4ac7-b6f2-23dc59d801f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582450070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2582450070
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3915880909
Short name T642
Test name
Test status
Simulation time 492245921291 ps
CPU time 1025.95 seconds
Started Jul 16 07:19:18 PM PDT 24
Finished Jul 16 07:37:24 PM PDT 24
Peak memory 201964 kb
Host smart-1578fcef-a47a-495b-bf49-b372ca5ab82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915880909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3915880909
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2533090799
Short name T730
Test name
Test status
Simulation time 161582205720 ps
CPU time 100.66 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:22:10 PM PDT 24
Peak memory 201888 kb
Host smart-5ace6094-bbdd-49f5-afa2-254278071a19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533090799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2533090799
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.583745576
Short name T110
Test name
Test status
Simulation time 348447588748 ps
CPU time 746.13 seconds
Started Jul 16 07:19:29 PM PDT 24
Finished Jul 16 07:32:55 PM PDT 24
Peak memory 201928 kb
Host smart-39a26953-8178-42b8-85f8-dd5f95c222cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583745576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.583745576
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3257321431
Short name T458
Test name
Test status
Simulation time 398806805903 ps
CPU time 222.37 seconds
Started Jul 16 07:19:32 PM PDT 24
Finished Jul 16 07:24:12 PM PDT 24
Peak memory 201912 kb
Host smart-2a194ba2-c623-41e4-932c-f7f77b8ae0e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257321431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3257321431
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1265566028
Short name T183
Test name
Test status
Simulation time 85209457433 ps
CPU time 331.43 seconds
Started Jul 16 07:19:28 PM PDT 24
Finished Jul 16 07:25:58 PM PDT 24
Peak memory 202228 kb
Host smart-74189796-f9a3-485a-913e-419c82a8961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265566028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1265566028
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2168007916
Short name T414
Test name
Test status
Simulation time 24617960998 ps
CPU time 55.73 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:21:25 PM PDT 24
Peak memory 201700 kb
Host smart-4a41a057-5168-4e3e-858e-99ba665e7212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168007916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2168007916
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3277137243
Short name T448
Test name
Test status
Simulation time 4168398077 ps
CPU time 9.87 seconds
Started Jul 16 07:19:34 PM PDT 24
Finished Jul 16 07:20:42 PM PDT 24
Peak memory 201728 kb
Host smart-48c8927e-535a-42e9-9a75-2d2c483a1c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277137243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3277137243
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1948545662
Short name T350
Test name
Test status
Simulation time 5580052541 ps
CPU time 3.39 seconds
Started Jul 16 07:19:17 PM PDT 24
Finished Jul 16 07:20:21 PM PDT 24
Peak memory 201716 kb
Host smart-c6bd1e0a-208b-4284-9237-89d9ea6c520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948545662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1948545662
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3290405742
Short name T202
Test name
Test status
Simulation time 163761530219 ps
CPU time 386 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:26:55 PM PDT 24
Peak memory 201844 kb
Host smart-3d5d875c-44bf-408d-9637-8f4394b5865d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290405742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3290405742
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3428262038
Short name T16
Test name
Test status
Simulation time 33000624163 ps
CPU time 40.22 seconds
Started Jul 16 07:19:29 PM PDT 24
Finished Jul 16 07:21:08 PM PDT 24
Peak memory 210224 kb
Host smart-5c2bb6b9-b503-477b-8a1b-9a99c59ef71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428262038 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3428262038
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.962493285
Short name T558
Test name
Test status
Simulation time 517817257 ps
CPU time 1.16 seconds
Started Jul 16 07:16:39 PM PDT 24
Finished Jul 16 07:17:10 PM PDT 24
Peak memory 201608 kb
Host smart-f38a2dab-86ac-4d9f-94e8-1f3a058ae353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962493285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.962493285
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2708371529
Short name T46
Test name
Test status
Simulation time 343468804702 ps
CPU time 838.59 seconds
Started Jul 16 07:16:24 PM PDT 24
Finished Jul 16 07:31:01 PM PDT 24
Peak memory 202088 kb
Host smart-60ae6b94-21df-42e9-a3ab-c19d417f12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708371529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2708371529
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3929943812
Short name T312
Test name
Test status
Simulation time 162773372571 ps
CPU time 101.13 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:18:50 PM PDT 24
Peak memory 201948 kb
Host smart-48ac7edb-d549-4752-a0dd-8014b616edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929943812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3929943812
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3492449530
Short name T483
Test name
Test status
Simulation time 492326377119 ps
CPU time 289.3 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:21:53 PM PDT 24
Peak memory 201872 kb
Host smart-e633910b-c45d-4987-bc4c-f532345709a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492449530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3492449530
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2914978165
Short name T145
Test name
Test status
Simulation time 162556092359 ps
CPU time 89.24 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:18:35 PM PDT 24
Peak memory 202012 kb
Host smart-050d58e0-fba9-4d61-b4df-58852a967340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914978165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2914978165
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.68164725
Short name T379
Test name
Test status
Simulation time 156411993705 ps
CPU time 364.43 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:23:10 PM PDT 24
Peak memory 201904 kb
Host smart-1e28e9ea-1c07-409a-a0a2-7240d78cc6cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=68164725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.68164725
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2939867293
Short name T198
Test name
Test status
Simulation time 168559861074 ps
CPU time 304.29 seconds
Started Jul 16 07:16:26 PM PDT 24
Finished Jul 16 07:22:09 PM PDT 24
Peak memory 201980 kb
Host smart-8ef42bb6-7200-4c15-9c89-d0d8d9d03709
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939867293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2939867293
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3569394915
Short name T601
Test name
Test status
Simulation time 401384527863 ps
CPU time 179.54 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:20:05 PM PDT 24
Peak memory 201888 kb
Host smart-3ecc6084-b106-43a0-8113-e517c2a1e235
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569394915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3569394915
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2271652436
Short name T612
Test name
Test status
Simulation time 62662760320 ps
CPU time 245.63 seconds
Started Jul 16 07:16:50 PM PDT 24
Finished Jul 16 07:21:18 PM PDT 24
Peak memory 202268 kb
Host smart-6ae2a7ac-7db3-488f-96fb-757d11099db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271652436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2271652436
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3490590186
Short name T186
Test name
Test status
Simulation time 29158306730 ps
CPU time 66.24 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:18:19 PM PDT 24
Peak memory 201020 kb
Host smart-a3efecd8-c0ef-4889-ab7b-6181856cc29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490590186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3490590186
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4055824861
Short name T613
Test name
Test status
Simulation time 4282385339 ps
CPU time 2.53 seconds
Started Jul 16 07:16:27 PM PDT 24
Finished Jul 16 07:17:08 PM PDT 24
Peak memory 201708 kb
Host smart-592b74ce-b85d-4b6f-bafc-2ce41e5a467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055824861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4055824861
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3728875365
Short name T81
Test name
Test status
Simulation time 8653160170 ps
CPU time 2.71 seconds
Started Jul 16 07:16:48 PM PDT 24
Finished Jul 16 07:17:14 PM PDT 24
Peak memory 217212 kb
Host smart-1b12fbac-8c0b-4102-8392-6f2d778b71d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728875365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3728875365
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.280527674
Short name T89
Test name
Test status
Simulation time 5757316609 ps
CPU time 4.34 seconds
Started Jul 16 07:16:25 PM PDT 24
Finished Jul 16 07:17:09 PM PDT 24
Peak memory 201656 kb
Host smart-e508b72d-ea3a-4959-ba4f-138a92303301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280527674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.280527674
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3140471902
Short name T721
Test name
Test status
Simulation time 214160098781 ps
CPU time 47.7 seconds
Started Jul 16 07:16:42 PM PDT 24
Finished Jul 16 07:17:58 PM PDT 24
Peak memory 201892 kb
Host smart-7e84122b-9d0f-413b-a5b3-273743166ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140471902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3140471902
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.666284924
Short name T32
Test name
Test status
Simulation time 174048662326 ps
CPU time 179.47 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:20:10 PM PDT 24
Peak memory 210612 kb
Host smart-c309be97-8cb5-461c-9362-42fce74073c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666284924 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.666284924
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.669924139
Short name T487
Test name
Test status
Simulation time 528095351 ps
CPU time 1.21 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:20:37 PM PDT 24
Peak memory 201656 kb
Host smart-c3d54d44-227e-4dc3-969b-2392cfdd5e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669924139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.669924139
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.147376030
Short name T172
Test name
Test status
Simulation time 588609441755 ps
CPU time 146.49 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:22:56 PM PDT 24
Peak memory 201888 kb
Host smart-424cc17a-b771-4f35-929f-7a9e0ddae426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147376030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.147376030
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1895905161
Short name T583
Test name
Test status
Simulation time 329068073834 ps
CPU time 201.26 seconds
Started Jul 16 07:19:32 PM PDT 24
Finished Jul 16 07:23:50 PM PDT 24
Peak memory 202000 kb
Host smart-560bf5d9-af96-4f58-8f46-a22e9886b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895905161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1895905161
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.839417986
Short name T682
Test name
Test status
Simulation time 160442283328 ps
CPU time 68.16 seconds
Started Jul 16 07:19:29 PM PDT 24
Finished Jul 16 07:21:37 PM PDT 24
Peak memory 201888 kb
Host smart-7ede626e-5392-498f-90ad-471586f499f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=839417986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.839417986
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2069152986
Short name T769
Test name
Test status
Simulation time 324982208144 ps
CPU time 341.88 seconds
Started Jul 16 07:19:31 PM PDT 24
Finished Jul 16 07:26:11 PM PDT 24
Peak memory 201940 kb
Host smart-3b7452db-ca9f-4328-beb4-6bf77a6856bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069152986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2069152986
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3483059573
Short name T425
Test name
Test status
Simulation time 328470947920 ps
CPU time 170.77 seconds
Started Jul 16 07:19:29 PM PDT 24
Finished Jul 16 07:23:20 PM PDT 24
Peak memory 201888 kb
Host smart-9851cedd-c1d5-4b9b-a9c7-2ddf6a1d757e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483059573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3483059573
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2159600963
Short name T549
Test name
Test status
Simulation time 595918444237 ps
CPU time 1330.97 seconds
Started Jul 16 07:19:29 PM PDT 24
Finished Jul 16 07:42:40 PM PDT 24
Peak memory 201944 kb
Host smart-51b96932-e8ff-4233-8171-279e8b07c8dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159600963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2159600963
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2614215068
Short name T727
Test name
Test status
Simulation time 617165979887 ps
CPU time 701.26 seconds
Started Jul 16 07:19:30 PM PDT 24
Finished Jul 16 07:32:10 PM PDT 24
Peak memory 201828 kb
Host smart-85efc92a-b9d8-47db-bfff-86cc67451452
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614215068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2614215068
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.67222524
Short name T541
Test name
Test status
Simulation time 90503410309 ps
CPU time 364.73 seconds
Started Jul 16 07:19:41 PM PDT 24
Finished Jul 16 07:26:39 PM PDT 24
Peak memory 202116 kb
Host smart-39331548-3446-4b47-8d6c-d86a4b7eb01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67222524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.67222524
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2174839071
Short name T387
Test name
Test status
Simulation time 26598594861 ps
CPU time 14.9 seconds
Started Jul 16 07:19:31 PM PDT 24
Finished Jul 16 07:20:45 PM PDT 24
Peak memory 201704 kb
Host smart-705187a5-9634-414d-a7b7-f2f596a402a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174839071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2174839071
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2963361380
Short name T620
Test name
Test status
Simulation time 3534748696 ps
CPU time 2.18 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:21:14 PM PDT 24
Peak memory 201744 kb
Host smart-6aebb57e-706b-4e2d-a21e-3b1544187069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963361380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2963361380
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3617964631
Short name T432
Test name
Test status
Simulation time 6095295583 ps
CPU time 4.48 seconds
Started Jul 16 07:19:34 PM PDT 24
Finished Jul 16 07:20:34 PM PDT 24
Peak memory 201736 kb
Host smart-1e29c4c1-c529-4125-bc4f-2c5b80bd51df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617964631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3617964631
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4063069273
Short name T97
Test name
Test status
Simulation time 237748106535 ps
CPU time 153.6 seconds
Started Jul 16 07:19:43 PM PDT 24
Finished Jul 16 07:23:12 PM PDT 24
Peak memory 201896 kb
Host smart-1d73dcc2-d909-4835-a6ea-cd651f9e0229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063069273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4063069273
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3737447468
Short name T287
Test name
Test status
Simulation time 44726320538 ps
CPU time 41.21 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:21:17 PM PDT 24
Peak memory 210220 kb
Host smart-942baa87-b8c3-4e54-96b9-727e6652800f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737447468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3737447468
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2168093547
Short name T362
Test name
Test status
Simulation time 471414090 ps
CPU time 0.68 seconds
Started Jul 16 07:19:53 PM PDT 24
Finished Jul 16 07:20:46 PM PDT 24
Peak memory 201848 kb
Host smart-e9e2d9ca-3041-482a-915b-0946f1612bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168093547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2168093547
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.728084138
Short name T303
Test name
Test status
Simulation time 198957176582 ps
CPU time 112.07 seconds
Started Jul 16 07:19:39 PM PDT 24
Finished Jul 16 07:22:28 PM PDT 24
Peak memory 201908 kb
Host smart-4c6fde45-a3ff-4f37-a844-e53a9c1b3f7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728084138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.728084138
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1973849810
Short name T230
Test name
Test status
Simulation time 371974773158 ps
CPU time 417.85 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:27:34 PM PDT 24
Peak memory 201828 kb
Host smart-e9f2fc59-7408-492b-9368-721e5885b998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973849810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1973849810
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.937997173
Short name T254
Test name
Test status
Simulation time 164572602319 ps
CPU time 404.09 seconds
Started Jul 16 07:19:39 PM PDT 24
Finished Jul 16 07:27:17 PM PDT 24
Peak memory 201984 kb
Host smart-cca527e0-8775-4bdd-98cd-de0ba2ab246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937997173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.937997173
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3075358907
Short name T571
Test name
Test status
Simulation time 490029242820 ps
CPU time 958.79 seconds
Started Jul 16 07:19:42 PM PDT 24
Finished Jul 16 07:36:36 PM PDT 24
Peak memory 201860 kb
Host smart-663cb23c-71bc-4062-9a8f-b64d80d508c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075358907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3075358907
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4015440386
Short name T553
Test name
Test status
Simulation time 495892198676 ps
CPU time 581.26 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:30:17 PM PDT 24
Peak memory 201964 kb
Host smart-52d2c015-6d70-4923-b3f2-771dd5f35e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015440386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4015440386
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1972884962
Short name T761
Test name
Test status
Simulation time 322727057392 ps
CPU time 366.98 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:26:43 PM PDT 24
Peak memory 201924 kb
Host smart-220d8b2a-8bd2-4feb-b8d1-a5360a81794e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972884962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1972884962
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.118565518
Short name T263
Test name
Test status
Simulation time 360051922631 ps
CPU time 674.82 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:31:51 PM PDT 24
Peak memory 201924 kb
Host smart-38a75f79-84db-4444-87a7-3259fa4d87c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118565518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.118565518
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1534597952
Short name T378
Test name
Test status
Simulation time 596518452312 ps
CPU time 341.36 seconds
Started Jul 16 07:19:41 PM PDT 24
Finished Jul 16 07:26:18 PM PDT 24
Peak memory 201912 kb
Host smart-2561a95f-831a-4ba5-9071-9e3f966ebe67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534597952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1534597952
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3924953039
Short name T45
Test name
Test status
Simulation time 80983922046 ps
CPU time 349.35 seconds
Started Jul 16 07:19:39 PM PDT 24
Finished Jul 16 07:26:25 PM PDT 24
Peak memory 202180 kb
Host smart-3b2482f7-27dd-4686-bddc-8992fee22c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924953039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3924953039
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2495290230
Short name T473
Test name
Test status
Simulation time 33656206958 ps
CPU time 19.63 seconds
Started Jul 16 07:19:42 PM PDT 24
Finished Jul 16 07:20:56 PM PDT 24
Peak memory 201752 kb
Host smart-993d3e20-52b8-4ab9-b8c1-9ad6efded715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495290230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2495290230
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1434607881
Short name T679
Test name
Test status
Simulation time 3560052447 ps
CPU time 1.75 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:20:38 PM PDT 24
Peak memory 201708 kb
Host smart-fa3e9a53-0390-4aff-b29c-fc1c70bc8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434607881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1434607881
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1613518181
Short name T357
Test name
Test status
Simulation time 5976951099 ps
CPU time 3.93 seconds
Started Jul 16 07:19:40 PM PDT 24
Finished Jul 16 07:20:40 PM PDT 24
Peak memory 201692 kb
Host smart-f724703b-1cb8-4d0a-be85-5b38505b8367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613518181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1613518181
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3433035484
Short name T566
Test name
Test status
Simulation time 384689439670 ps
CPU time 955.37 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:36:40 PM PDT 24
Peak memory 201916 kb
Host smart-30deafe9-baa0-4ac4-90a1-e3d838d8cc20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433035484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3433035484
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3436349508
Short name T412
Test name
Test status
Simulation time 400079564 ps
CPU time 0.88 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:20:46 PM PDT 24
Peak memory 201572 kb
Host smart-77e4714d-742b-4503-910c-0a4353bf7a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436349508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3436349508
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.215424444
Short name T634
Test name
Test status
Simulation time 502520681027 ps
CPU time 970.71 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:36:56 PM PDT 24
Peak memory 201832 kb
Host smart-53fbdb44-020e-4547-b3c3-c04f22f15670
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215424444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.215424444
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1524112639
Short name T101
Test name
Test status
Simulation time 530252095939 ps
CPU time 612.12 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:30:58 PM PDT 24
Peak memory 201908 kb
Host smart-ae692fbe-2806-42f9-bd43-10c471da2c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524112639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1524112639
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4213581856
Short name T140
Test name
Test status
Simulation time 333156860454 ps
CPU time 195.69 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:24:01 PM PDT 24
Peak memory 201968 kb
Host smart-bc912142-8c63-49a6-a6fb-a092d87218cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213581856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4213581856
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3280495855
Short name T741
Test name
Test status
Simulation time 164920853111 ps
CPU time 370.36 seconds
Started Jul 16 07:19:57 PM PDT 24
Finished Jul 16 07:26:57 PM PDT 24
Peak memory 201820 kb
Host smart-f29ecfd7-fcc4-4957-b04a-862dc3f1a536
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280495855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3280495855
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1521914318
Short name T235
Test name
Test status
Simulation time 494817260381 ps
CPU time 543.79 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:29:48 PM PDT 24
Peak memory 201956 kb
Host smart-09024dac-a153-47eb-b737-d69f0b088922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521914318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1521914318
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.272190550
Short name T489
Test name
Test status
Simulation time 170779108023 ps
CPU time 141.84 seconds
Started Jul 16 07:19:58 PM PDT 24
Finished Jul 16 07:23:06 PM PDT 24
Peak memory 201888 kb
Host smart-9ebee13f-a820-465f-8381-a8fb2d5221e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=272190550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.272190550
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1876017651
Short name T584
Test name
Test status
Simulation time 169722808988 ps
CPU time 390.11 seconds
Started Jul 16 07:19:56 PM PDT 24
Finished Jul 16 07:27:17 PM PDT 24
Peak memory 201848 kb
Host smart-85aaffae-db7f-4f80-871a-9a2854d7389b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876017651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1876017651
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3540011827
Short name T604
Test name
Test status
Simulation time 394769976228 ps
CPU time 47.36 seconds
Started Jul 16 07:19:55 PM PDT 24
Finished Jul 16 07:21:33 PM PDT 24
Peak memory 201908 kb
Host smart-e8d63b1c-0c1b-440d-988a-39c15ad82469
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540011827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3540011827
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2988046788
Short name T221
Test name
Test status
Simulation time 72476624085 ps
CPU time 366.62 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:26:52 PM PDT 24
Peak memory 202244 kb
Host smart-f11e0265-d53e-4ec0-a9bf-6aa13fcf6d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988046788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2988046788
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1480940771
Short name T528
Test name
Test status
Simulation time 45083223767 ps
CPU time 51.2 seconds
Started Jul 16 07:19:54 PM PDT 24
Finished Jul 16 07:21:36 PM PDT 24
Peak memory 201728 kb
Host smart-c427587c-ce07-40ed-a780-d5a51b447fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480940771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1480940771
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2871528558
Short name T486
Test name
Test status
Simulation time 4861045023 ps
CPU time 5.92 seconds
Started Jul 16 07:19:56 PM PDT 24
Finished Jul 16 07:20:52 PM PDT 24
Peak memory 201724 kb
Host smart-6f78deab-533c-4687-9ba2-3f1669aa2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871528558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2871528558
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2429225121
Short name T359
Test name
Test status
Simulation time 6052251144 ps
CPU time 4.24 seconds
Started Jul 16 07:19:55 PM PDT 24
Finished Jul 16 07:20:50 PM PDT 24
Peak memory 201652 kb
Host smart-5a1d6fff-3531-463c-895a-276bf16e1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429225121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2429225121
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1397617215
Short name T244
Test name
Test status
Simulation time 208606798718 ps
CPU time 220.71 seconds
Started Jul 16 07:19:58 PM PDT 24
Finished Jul 16 07:24:27 PM PDT 24
Peak memory 201976 kb
Host smart-4f026943-ccbc-403c-9bd9-40122b5b20d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397617215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1397617215
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1411087292
Short name T366
Test name
Test status
Simulation time 495661460 ps
CPU time 1.06 seconds
Started Jul 16 07:20:21 PM PDT 24
Finished Jul 16 07:21:00 PM PDT 24
Peak memory 201664 kb
Host smart-a4e7a2a0-06a3-4042-bb1a-6178101897cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411087292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1411087292
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3104702842
Short name T659
Test name
Test status
Simulation time 175984605951 ps
CPU time 196.3 seconds
Started Jul 16 07:20:06 PM PDT 24
Finished Jul 16 07:24:05 PM PDT 24
Peak memory 201932 kb
Host smart-6dba58c7-8b76-4b70-a152-2d91cda3bf42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104702842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3104702842
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3025989524
Short name T260
Test name
Test status
Simulation time 494088889565 ps
CPU time 551.17 seconds
Started Jul 16 07:20:08 PM PDT 24
Finished Jul 16 07:30:02 PM PDT 24
Peak memory 201920 kb
Host smart-af03c30b-32a5-4cbe-b63e-f34f1efefe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025989524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3025989524
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3566510630
Short name T588
Test name
Test status
Simulation time 164599855990 ps
CPU time 93.67 seconds
Started Jul 16 07:20:08 PM PDT 24
Finished Jul 16 07:22:26 PM PDT 24
Peak memory 201876 kb
Host smart-5d5b5fca-c4c3-48ef-ac1c-6f631680a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566510630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3566510630
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2279764513
Short name T352
Test name
Test status
Simulation time 328109278710 ps
CPU time 696.38 seconds
Started Jul 16 07:20:06 PM PDT 24
Finished Jul 16 07:32:27 PM PDT 24
Peak memory 201916 kb
Host smart-2af5d6c2-cb33-485a-b89b-fb668e8dc85a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279764513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2279764513
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3004990807
Short name T463
Test name
Test status
Simulation time 487863461612 ps
CPU time 267.63 seconds
Started Jul 16 07:20:07 PM PDT 24
Finished Jul 16 07:25:18 PM PDT 24
Peak memory 201968 kb
Host smart-a6342375-49c8-4ff3-afe4-94b0a545a14d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004990807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3004990807
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1594991074
Short name T28
Test name
Test status
Simulation time 194130853205 ps
CPU time 229.56 seconds
Started Jul 16 07:20:08 PM PDT 24
Finished Jul 16 07:24:41 PM PDT 24
Peak memory 201900 kb
Host smart-19aaf429-afa3-47c3-aa6f-4df6249a32bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594991074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1594991074
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.400009943
Short name T542
Test name
Test status
Simulation time 134906127280 ps
CPU time 427.92 seconds
Started Jul 16 07:20:07 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 202228 kb
Host smart-7591a3c7-1956-4f72-869a-373038048da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400009943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.400009943
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1056802874
Short name T429
Test name
Test status
Simulation time 27882484122 ps
CPU time 68.3 seconds
Started Jul 16 07:20:06 PM PDT 24
Finished Jul 16 07:21:59 PM PDT 24
Peak memory 201692 kb
Host smart-a84453e1-4477-46ad-b8f6-3c1673aff1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056802874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1056802874
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3928091495
Short name T717
Test name
Test status
Simulation time 4172364115 ps
CPU time 10.17 seconds
Started Jul 16 07:20:05 PM PDT 24
Finished Jul 16 07:20:59 PM PDT 24
Peak memory 201620 kb
Host smart-9db99118-7ff5-4c5f-8cdc-7a90fd921cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928091495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3928091495
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2855760004
Short name T632
Test name
Test status
Simulation time 5924858708 ps
CPU time 3.39 seconds
Started Jul 16 07:20:07 PM PDT 24
Finished Jul 16 07:20:54 PM PDT 24
Peak memory 201664 kb
Host smart-b6b7c666-faf4-416a-9540-ddab7dc018b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855760004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2855760004
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2012847027
Short name T670
Test name
Test status
Simulation time 239303487848 ps
CPU time 131.07 seconds
Started Jul 16 07:20:18 PM PDT 24
Finished Jul 16 07:23:07 PM PDT 24
Peak memory 201860 kb
Host smart-efc6810f-c167-4032-86c2-f48ee3b3019e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012847027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2012847027
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1871640177
Short name T735
Test name
Test status
Simulation time 256114758708 ps
CPU time 260.61 seconds
Started Jul 16 07:20:21 PM PDT 24
Finished Jul 16 07:25:18 PM PDT 24
Peak memory 210132 kb
Host smart-aee3cc3b-fd2d-4878-8607-7f5afd924ac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871640177 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1871640177
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3431143405
Short name T14
Test name
Test status
Simulation time 398210549 ps
CPU time 0.78 seconds
Started Jul 16 07:20:44 PM PDT 24
Finished Jul 16 07:21:09 PM PDT 24
Peak memory 201644 kb
Host smart-9d8b65b3-a3b6-4d8e-92a7-e0343e25e144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431143405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3431143405
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.152342888
Short name T204
Test name
Test status
Simulation time 350031206682 ps
CPU time 171.97 seconds
Started Jul 16 07:20:29 PM PDT 24
Finished Jul 16 07:23:54 PM PDT 24
Peak memory 201984 kb
Host smart-b58481d7-d1e4-4f6b-b281-af1ef7227f30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152342888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.152342888
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1540615438
Short name T197
Test name
Test status
Simulation time 164071320425 ps
CPU time 58.84 seconds
Started Jul 16 07:20:31 PM PDT 24
Finished Jul 16 07:22:01 PM PDT 24
Peak memory 201872 kb
Host smart-47a059f3-8a41-4891-8ba2-6fce97064e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540615438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1540615438
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.745348464
Short name T345
Test name
Test status
Simulation time 166573858806 ps
CPU time 189.94 seconds
Started Jul 16 07:20:18 PM PDT 24
Finished Jul 16 07:24:06 PM PDT 24
Peak memory 201908 kb
Host smart-95f4731e-dd46-4e0c-b2e2-f50f58809030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745348464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.745348464
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.126605248
Short name T680
Test name
Test status
Simulation time 323090085368 ps
CPU time 722.4 seconds
Started Jul 16 07:20:18 PM PDT 24
Finished Jul 16 07:32:58 PM PDT 24
Peak memory 201900 kb
Host smart-07c444bb-2356-4b58-983f-9e152f602fc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=126605248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.126605248
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3571879784
Short name T43
Test name
Test status
Simulation time 162266682825 ps
CPU time 332.12 seconds
Started Jul 16 07:20:17 PM PDT 24
Finished Jul 16 07:26:29 PM PDT 24
Peak memory 201884 kb
Host smart-ee5f7d41-f6ef-432f-a69a-dad417b60e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571879784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3571879784
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1718835696
Short name T367
Test name
Test status
Simulation time 324968861116 ps
CPU time 737.95 seconds
Started Jul 16 07:20:17 PM PDT 24
Finished Jul 16 07:33:15 PM PDT 24
Peak memory 201800 kb
Host smart-b858b249-b0d4-401b-a42b-7c772dbba78e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718835696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1718835696
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1506528999
Short name T239
Test name
Test status
Simulation time 355920647062 ps
CPU time 43.97 seconds
Started Jul 16 07:20:19 PM PDT 24
Finished Jul 16 07:21:42 PM PDT 24
Peak memory 201844 kb
Host smart-f204b9fc-ee48-42fc-be29-78eeec5f9240
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506528999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1506528999
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2852454129
Short name T481
Test name
Test status
Simulation time 616452076378 ps
CPU time 1460.03 seconds
Started Jul 16 07:20:21 PM PDT 24
Finished Jul 16 07:45:19 PM PDT 24
Peak memory 201592 kb
Host smart-3e044144-c95f-4640-b46d-e16e721edbd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852454129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2852454129
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1651688091
Short name T209
Test name
Test status
Simulation time 84997030460 ps
CPU time 299.9 seconds
Started Jul 16 07:20:43 PM PDT 24
Finished Jul 16 07:26:08 PM PDT 24
Peak memory 202216 kb
Host smart-efb5b00b-4bfd-441a-8a34-29803386ff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651688091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1651688091
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.227243011
Short name T398
Test name
Test status
Simulation time 40704193083 ps
CPU time 82.64 seconds
Started Jul 16 07:20:33 PM PDT 24
Finished Jul 16 07:22:26 PM PDT 24
Peak memory 201676 kb
Host smart-a9f2bd57-67b6-4deb-a70d-f6b7e0ded11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227243011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.227243011
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3528412350
Short name T656
Test name
Test status
Simulation time 4302770411 ps
CPU time 10.69 seconds
Started Jul 16 07:20:31 PM PDT 24
Finished Jul 16 07:21:13 PM PDT 24
Peak memory 201660 kb
Host smart-59ae75c0-c4d4-49a4-a2b1-6a825fbb13f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528412350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3528412350
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3227146279
Short name T594
Test name
Test status
Simulation time 5589150633 ps
CPU time 11.81 seconds
Started Jul 16 07:20:17 PM PDT 24
Finished Jul 16 07:21:09 PM PDT 24
Peak memory 201624 kb
Host smart-3bc58750-6223-48e9-ae57-5c4dc640e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227146279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3227146279
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.259790472
Short name T311
Test name
Test status
Simulation time 333391560591 ps
CPU time 141.51 seconds
Started Jul 16 07:20:42 PM PDT 24
Finished Jul 16 07:23:29 PM PDT 24
Peak memory 201928 kb
Host smart-0fbae47d-82b0-45a7-bc01-4aa361cfad75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259790472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
259790472
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.323057519
Short name T17
Test name
Test status
Simulation time 255586121090 ps
CPU time 105.39 seconds
Started Jul 16 07:20:44 PM PDT 24
Finished Jul 16 07:22:54 PM PDT 24
Peak memory 210280 kb
Host smart-e10636ca-45e8-4d6d-89ca-e578f6fdbe98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323057519 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.323057519
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3899959567
Short name T757
Test name
Test status
Simulation time 435372315 ps
CPU time 1.11 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:21:13 PM PDT 24
Peak memory 201620 kb
Host smart-d862efc7-15a6-4fdc-8f0e-bf4f1cc29745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899959567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3899959567
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.818597606
Short name T716
Test name
Test status
Simulation time 164332869443 ps
CPU time 91.99 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:22:44 PM PDT 24
Peak memory 201892 kb
Host smart-24a23e7f-a7f2-4960-9287-98c4e121053f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818597606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.818597606
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.883247864
Short name T98
Test name
Test status
Simulation time 359119681526 ps
CPU time 787.6 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:34:20 PM PDT 24
Peak memory 201940 kb
Host smart-e1650e2a-47ad-4ff9-aa93-fb5c65834fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883247864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.883247864
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1204953956
Short name T27
Test name
Test status
Simulation time 164886074647 ps
CPU time 358.06 seconds
Started Jul 16 07:20:43 PM PDT 24
Finished Jul 16 07:27:06 PM PDT 24
Peak memory 201904 kb
Host smart-85a994c1-0210-4c25-a0e0-c2f1b68ed6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204953956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1204953956
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1622463217
Short name T84
Test name
Test status
Simulation time 160578310600 ps
CPU time 340.65 seconds
Started Jul 16 07:20:44 PM PDT 24
Finished Jul 16 07:26:49 PM PDT 24
Peak memory 201904 kb
Host smart-cdbc0488-1dba-4c5b-8728-273c4a85783b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622463217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1622463217
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.372328739
Short name T517
Test name
Test status
Simulation time 482236354275 ps
CPU time 141.73 seconds
Started Jul 16 07:20:44 PM PDT 24
Finished Jul 16 07:23:30 PM PDT 24
Peak memory 201888 kb
Host smart-e29e586d-8037-4e3a-a6d5-876a6e4acfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372328739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.372328739
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1840289258
Short name T587
Test name
Test status
Simulation time 165187586606 ps
CPU time 182.64 seconds
Started Jul 16 07:20:42 PM PDT 24
Finished Jul 16 07:24:10 PM PDT 24
Peak memory 201832 kb
Host smart-85886c5e-0e47-4833-a377-a974ac43f9fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840289258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1840289258
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.45797784
Short name T296
Test name
Test status
Simulation time 341291777028 ps
CPU time 710.8 seconds
Started Jul 16 07:20:43 PM PDT 24
Finished Jul 16 07:32:59 PM PDT 24
Peak memory 201920 kb
Host smart-69241f69-17aa-480e-a2c3-28a13f6e8331
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45797784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_w
akeup.45797784
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1595844812
Short name T698
Test name
Test status
Simulation time 402117887582 ps
CPU time 196.37 seconds
Started Jul 16 07:20:42 PM PDT 24
Finished Jul 16 07:24:24 PM PDT 24
Peak memory 201872 kb
Host smart-f554f667-cf91-45bf-ade3-c296a94435f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595844812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1595844812
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1431568883
Short name T687
Test name
Test status
Simulation time 69408875090 ps
CPU time 290.69 seconds
Started Jul 16 07:20:50 PM PDT 24
Finished Jul 16 07:26:01 PM PDT 24
Peak memory 202168 kb
Host smart-dab324e9-bd0c-4d7b-a50c-e303b62894a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431568883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1431568883
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2647367886
Short name T200
Test name
Test status
Simulation time 46734233576 ps
CPU time 44.87 seconds
Started Jul 16 07:20:50 PM PDT 24
Finished Jul 16 07:21:56 PM PDT 24
Peak memory 201716 kb
Host smart-05050e9e-2ffc-41de-b0a3-d8e89ee408b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647367886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2647367886
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1701523754
Short name T657
Test name
Test status
Simulation time 3125245186 ps
CPU time 6.67 seconds
Started Jul 16 07:20:50 PM PDT 24
Finished Jul 16 07:21:18 PM PDT 24
Peak memory 201656 kb
Host smart-ccbbcb55-cac7-4916-b3f5-58548b677cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701523754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1701523754
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2291626529
Short name T708
Test name
Test status
Simulation time 5683315769 ps
CPU time 4.24 seconds
Started Jul 16 07:20:43 PM PDT 24
Finished Jul 16 07:21:12 PM PDT 24
Peak memory 201688 kb
Host smart-cde8a127-1f62-4365-9c4d-33e0e9af3ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291626529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2291626529
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2005288274
Short name T193
Test name
Test status
Simulation time 334820225332 ps
CPU time 193.51 seconds
Started Jul 16 07:20:54 PM PDT 24
Finished Jul 16 07:24:25 PM PDT 24
Peak memory 201904 kb
Host smart-03f35007-8d3e-45f6-9d0a-26e8789e2530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005288274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2005288274
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3917216809
Short name T93
Test name
Test status
Simulation time 369802044172 ps
CPU time 200.97 seconds
Started Jul 16 07:20:51 PM PDT 24
Finished Jul 16 07:24:32 PM PDT 24
Peak memory 210276 kb
Host smart-872c54fc-a525-4d04-a6b8-f822d3367c66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917216809 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3917216809
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2631799998
Short name T742
Test name
Test status
Simulation time 343732941 ps
CPU time 0.73 seconds
Started Jul 16 07:21:04 PM PDT 24
Finished Jul 16 07:21:18 PM PDT 24
Peak memory 201660 kb
Host smart-dfaffe86-b10d-44dc-83e5-f04f012ddbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631799998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2631799998
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.4065863032
Short name T752
Test name
Test status
Simulation time 324161611081 ps
CPU time 745.35 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:33:37 PM PDT 24
Peak memory 201836 kb
Host smart-af91ebc1-1d2b-4aba-b06e-9131c49e89cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065863032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.4065863032
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3534590527
Short name T306
Test name
Test status
Simulation time 359068943892 ps
CPU time 420.93 seconds
Started Jul 16 07:20:51 PM PDT 24
Finished Jul 16 07:28:12 PM PDT 24
Peak memory 201968 kb
Host smart-03c366ed-6155-4306-86ae-ce8453b4ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534590527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3534590527
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1532650640
Short name T107
Test name
Test status
Simulation time 487281017007 ps
CPU time 340.47 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:26:52 PM PDT 24
Peak memory 201916 kb
Host smart-bdf25b1c-373e-44b8-9427-c1bd081e7373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532650640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1532650640
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3478221941
Short name T548
Test name
Test status
Simulation time 171183903214 ps
CPU time 200.45 seconds
Started Jul 16 07:20:50 PM PDT 24
Finished Jul 16 07:24:31 PM PDT 24
Peak memory 201788 kb
Host smart-38e47691-60ba-4143-9a28-64ad37f795ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478221941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3478221941
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4011733766
Short name T684
Test name
Test status
Simulation time 166092304879 ps
CPU time 369.03 seconds
Started Jul 16 07:20:52 PM PDT 24
Finished Jul 16 07:27:21 PM PDT 24
Peak memory 201968 kb
Host smart-70b54481-d2e2-48fa-b0b4-74559cb4deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011733766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4011733766
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1837157953
Short name T666
Test name
Test status
Simulation time 326797963988 ps
CPU time 156.31 seconds
Started Jul 16 07:20:51 PM PDT 24
Finished Jul 16 07:23:48 PM PDT 24
Peak memory 201920 kb
Host smart-13545515-bebb-46f7-95f2-1907c8a48a57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837157953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1837157953
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2724218521
Short name T759
Test name
Test status
Simulation time 201608682779 ps
CPU time 454.36 seconds
Started Jul 16 07:20:50 PM PDT 24
Finished Jul 16 07:28:45 PM PDT 24
Peak memory 201868 kb
Host smart-9e9b4e46-b2c4-4fc2-a8d4-d22a92754954
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724218521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2724218521
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3257143054
Short name T524
Test name
Test status
Simulation time 108379314900 ps
CPU time 538.31 seconds
Started Jul 16 07:21:05 PM PDT 24
Finished Jul 16 07:30:16 PM PDT 24
Peak memory 202188 kb
Host smart-6c6e49de-d6e5-4d35-8244-7a54d8337a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257143054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3257143054
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3156164365
Short name T603
Test name
Test status
Simulation time 44638197815 ps
CPU time 96.72 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:22:49 PM PDT 24
Peak memory 201676 kb
Host smart-999c4ede-ac78-45d5-9f75-cd071b1cad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156164365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3156164365
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2024293206
Short name T349
Test name
Test status
Simulation time 4759528077 ps
CPU time 2.83 seconds
Started Jul 16 07:20:53 PM PDT 24
Finished Jul 16 07:21:15 PM PDT 24
Peak memory 201712 kb
Host smart-eefe3d5f-fe46-4e66-b05b-eea6e940be54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024293206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2024293206
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4126331102
Short name T466
Test name
Test status
Simulation time 5980840370 ps
CPU time 3.05 seconds
Started Jul 16 07:20:51 PM PDT 24
Finished Jul 16 07:21:15 PM PDT 24
Peak memory 201732 kb
Host smart-2fb6c882-c5ac-42f1-96a1-0066f6adfef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126331102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4126331102
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1337943898
Short name T210
Test name
Test status
Simulation time 167801983221 ps
CPU time 422.18 seconds
Started Jul 16 07:21:04 PM PDT 24
Finished Jul 16 07:28:19 PM PDT 24
Peak memory 202156 kb
Host smart-2d28d7ea-7ba3-4808-abae-df9cc9b66772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337943898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1337943898
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.742395664
Short name T368
Test name
Test status
Simulation time 379225547 ps
CPU time 1.4 seconds
Started Jul 16 07:21:14 PM PDT 24
Finished Jul 16 07:21:25 PM PDT 24
Peak memory 201664 kb
Host smart-aa0ed4fb-96da-48c4-be73-50849e32a58c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742395664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.742395664
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.742866487
Short name T181
Test name
Test status
Simulation time 585597156478 ps
CPU time 62.96 seconds
Started Jul 16 07:21:04 PM PDT 24
Finished Jul 16 07:22:20 PM PDT 24
Peak memory 201972 kb
Host smart-bfda50ba-8c19-4149-ac5c-bd3a6551528e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742866487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.742866487
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2777862476
Short name T266
Test name
Test status
Simulation time 325979031774 ps
CPU time 762.77 seconds
Started Jul 16 07:21:03 PM PDT 24
Finished Jul 16 07:33:59 PM PDT 24
Peak memory 201888 kb
Host smart-a3fe2d14-1665-45de-95f7-f78823b32eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777862476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2777862476
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1502969309
Short name T407
Test name
Test status
Simulation time 497842191624 ps
CPU time 1163.62 seconds
Started Jul 16 07:21:04 PM PDT 24
Finished Jul 16 07:40:41 PM PDT 24
Peak memory 201912 kb
Host smart-f8a50ffb-d671-44b1-8c16-31cfd54cee9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502969309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1502969309
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.390150661
Short name T633
Test name
Test status
Simulation time 325843105849 ps
CPU time 62.71 seconds
Started Jul 16 07:21:05 PM PDT 24
Finished Jul 16 07:22:21 PM PDT 24
Peak memory 201904 kb
Host smart-38290d40-8b3b-4c1f-ba93-95a1c66a35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390150661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.390150661
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.744433011
Short name T723
Test name
Test status
Simulation time 491966784117 ps
CPU time 1056.87 seconds
Started Jul 16 07:21:06 PM PDT 24
Finished Jul 16 07:38:56 PM PDT 24
Peak memory 201896 kb
Host smart-4841efdd-d122-4728-b62a-94364228c0c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=744433011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.744433011
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1333777025
Short name T577
Test name
Test status
Simulation time 181682229845 ps
CPU time 107.09 seconds
Started Jul 16 07:21:05 PM PDT 24
Finished Jul 16 07:23:05 PM PDT 24
Peak memory 201952 kb
Host smart-dc7b7c5f-e076-44c0-94d7-3a6dbb6c0ec0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333777025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1333777025
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.913865658
Short name T437
Test name
Test status
Simulation time 390927054761 ps
CPU time 851.73 seconds
Started Jul 16 07:21:06 PM PDT 24
Finished Jul 16 07:35:30 PM PDT 24
Peak memory 201896 kb
Host smart-279d74ba-a227-487f-9179-cc29aecf7c2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913865658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.913865658
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.707356530
Short name T5
Test name
Test status
Simulation time 78682699056 ps
CPU time 225.77 seconds
Started Jul 16 07:21:06 PM PDT 24
Finished Jul 16 07:25:05 PM PDT 24
Peak memory 202260 kb
Host smart-d889bf0e-e551-4d11-a151-24a624e91c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707356530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.707356530
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.306183434
Short name T30
Test name
Test status
Simulation time 43821320716 ps
CPU time 96.44 seconds
Started Jul 16 07:21:04 PM PDT 24
Finished Jul 16 07:22:53 PM PDT 24
Peak memory 201724 kb
Host smart-ecb489c8-347b-4101-862b-00b3a0a5a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306183434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.306183434
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3081271576
Short name T369
Test name
Test status
Simulation time 5199496924 ps
CPU time 6.07 seconds
Started Jul 16 07:21:06 PM PDT 24
Finished Jul 16 07:21:24 PM PDT 24
Peak memory 201776 kb
Host smart-00a47de3-e9da-4cc6-a3ff-4882b6d08db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081271576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3081271576
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1349145483
Short name T567
Test name
Test status
Simulation time 5993661023 ps
CPU time 7.19 seconds
Started Jul 16 07:21:04 PM PDT 24
Finished Jul 16 07:21:23 PM PDT 24
Peak memory 201712 kb
Host smart-ac232968-f889-47c5-826c-acd4f1b5b63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349145483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1349145483
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1385895608
Short name T257
Test name
Test status
Simulation time 649829081281 ps
CPU time 1529.01 seconds
Started Jul 16 07:21:17 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 201928 kb
Host smart-32927fad-c46e-47da-830e-8fefe5d763a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385895608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1385895608
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3610219738
Short name T796
Test name
Test status
Simulation time 341791971998 ps
CPU time 517.92 seconds
Started Jul 16 07:21:14 PM PDT 24
Finished Jul 16 07:30:01 PM PDT 24
Peak memory 211492 kb
Host smart-2b6e8bd7-fd98-4842-9eb7-a8fdf58572a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610219738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3610219738
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2993473515
Short name T731
Test name
Test status
Simulation time 522007517 ps
CPU time 0.91 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:21:34 PM PDT 24
Peak memory 201848 kb
Host smart-cad4bac0-cf56-4527-a767-fe15891be622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993473515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2993473515
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1875151289
Short name T511
Test name
Test status
Simulation time 534879458582 ps
CPU time 240.39 seconds
Started Jul 16 07:21:16 PM PDT 24
Finished Jul 16 07:25:25 PM PDT 24
Peak memory 201920 kb
Host smart-8e2c8793-047c-4381-be17-507f42461975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875151289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1875151289
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3139672873
Short name T236
Test name
Test status
Simulation time 320416129361 ps
CPU time 708.18 seconds
Started Jul 16 07:21:16 PM PDT 24
Finished Jul 16 07:33:12 PM PDT 24
Peak memory 201924 kb
Host smart-fcb4c2c9-1b9f-4c89-9e0d-402070cf2153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139672873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3139672873
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3149150857
Short name T440
Test name
Test status
Simulation time 165295514680 ps
CPU time 92.04 seconds
Started Jul 16 07:21:14 PM PDT 24
Finished Jul 16 07:22:55 PM PDT 24
Peak memory 201872 kb
Host smart-034f79a5-4272-49fb-adf2-8847e7e32d36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149150857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3149150857
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4265378129
Short name T381
Test name
Test status
Simulation time 161814015139 ps
CPU time 350.12 seconds
Started Jul 16 07:21:13 PM PDT 24
Finished Jul 16 07:27:13 PM PDT 24
Peak memory 201900 kb
Host smart-3d1cd6a0-58b4-4458-9636-43a97166125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265378129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4265378129
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.257579085
Short name T706
Test name
Test status
Simulation time 331034065067 ps
CPU time 350.48 seconds
Started Jul 16 07:21:13 PM PDT 24
Finished Jul 16 07:27:13 PM PDT 24
Peak memory 201984 kb
Host smart-78f4a0d8-6d26-445d-901b-0b5248fa37d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=257579085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.257579085
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.40285986
Short name T538
Test name
Test status
Simulation time 622160956120 ps
CPU time 1320.2 seconds
Started Jul 16 07:21:15 PM PDT 24
Finished Jul 16 07:43:24 PM PDT 24
Peak memory 201844 kb
Host smart-ca1c05c3-0768-4dc4-8aa6-dea583cb5f22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40285986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.a
dc_ctrl_filters_wakeup_fixed.40285986
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2120023742
Short name T640
Test name
Test status
Simulation time 99627863756 ps
CPU time 522.74 seconds
Started Jul 16 07:21:13 PM PDT 24
Finished Jul 16 07:30:05 PM PDT 24
Peak memory 202216 kb
Host smart-5b967c2e-075a-49ba-a330-1802d1107243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120023742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2120023742
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3701422469
Short name T371
Test name
Test status
Simulation time 23006693453 ps
CPU time 17.31 seconds
Started Jul 16 07:21:15 PM PDT 24
Finished Jul 16 07:21:41 PM PDT 24
Peak memory 201652 kb
Host smart-d3319646-8887-4cb2-8262-48eaca5cc37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701422469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3701422469
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2625651969
Short name T785
Test name
Test status
Simulation time 5177175330 ps
CPU time 6.67 seconds
Started Jul 16 07:21:14 PM PDT 24
Finished Jul 16 07:21:30 PM PDT 24
Peak memory 201628 kb
Host smart-b97c29aa-c97d-4d34-a7f6-4a4cca4aab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625651969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2625651969
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2208451910
Short name T514
Test name
Test status
Simulation time 5836557692 ps
CPU time 4.49 seconds
Started Jul 16 07:21:20 PM PDT 24
Finished Jul 16 07:21:31 PM PDT 24
Peak memory 201744 kb
Host smart-187c964a-0ce2-4fcb-ad6b-bef2462b068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208451910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2208451910
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.795936927
Short name T795
Test name
Test status
Simulation time 679005949863 ps
CPU time 1599.6 seconds
Started Jul 16 07:21:29 PM PDT 24
Finished Jul 16 07:48:14 PM PDT 24
Peak memory 201840 kb
Host smart-cddd37dd-b4ed-4401-b913-d81a3e26ae51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795936927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
795936927
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3467177376
Short name T788
Test name
Test status
Simulation time 96398473680 ps
CPU time 104.27 seconds
Started Jul 16 07:21:14 PM PDT 24
Finished Jul 16 07:23:08 PM PDT 24
Peak memory 210280 kb
Host smart-15e4477f-a0d1-4c8e-9c6b-9e760e444c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467177376 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3467177376
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.436739087
Short name T702
Test name
Test status
Simulation time 559594034 ps
CPU time 0.89 seconds
Started Jul 16 07:21:29 PM PDT 24
Finished Jul 16 07:21:36 PM PDT 24
Peak memory 201644 kb
Host smart-7c925c9d-cc5e-45d3-af34-f90f04db2cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436739087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.436739087
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3878952053
Short name T770
Test name
Test status
Simulation time 166708880622 ps
CPU time 335.16 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:27:07 PM PDT 24
Peak memory 201864 kb
Host smart-c9bcfc46-d651-41d3-b758-2c98bb86fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878952053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3878952053
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2852099671
Short name T689
Test name
Test status
Simulation time 170708450526 ps
CPU time 93 seconds
Started Jul 16 07:21:29 PM PDT 24
Finished Jul 16 07:23:07 PM PDT 24
Peak memory 201904 kb
Host smart-b0ebe052-be84-4653-9304-ddb0f42b78af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852099671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2852099671
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1363443999
Short name T564
Test name
Test status
Simulation time 161507285605 ps
CPU time 96.87 seconds
Started Jul 16 07:21:26 PM PDT 24
Finished Jul 16 07:23:08 PM PDT 24
Peak memory 201908 kb
Host smart-bf2ba5e3-598e-4fa2-abe1-003d10ca5bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363443999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1363443999
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2371203813
Short name T195
Test name
Test status
Simulation time 489589213185 ps
CPU time 590.91 seconds
Started Jul 16 07:21:30 PM PDT 24
Finished Jul 16 07:31:27 PM PDT 24
Peak memory 201864 kb
Host smart-df363354-1e9d-4710-8dad-16fde2317c53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371203813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2371203813
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1558276043
Short name T273
Test name
Test status
Simulation time 471995218103 ps
CPU time 250.62 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:25:42 PM PDT 24
Peak memory 201848 kb
Host smart-3e6c7b54-51a2-4c10-8f5a-b0e7751b42f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558276043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1558276043
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.16607954
Short name T672
Test name
Test status
Simulation time 621975524095 ps
CPU time 298.02 seconds
Started Jul 16 07:21:26 PM PDT 24
Finished Jul 16 07:26:29 PM PDT 24
Peak memory 201872 kb
Host smart-d8068cc0-82d7-4d31-87f9-045c504a1f7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.a
dc_ctrl_filters_wakeup_fixed.16607954
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1592823063
Short name T212
Test name
Test status
Simulation time 141037400007 ps
CPU time 477.39 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:29:29 PM PDT 24
Peak memory 202204 kb
Host smart-74409a3e-ec8a-4811-a0af-a5af3be3e81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592823063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1592823063
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.331693628
Short name T572
Test name
Test status
Simulation time 38109293753 ps
CPU time 83.4 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:22:56 PM PDT 24
Peak memory 201628 kb
Host smart-df910936-35b8-40fc-aeed-9bdc703d67eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331693628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.331693628
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1511391023
Short name T661
Test name
Test status
Simulation time 2901449171 ps
CPU time 2.29 seconds
Started Jul 16 07:21:29 PM PDT 24
Finished Jul 16 07:21:37 PM PDT 24
Peak memory 201628 kb
Host smart-e31d3599-5298-4a1b-94e5-b5b2385f1a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511391023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1511391023
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.988718846
Short name T394
Test name
Test status
Simulation time 5865592777 ps
CPU time 13.97 seconds
Started Jul 16 07:21:27 PM PDT 24
Finished Jul 16 07:21:46 PM PDT 24
Peak memory 201696 kb
Host smart-7a3d68e6-e9bb-40ec-b1f5-2327711d5163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988718846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.988718846
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1352824627
Short name T213
Test name
Test status
Simulation time 98814510788 ps
CPU time 556.66 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:30:50 PM PDT 24
Peak memory 202160 kb
Host smart-cef34e56-f026-4a86-8369-30bc97b158e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352824627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1352824627
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.790069109
Short name T194
Test name
Test status
Simulation time 33907178829 ps
CPU time 38.39 seconds
Started Jul 16 07:21:28 PM PDT 24
Finished Jul 16 07:22:11 PM PDT 24
Peak memory 210240 kb
Host smart-cc764177-6000-401a-a460-1732e8632272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790069109 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.790069109
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1525234063
Short name T506
Test name
Test status
Simulation time 331936821 ps
CPU time 1.4 seconds
Started Jul 16 07:16:40 PM PDT 24
Finished Jul 16 07:17:11 PM PDT 24
Peak memory 201636 kb
Host smart-d4f724d7-5732-43d5-aa62-f4a8b78019a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525234063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1525234063
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3813939952
Short name T692
Test name
Test status
Simulation time 368180034921 ps
CPU time 822.37 seconds
Started Jul 16 07:16:39 PM PDT 24
Finished Jul 16 07:30:50 PM PDT 24
Peak memory 201888 kb
Host smart-3d6bdf19-ebfc-4061-b2cc-83c0ae9f751d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813939952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3813939952
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1384186695
Short name T339
Test name
Test status
Simulation time 321526709418 ps
CPU time 369.37 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:23:23 PM PDT 24
Peak memory 201888 kb
Host smart-17425a04-b494-40b9-a5ad-98b778d22ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384186695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1384186695
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4098796164
Short name T504
Test name
Test status
Simulation time 488444521080 ps
CPU time 522.93 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:25:52 PM PDT 24
Peak memory 201864 kb
Host smart-1f260670-6cb7-4047-88be-4a2eccf16927
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098796164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4098796164
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.739034595
Short name T404
Test name
Test status
Simulation time 485590391909 ps
CPU time 1045.07 seconds
Started Jul 16 07:16:40 PM PDT 24
Finished Jul 16 07:34:34 PM PDT 24
Peak memory 201868 kb
Host smart-65c36b0a-640b-435c-bdba-43105ba615f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739034595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.739034595
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3422951809
Short name T453
Test name
Test status
Simulation time 162068017980 ps
CPU time 174.94 seconds
Started Jul 16 07:16:39 PM PDT 24
Finished Jul 16 07:20:04 PM PDT 24
Peak memory 201880 kb
Host smart-0584f7b7-62b2-4ab7-9b45-5c08c74fd4e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422951809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3422951809
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1096609030
Short name T671
Test name
Test status
Simulation time 610150518076 ps
CPU time 79.32 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:18:32 PM PDT 24
Peak memory 201140 kb
Host smart-900fac52-1071-4944-8ea9-6d491f25a4e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096609030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1096609030
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.584458000
Short name T783
Test name
Test status
Simulation time 102331825632 ps
CPU time 388.34 seconds
Started Jul 16 07:16:39 PM PDT 24
Finished Jul 16 07:23:37 PM PDT 24
Peak memory 202268 kb
Host smart-a7c571cc-eb91-49bc-98fe-efedd6b387af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584458000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.584458000
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1585599355
Short name T771
Test name
Test status
Simulation time 24144112090 ps
CPU time 11.9 seconds
Started Jul 16 07:16:39 PM PDT 24
Finished Jul 16 07:17:21 PM PDT 24
Peak memory 201688 kb
Host smart-da016fc0-482d-4855-ac26-d6ec8d5603da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585599355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1585599355
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3349820045
Short name T365
Test name
Test status
Simulation time 5364922814 ps
CPU time 12.47 seconds
Started Jul 16 07:16:49 PM PDT 24
Finished Jul 16 07:17:24 PM PDT 24
Peak memory 201688 kb
Host smart-046adf81-6672-431c-930f-61d89963b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349820045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3349820045
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3548797928
Short name T582
Test name
Test status
Simulation time 5959080752 ps
CPU time 4.47 seconds
Started Jul 16 07:16:48 PM PDT 24
Finished Jul 16 07:17:16 PM PDT 24
Peak memory 201728 kb
Host smart-28a867f7-abe0-4214-bfc9-937ffe0f6dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548797928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3548797928
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2347572341
Short name T531
Test name
Test status
Simulation time 53509855275 ps
CPU time 21.99 seconds
Started Jul 16 07:16:42 PM PDT 24
Finished Jul 16 07:17:31 PM PDT 24
Peak memory 202036 kb
Host smart-821bd015-03e5-4b39-b8d9-7d41e137d080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347572341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2347572341
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1219792228
Short name T377
Test name
Test status
Simulation time 302242806 ps
CPU time 1.27 seconds
Started Jul 16 07:16:55 PM PDT 24
Finished Jul 16 07:17:15 PM PDT 24
Peak memory 201692 kb
Host smart-4637ca1e-8e22-43fb-bfe8-2c4985a6d2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219792228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1219792228
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2404477265
Short name T525
Test name
Test status
Simulation time 334777984149 ps
CPU time 394.94 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:23:45 PM PDT 24
Peak memory 201896 kb
Host smart-c86902f1-b127-43bf-81e9-f8ec4eae1a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404477265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2404477265
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2311013399
Short name T405
Test name
Test status
Simulation time 325341359112 ps
CPU time 323.93 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:22:34 PM PDT 24
Peak memory 201976 kb
Host smart-ffd0797c-62da-408d-8097-99f736288a6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311013399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2311013399
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3371348260
Short name T622
Test name
Test status
Simulation time 332103528106 ps
CPU time 656.38 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:28:06 PM PDT 24
Peak memory 201884 kb
Host smart-8cdf1074-ab8d-4240-a5a5-a56fa4e02968
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371348260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3371348260
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2131406124
Short name T226
Test name
Test status
Simulation time 522618555562 ps
CPU time 1190.77 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:37:04 PM PDT 24
Peak memory 201892 kb
Host smart-1b244329-d6ac-457e-b7c2-351c58c67d45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131406124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2131406124
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2666135092
Short name T516
Test name
Test status
Simulation time 395586456102 ps
CPU time 783.64 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:30:13 PM PDT 24
Peak memory 201824 kb
Host smart-47606209-838e-48fe-80e8-c0cae6033cf4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666135092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2666135092
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.666599046
Short name T91
Test name
Test status
Simulation time 81152370331 ps
CPU time 438.7 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:24:28 PM PDT 24
Peak memory 202160 kb
Host smart-4aaacd59-ab0e-497d-bfdb-99f90a3e43dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666599046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.666599046
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1344478221
Short name T488
Test name
Test status
Simulation time 24584078594 ps
CPU time 10.47 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:17:21 PM PDT 24
Peak memory 201696 kb
Host smart-8ae63d78-6f67-45b8-bba1-7e6fc69bbf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344478221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1344478221
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1345813592
Short name T611
Test name
Test status
Simulation time 4114437037 ps
CPU time 5.04 seconds
Started Jul 16 07:16:40 PM PDT 24
Finished Jul 16 07:17:14 PM PDT 24
Peak memory 201636 kb
Host smart-c85f28b3-ba78-41a0-a6d3-684ae6ed8de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345813592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1345813592
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1429845008
Short name T475
Test name
Test status
Simulation time 6007740346 ps
CPU time 7.66 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:17:17 PM PDT 24
Peak memory 201692 kb
Host smart-ec0706bc-2673-45fe-be74-75da834a3ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429845008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1429845008
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2275215815
Short name T37
Test name
Test status
Simulation time 427772212946 ps
CPU time 413.32 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:24:03 PM PDT 24
Peak memory 210448 kb
Host smart-8b68ff76-8dbc-43be-b2b2-e5804ecc1633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275215815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2275215815
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.94791323
Short name T142
Test name
Test status
Simulation time 44361088056 ps
CPU time 93.82 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:18:43 PM PDT 24
Peak memory 210928 kb
Host smart-66a415df-75ed-4e5e-bf53-3a6a004105ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94791323 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.94791323
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.282576831
Short name T449
Test name
Test status
Simulation time 418417176 ps
CPU time 1.52 seconds
Started Jul 16 07:16:40 PM PDT 24
Finished Jul 16 07:17:10 PM PDT 24
Peak memory 201576 kb
Host smart-01f0137c-2064-4450-8dbd-424085e23080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282576831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.282576831
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3728617781
Short name T290
Test name
Test status
Simulation time 523022246578 ps
CPU time 1281.52 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:38:32 PM PDT 24
Peak memory 201884 kb
Host smart-eb08d6f9-a0fc-4569-b684-a45bfe0d7e0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728617781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3728617781
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.272317135
Short name T792
Test name
Test status
Simulation time 330915835249 ps
CPU time 719.57 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:29:10 PM PDT 24
Peak memory 201948 kb
Host smart-2f492636-894f-4bf0-901f-0412eca59eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272317135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.272317135
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.157539934
Short name T477
Test name
Test status
Simulation time 168294243428 ps
CPU time 95.36 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:18:45 PM PDT 24
Peak memory 201860 kb
Host smart-44e13b9c-c3c1-46e4-b8c3-5d9ed909dfdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=157539934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.157539934
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1201889351
Short name T141
Test name
Test status
Simulation time 169212654094 ps
CPU time 364.6 seconds
Started Jul 16 07:16:49 PM PDT 24
Finished Jul 16 07:23:16 PM PDT 24
Peak memory 201892 kb
Host smart-fc3f9d3a-6323-45bf-a3b5-c46ec6f5c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201889351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1201889351
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2660830297
Short name T693
Test name
Test status
Simulation time 162846587905 ps
CPU time 161.57 seconds
Started Jul 16 07:16:55 PM PDT 24
Finished Jul 16 07:19:56 PM PDT 24
Peak memory 201920 kb
Host smart-17e2cf9c-81e3-4a68-bbf8-f6bca95106ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660830297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2660830297
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.959109453
Short name T775
Test name
Test status
Simulation time 186491667014 ps
CPU time 434.12 seconds
Started Jul 16 07:16:43 PM PDT 24
Finished Jul 16 07:24:24 PM PDT 24
Peak memory 201964 kb
Host smart-501933db-2d38-4bb2-842f-ae71ed08e548
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959109453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.959109453
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2593473053
Short name T719
Test name
Test status
Simulation time 195215180733 ps
CPU time 24.86 seconds
Started Jul 16 07:16:41 PM PDT 24
Finished Jul 16 07:17:34 PM PDT 24
Peak memory 201868 kb
Host smart-093b0b0c-4ed6-4ff2-9b84-844b44954e74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593473053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2593473053
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1495438743
Short name T590
Test name
Test status
Simulation time 73515681305 ps
CPU time 389.01 seconds
Started Jul 16 07:16:55 PM PDT 24
Finished Jul 16 07:23:44 PM PDT 24
Peak memory 202256 kb
Host smart-17c9f881-c1db-4d71-9444-027c61cb6a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495438743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1495438743
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.146554796
Short name T534
Test name
Test status
Simulation time 40153385894 ps
CPU time 15.96 seconds
Started Jul 16 07:16:48 PM PDT 24
Finished Jul 16 07:17:27 PM PDT 24
Peak memory 201712 kb
Host smart-67c202db-5061-4ba1-bd05-955ccac23004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146554796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.146554796
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.553027917
Short name T732
Test name
Test status
Simulation time 4940605176 ps
CPU time 12.04 seconds
Started Jul 16 07:16:40 PM PDT 24
Finished Jul 16 07:17:21 PM PDT 24
Peak memory 201712 kb
Host smart-37cc3f99-c4f5-4261-a13f-e79210cf630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553027917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.553027917
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1746124059
Short name T428
Test name
Test status
Simulation time 5939422726 ps
CPU time 3.02 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:17:13 PM PDT 24
Peak memory 201812 kb
Host smart-50d01a99-1d49-4ea8-ba19-2b9333af04f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746124059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1746124059
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2012104488
Short name T605
Test name
Test status
Simulation time 50029904863 ps
CPU time 61.07 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:18:11 PM PDT 24
Peak memory 201812 kb
Host smart-98041496-6ee6-4a11-99e2-0e56de0e1125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012104488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2012104488
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.595399845
Short name T674
Test name
Test status
Simulation time 328811895 ps
CPU time 1.19 seconds
Started Jul 16 07:16:49 PM PDT 24
Finished Jul 16 07:17:13 PM PDT 24
Peak memory 201848 kb
Host smart-a0e1e232-d5ad-49ac-9d4b-e041e71f5f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595399845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.595399845
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.386442926
Short name T158
Test name
Test status
Simulation time 337853773191 ps
CPU time 350.4 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:23:03 PM PDT 24
Peak memory 201876 kb
Host smart-df8e21e0-5728-4886-8734-38b8b5b45730
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386442926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.386442926
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2339428383
Short name T559
Test name
Test status
Simulation time 164191439157 ps
CPU time 342.41 seconds
Started Jul 16 07:16:55 PM PDT 24
Finished Jul 16 07:22:57 PM PDT 24
Peak memory 201920 kb
Host smart-778f7dfd-b4f2-426f-b36f-a38c6fdb7b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339428383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2339428383
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.198459307
Short name T649
Test name
Test status
Simulation time 326209271374 ps
CPU time 449.41 seconds
Started Jul 16 07:16:56 PM PDT 24
Finished Jul 16 07:24:44 PM PDT 24
Peak memory 201924 kb
Host smart-74ad7b1b-7cf4-4049-8977-8dda8900d4eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=198459307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.198459307
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1452383792
Short name T173
Test name
Test status
Simulation time 501186591228 ps
CPU time 301.44 seconds
Started Jul 16 07:16:40 PM PDT 24
Finished Jul 16 07:22:10 PM PDT 24
Peak memory 201912 kb
Host smart-a84a7ded-116a-41de-9fb7-8336abd78c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452383792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1452383792
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.439052202
Short name T597
Test name
Test status
Simulation time 489781127551 ps
CPU time 1074.19 seconds
Started Jul 16 07:16:54 PM PDT 24
Finished Jul 16 07:35:08 PM PDT 24
Peak memory 201912 kb
Host smart-4f5a3e07-b578-435c-adbe-fc9c55322024
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=439052202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.439052202
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4244356463
Short name T715
Test name
Test status
Simulation time 186503342390 ps
CPU time 112.55 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:19:02 PM PDT 24
Peak memory 202008 kb
Host smart-eb9f8d20-ea50-4db0-adf2-1e833330f238
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244356463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4244356463
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3011497477
Short name T501
Test name
Test status
Simulation time 187333246280 ps
CPU time 50.36 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:18:04 PM PDT 24
Peak memory 201872 kb
Host smart-c41cbfaf-190a-4cb0-b471-1c3139a59add
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011497477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3011497477
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.728114184
Short name T219
Test name
Test status
Simulation time 143071748032 ps
CPU time 487.03 seconds
Started Jul 16 07:16:51 PM PDT 24
Finished Jul 16 07:25:20 PM PDT 24
Peak memory 202216 kb
Host smart-da86b4dc-10a3-4331-928e-b01b8652b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728114184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.728114184
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.763621169
Short name T707
Test name
Test status
Simulation time 22353088768 ps
CPU time 10.3 seconds
Started Jul 16 07:16:51 PM PDT 24
Finished Jul 16 07:17:23 PM PDT 24
Peak memory 201676 kb
Host smart-84b6c6c2-2e08-4eb3-b3ad-eb468d22efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763621169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.763621169
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3174867789
Short name T136
Test name
Test status
Simulation time 5335531496 ps
CPU time 3.55 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:17:17 PM PDT 24
Peak memory 201708 kb
Host smart-97b7270c-d59a-40f7-ae26-edf487662d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174867789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3174867789
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1654130515
Short name T372
Test name
Test status
Simulation time 6069010212 ps
CPU time 4.56 seconds
Started Jul 16 07:16:44 PM PDT 24
Finished Jul 16 07:17:15 PM PDT 24
Peak memory 201696 kb
Host smart-92dc655c-1393-4dc4-a7e0-cb4692953f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654130515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1654130515
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3437229866
Short name T329
Test name
Test status
Simulation time 605217291808 ps
CPU time 592.72 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:27:07 PM PDT 24
Peak memory 202188 kb
Host smart-8518f33c-cff5-4197-a5a3-cf43a324d3c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437229866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3437229866
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1000292315
Short name T22
Test name
Test status
Simulation time 77468300224 ps
CPU time 88.75 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:18:42 PM PDT 24
Peak memory 210148 kb
Host smart-73c656d0-e8cd-47d5-8a6e-2ef096238737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000292315 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1000292315
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.4283799807
Short name T712
Test name
Test status
Simulation time 383589142 ps
CPU time 0.85 seconds
Started Jul 16 07:16:52 PM PDT 24
Finished Jul 16 07:17:14 PM PDT 24
Peak memory 201692 kb
Host smart-43237733-9401-4b3c-93e7-3ef4e113fc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283799807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4283799807
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2843706866
Short name T602
Test name
Test status
Simulation time 163980911348 ps
CPU time 357.34 seconds
Started Jul 16 07:16:54 PM PDT 24
Finished Jul 16 07:23:12 PM PDT 24
Peak memory 201952 kb
Host smart-06866168-bcf3-4ba4-b4b8-8f182d58a8cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843706866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2843706866
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.985773239
Short name T154
Test name
Test status
Simulation time 164948420534 ps
CPU time 355.9 seconds
Started Jul 16 07:16:59 PM PDT 24
Finished Jul 16 07:23:11 PM PDT 24
Peak memory 201916 kb
Host smart-8faeb537-aae6-4c49-9c28-8a59293fcfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985773239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.985773239
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2540894158
Short name T681
Test name
Test status
Simulation time 343204071434 ps
CPU time 71.62 seconds
Started Jul 16 07:16:51 PM PDT 24
Finished Jul 16 07:18:24 PM PDT 24
Peak memory 201980 kb
Host smart-711adba0-8798-4c69-a064-8380171b02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540894158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2540894158
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.741358925
Short name T653
Test name
Test status
Simulation time 338422053719 ps
CPU time 189.18 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:20:22 PM PDT 24
Peak memory 202004 kb
Host smart-ec5592df-63de-4efc-95e2-ddbff4b689d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=741358925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.741358925
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.864102433
Short name T395
Test name
Test status
Simulation time 161041983632 ps
CPU time 330.37 seconds
Started Jul 16 07:16:54 PM PDT 24
Finished Jul 16 07:22:45 PM PDT 24
Peak memory 201928 kb
Host smart-9b452a23-4cfe-4b93-8758-e232df091859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864102433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.864102433
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.919256983
Short name T431
Test name
Test status
Simulation time 167082516117 ps
CPU time 337.99 seconds
Started Jul 16 07:16:58 PM PDT 24
Finished Jul 16 07:22:53 PM PDT 24
Peak memory 201868 kb
Host smart-8fdd234f-ed61-4219-966c-79edd6d9d123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919256983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.919256983
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.15177679
Short name T660
Test name
Test status
Simulation time 354605814038 ps
CPU time 671.54 seconds
Started Jul 16 07:16:54 PM PDT 24
Finished Jul 16 07:28:25 PM PDT 24
Peak memory 201944 kb
Host smart-bcffaac4-9319-4a5f-81ce-c1170f9e78c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15177679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wa
keup.15177679
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4242385071
Short name T794
Test name
Test status
Simulation time 401668650062 ps
CPU time 728.89 seconds
Started Jul 16 07:16:51 PM PDT 24
Finished Jul 16 07:29:22 PM PDT 24
Peak memory 201900 kb
Host smart-7b88fa7d-2925-4b88-b5f7-4b3d2afd8224
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242385071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4242385071
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1797342682
Short name T408
Test name
Test status
Simulation time 42397332440 ps
CPU time 87.57 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:18:42 PM PDT 24
Peak memory 201260 kb
Host smart-98a9a563-ed0b-43a7-a548-b3e35a5c7596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797342682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1797342682
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1634206100
Short name T497
Test name
Test status
Simulation time 4321245434 ps
CPU time 6.67 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:17:21 PM PDT 24
Peak memory 201392 kb
Host smart-f52c9e23-b6d3-4c39-b336-f74820e50a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634206100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1634206100
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4055296470
Short name T560
Test name
Test status
Simulation time 5979092347 ps
CPU time 3.03 seconds
Started Jul 16 07:16:53 PM PDT 24
Finished Jul 16 07:17:17 PM PDT 24
Peak memory 201652 kb
Host smart-2ec74c71-adee-4122-b051-700b51bac748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055296470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4055296470
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2379975325
Short name T747
Test name
Test status
Simulation time 173119079960 ps
CPU time 79.22 seconds
Started Jul 16 07:16:59 PM PDT 24
Finished Jul 16 07:18:35 PM PDT 24
Peak memory 201884 kb
Host smart-4f907242-4c5f-4696-86a8-4125429b5c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379975325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2379975325
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2091217817
Short name T332
Test name
Test status
Simulation time 46560287473 ps
CPU time 135.24 seconds
Started Jul 16 07:16:55 PM PDT 24
Finished Jul 16 07:19:29 PM PDT 24
Peak memory 218100 kb
Host smart-dce81261-5fcc-49dc-b415-5647f5d8ae47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091217817 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2091217817
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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