Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7180	1			T4	3		T6	5		T8	59
testmodes[AdcCtrlTestmodeNormal]	5735	1			T2	1		T3	2		T4	10
testmodes[AdcCtrlTestmodeLowpower]	6142	1			T1	1		T4	1		T5	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3813	1			T6	2		T8	55		T9	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1803	1			T4	3		T6	2		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1453	1			T8	1		T40	21		T30	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1835	1			T4	3		T6	3		T8	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2123	1			T3	1		T4	5		T6	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1445	1			T4	1		T43	1		T40	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1432	1			T40	20		T29	1		T44	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1466	1			T4	1		T40	13		T29	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2988	1			T5	10		T8	14		T25	2