Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23690

1

T3

11

T4

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3750

1

T1

15

T2

11

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21389

1

T4

18

T5

11

T6

11

auto[1]

6051

1

T1

15

T2

11

T3

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	309	1			T4	2		T13	16		T159	1
values[1]	821	1			T1	15		T4	6		T11	1
values[2]	595	1			T7	26		T11	3		T12	3
values[3]	806	1			T25	22		T39	18		T133	26
values[4]	652	1			T11	8		T38	12		T109	9
values[5]	2961	1			T3	11		T24	3		T25	21
values[6]	765	1			T2	11		T109	16		T29	1
values[7]	789	1			T25	8		T39	7		T138	19
values[8]	657	1			T133	15		T31	9		T107	14
values[9]	989	1			T8	20		T10	23		T138	37
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	767	1			T4	6		T11	1		T12	3
values[1]	559	1			T7	26		T11	3		T109	4
values[2]	747	1			T25	22		T38	12		T39	18
values[3]	2985	1			T3	11		T11	8		T24	3
values[4]	708	1			T29	13		T129	13		T155	1
values[5]	859	1			T2	11		T109	16		T29	1
values[6]	676	1			T25	8		T39	7		T138	19
values[7]	672	1			T133	15		T138	28		T31	9
values[8]	983	1			T4	2		T8	20		T10	23
values[9]	140	1			T132	16		T198	20		T199	22
minimum	18344	1			T1	15		T4	10		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T200	10		T14	11		T136	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	3		T11	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T109	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T7	14		T134	1		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	22		T133	14		T106	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T38	1		T39	18		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T3	2		T24	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T25	21		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T129	5		T155	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T29	8		T197	16		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	1		T130	3		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	1		T109	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T99	1		T165	12		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T25	8		T39	7		T138	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T107	14		T32	8		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	3		T138	14		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	11		T138	9		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T4	2		T8	9		T13	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T132	1		T19	2		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T198	11		T199	12		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18041	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T1	4		T145	1		T18	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	10		T197	5		T204	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	3		T12	2		T205	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	2		T109	3		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	12		T134	8		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	12		T106	5		T32	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	11		T194	7		T33	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T3	9		T26	15		T137	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	7		T129	18		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T129	8		T132	10		T148	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	5		T197	10		T50	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T130	4		T99	9		T106	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	10		T109	15		T194	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T201	1		T158	12		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T138	9		T135	17		T14	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	11		T147	7		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T133	12		T138	14		T31	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	12		T135	4		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	11		T194	21		T32	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T132	15		T206	7		T207	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T198	9		T199	10		T203	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T1	11		T18	7		T164	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T208	1		T209	5		T19	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T4	2		T13	16		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	11		T197	5		T210	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	4		T4	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T109	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	14		T12	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T25	22		T133	14		T106	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	18		T194	8		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T109	1		T43	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T38	1		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T3	2		T24	3		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T25	21		T29	8		T197	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	1		T130	3		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	1		T109	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T99	1		T201	1		T158	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T25	8		T39	7		T138	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T107	14		T145	11		T32	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T133	3		T31	4		T210	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T10	11		T138	9		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	9		T138	14		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T208	11		T209	12		T211	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T212	10		T191	17		T199	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	10		T197	5		T204	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	11		T4	3		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	2		T109	3		T133	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	12		T12	2		T134	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T133	12		T106	5		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T194	7		T33	4		T201	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T109	8		T43	13		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	7		T38	11		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T3	9		T26	15		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	5		T197	10		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	4		T99	9		T106	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	10		T109	15		T50	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T201	1		T158	12		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T138	9		T135	17		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	10		T32	11		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T133	12		T31	5		T156	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T10	12		T135	4		T132	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	11		T138	14		T194	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T200	1		T14	11		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	5		T11	1		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	3		T109	4		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	13		T134	9		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	1		T133	13		T106	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T38	12		T39	1		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T3	11		T24	3		T26	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	8		T25	1		T129	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	9		T155	1		T132	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T29	10		T197	11		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T29	1		T130	5		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	11		T109	16		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T99	1		T165	1		T201	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T25	1		T39	1		T138	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T107	1		T32	13		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	13		T138	15		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T10	13		T138	1		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	2		T8	17		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T132	16		T19	2		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T198	10		T199	11		T203	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18160	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T1	12		T145	1		T18	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T200	9		T14	10		T136	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	1		T200	7		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T133	13		T129	8		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T7	13		T149	3		T16	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T25	21		T133	13		T106	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	17		T194	7		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T37	7		T38	2		T214	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	20		T129	10		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T129	4		T215	3		T147	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T29	3		T197	15		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T130	2		T106	12		T186	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T194	12		T100	3		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T165	11		T158	11		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T25	7		T39	6		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T107	13		T32	6		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T133	2		T138	13		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	10		T138	8		T136	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	3		T13	15		T194	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T206	8		T207	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T198	10		T199	11		T216	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T217	11		T218	2		T219	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T1	3		T18	6		T220	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T208	12		T209	13		T19	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	2		T13	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	11		T197	6		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	12		T4	5		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	3		T109	4		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	13		T12	3		T134	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T25	1		T133	13		T106	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	1		T194	8		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T109	9		T43	14		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	8		T38	12		T129	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T3	11		T24	3		T26	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	1		T29	10		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	1		T130	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T2	11		T109	16		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T99	1		T201	2		T158	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T25	1		T39	1		T138	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T107	1		T145	11		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T133	13		T31	9		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T10	13		T138	1		T135	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	17		T138	15		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T209	4		T221	12		T211	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T13	15		T212	3		T191	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	10		T197	4		T210	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	3		T4	1		T200	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T133	13		T129	8		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	13		T213	9		T149	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T25	21		T133	13		T106	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	17		T194	7		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T50	5		T139	8		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T129	10		T130	12		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T37	7		T38	2		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	20		T29	3		T197	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T130	2		T106	12		T222	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T50	2		T194	12		T100	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	11		T151	11		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T25	7		T39	6		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T107	13		T145	10		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T133	2		T210	10		T223	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	10		T138	8		T136	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	3		T138	13		T194	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21743

1

T1

15

T4

16

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

5697

1

T2

11

T3

11

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21280

1

T1

15

T4

12

T5

11

auto[1]

6160

1

T2

11

T3

11

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T141	1		T174	11		-	-
values[0]	18	1			T132	1		T224	13		T225	3
values[1]	515	1			T1	15		T25	22		T130	7
values[2]	572	1			T11	3		T38	12		T130	23
values[3]	900	1			T11	1		T109	9		T39	1
values[4]	965	1			T2	11		T7	26		T8	20
values[5]	692	1			T25	8		T38	11		T109	4
values[6]	687	1			T4	6		T12	3		T30	1
values[7]	815	1			T39	25		T133	26		T129	46
values[8]	679	1			T10	23		T25	21		T29	1
values[9]	3489	1			T3	11		T4	2		T11	8
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	704	1			T1	15		T25	22		T130	30
values[1]	2975	1			T3	11		T11	4		T24	3
values[2]	900	1			T2	11		T13	16		T39	1
values[3]	847	1			T7	26		T8	20		T133	27
values[4]	698	1			T25	8		T38	11		T109	4
values[5]	618	1			T4	6		T12	3		T129	29
values[6]	846	1			T39	25		T133	26		T129	17
values[7]	730	1			T10	23		T25	21		T29	1
values[8]	765	1			T11	8		T109	16		T43	14
values[9]	248	1			T4	2		T194	35		T158	24
minimum	18109	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	4		T25	22		T130	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T130	13		T200	12		T50	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	2		T109	1		T29	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1590	1			T3	2		T24	3		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	16		T39	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	1		T129	5		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T134	1		T136	3		T194	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	14		T8	9		T133	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	3		T138	10		T197	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T25	8		T109	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	3		T12	1		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T99	1		T132	9		T139	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T133	14		T129	9		T200	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	25		T32	2		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	11		T135	1		T106	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	21		T29	1		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T109	1		T43	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T223	9		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T194	14		T17	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T4	2		T158	12		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T224	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	11		T130	4		T205	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T130	10		T50	5		T194	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	2		T109	8		T29	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1047	1			T3	9		T26	15		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	12		T30	1		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	10		T129	8		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T134	8		T194	10		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	12		T8	11		T133	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T38	8		T138	9		T197	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T109	3		T148	4		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	3		T12	2		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T132	9		T139	2		T150	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	12		T129	8		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	1		T201	7		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T10	12		T135	2		T106	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T35	5		T16	3		T212	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T109	15		T43	13		T135	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	7		T219	12		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T194	21		T226	10		T144	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T158	12		T208	2		T195	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T141	1		T174	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T132	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T224	13		T225	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	4		T25	22		T130	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T200	12		T50	6		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	1		T138	9		T197	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	1		T130	13		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	1		T109	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T129	5		T210	17		T198	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	16		T131	1		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	1		T7	14		T8	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T38	3		T138	10		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	8		T109	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	3		T12	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	1		T99	1		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T133	14		T129	20		T200	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	25		T32	2		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	11		T100	4		T106	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	21		T29	1		T154	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T109	1		T43	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1704	1			T3	2		T4	2		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T1	11		T130	4		T205	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T50	5		T213	11		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	2		T197	5		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	11		T130	10		T194	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T109	8		T29	5		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T129	8		T198	9		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	11		T194	10		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	10		T7	12		T8	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	8		T138	9		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T109	3		T135	4		T14	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	3		T12	2		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T132	9		T148	4		T139	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T133	12		T129	26		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T32	1		T201	7		T150	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	12		T100	10		T106	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T35	5		T36	1		T160	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T109	15		T43	13		T135	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1101	1			T3	9		T11	7		T26	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3