Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23686

1

T3

11

T4

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3754

1

T1

15

T2

11

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21579

1

T4

12

T5

11

T6

11

auto[1]

5861

1

T1

15

T2

11

T3

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T156	1		T247	5		T279	10
values[0]	92	1			T43	14		T39	18		T200	8
values[1]	756	1			T7	26		T130	23		T200	12
values[2]	827	1			T8	20		T10	23		T11	3
values[3]	583	1			T4	2		T25	22		T30	2
values[4]	664	1			T29	1		T133	15		T106	22
values[5]	3057	1			T3	11		T24	3		T25	21
values[6]	883	1			T11	8		T38	11		T39	7
values[7]	563	1			T1	15		T109	20		T130	7
values[8]	596	1			T129	17		T154	2		T134	9
values[9]	1295	1			T2	11		T4	6		T11	1
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1042	1			T7	26		T8	20		T38	12
values[1]	723	1			T10	23		T12	3		T13	16
values[2]	626	1			T11	3		T25	22		T133	15
values[3]	2990	1			T3	11		T4	2		T24	3
values[4]	901	1			T25	21		T133	26		T129	13
values[5]	653	1			T11	8		T38	11		T109	4
values[6]	643	1			T1	15		T109	16		T129	17
values[7]	556	1			T11	1		T25	8		T154	1
values[8]	1036	1			T2	11		T4	6		T29	13
values[9]	171	1			T39	1		T200	10		T147	5
minimum	18099	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T43	1		T200	12		T14	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T7	14		T8	9		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T194	8		T106	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	11		T13	16		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T25	22		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T135	1		T210	17		T198	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T3	2		T24	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	2		T29	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T25	21		T129	5		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T133	14		T155	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T109	1		T130	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T38	3		T39	7		T197	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T138	9		T151	12		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	4		T109	1		T129	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T154	1		T134	1		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T25	8		T204	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T29	8		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T4	3		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T39	1		T200	10		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T17	2		T144	13		T247	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T43	13		T14	8		T194	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	12		T8	11		T38	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	2		T194	7		T106	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	12		T109	8		T129	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T11	2		T133	12		T150	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T135	15		T198	9		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T3	9		T26	15		T137	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T30	1		T50	11		T194	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T129	8		T138	9		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T133	12		T135	2		T14	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T11	7		T109	3		T130	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	8		T197	5		T106	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T142	10		T162	12		T219	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	11		T109	15		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T134	8		T50	5		T156	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T204	13		T201	6		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T29	5		T135	4		T204	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	10		T4	3		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T147	2		T36	1		T144	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T144	9		T247	2		T249	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T280	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T279	1		T179	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T156	1		T247	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T43	1		T223	9		T281	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T39	18		T200	8		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T200	12		T14	12		T136	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	14		T130	13		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	1		T12	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T8	9		T10	11		T13	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T25	22		T131	1		T100	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	2		T30	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T133	3		T157	14		T165	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	1		T106	13		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T3	2		T24	3		T25	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T133	14		T14	11		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	1		T129	5		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T38	3		T39	7		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T109	1		T130	3		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	4		T109	1		T197	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	2		T134	1		T156	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T129	9		T204	15		T257	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T39	1		T29	8		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T4	3		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T279	9		T179	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T43	13		T281	15		T282	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T99	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	8		T194	10		T204	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	12		T130	10		T213	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	2		T12	2		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	11		T10	12		T38	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T100	10		T146	2		T150	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	1		T135	15		T132	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T133	12		T199	3		T78	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T106	9		T132	15		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T3	9		T26	15		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T133	12		T14	10		T50	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	7		T129	8		T138	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T38	8		T135	2		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T109	3		T130	4		T162	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	11		T109	15		T197	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T134	8		T156	1		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T129	8		T204	13		T257	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T29	5		T135	4		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	10		T4	3		T145	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T43	14		T200	1		T14	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	13		T8	17		T38	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	3		T194	8		T106	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	13		T13	1		T109	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	3		T25	1		T133	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T135	16		T210	1		T198	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T3	11		T24	3		T26	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	2		T29	1		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T25	1		T129	9		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T133	13		T155	1		T135	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	8		T109	4		T130	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	9		T39	1		T197	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T138	1		T151	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	12		T109	16		T129	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T154	1		T134	9		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	1		T25	1		T204	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T29	10		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	11		T4	5		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T39	1		T200	1		T147	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T17	1		T144	10		T247	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T280	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T200	11		T14	10		T136	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	13		T8	3		T39	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T194	7		T106	9		T107	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	10		T13	15		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T25	21		T133	2		T150	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T210	16		T198	10		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T37	7		T214	24		T230	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	2		T194	13		T106	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	20		T129	4		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T133	13		T14	10		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T130	2		T138	13		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	2		T39	6		T197	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T138	8		T151	11		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	3		T129	8		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T50	5		T156	16		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T25	7		T204	14		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T29	3		T136	2		T204	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	1		T145	10		T15	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T200	9		T283	11		T284	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T17	1		T144	12		T247	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T279	10		T179	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T156	1		T247	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T43	14		T223	1		T281	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T39	1		T200	1		T99	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T200	1		T14	10		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	13		T130	11		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	3		T12	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	17		T10	13		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T25	1		T131	1		T100	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	2		T30	2		T135	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T133	13		T157	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T29	1		T106	10		T132	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T3	11		T24	3		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T133	13		T14	11		T50	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	8		T129	9		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T38	9		T39	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T109	4		T130	5		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	12		T109	16		T197	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	2		T134	9		T156	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T129	9		T204	14		T257	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	466	1			T39	1		T29	10		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T2	11		T4	5		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T223	8		T281	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T39	17		T200	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T200	11		T14	10		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T130	12		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T194	7		T106	9		T107	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	3		T10	10		T13	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	21		T100	3		T146	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	8		T210	16		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T133	2		T157	13		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T106	12		T223	14		T198	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T25	20		T37	7		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T133	13		T14	10		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T129	4		T138	13		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T38	2		T39	6		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	2		T138	8		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T1	3		T197	4		T106	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T156	16		T151	11		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T129	8		T204	14		T257	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T29	3		T200	9		T136	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T25	7		T145	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13