Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23846

1

T1

15

T3

11

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3594

1

T2

11

T8

20

T11

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21201

1

T2

11

T4

18

T5

11

auto[1]

6239

1

T1

15

T3

11

T10

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	68	1			T199	11		T285	1		T286	1
values[0]	73	1			T199	22		T226	6		T85	16
values[1]	619	1			T4	2		T130	23		T135	21
values[2]	625	1			T25	21		T29	1		T138	9
values[3]	688	1			T2	11		T11	4		T25	22
values[4]	747	1			T10	23		T13	16		T129	29
values[5]	850	1			T25	8		T38	12		T43	14
values[6]	942	1			T7	26		T11	8		T29	13
values[7]	495	1			T38	11		T39	1		T130	7
values[8]	3183	1			T3	11		T4	6		T8	20
values[9]	1054	1			T1	15		T12	3		T109	16
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	923	1			T4	2		T130	23		T135	21
values[1]	546	1			T2	11		T11	3		T25	43
values[2]	797	1			T10	23		T11	1		T109	4
values[3]	687	1			T13	16		T43	14		T129	29
values[4]	945	1			T11	8		T25	8		T38	12
values[5]	764	1			T7	26		T38	11		T29	13
values[6]	2811	1			T3	11		T4	6		T24	3
values[7]	812	1			T8	20		T39	7		T30	1
values[8]	989	1			T1	15		T12	3		T109	16
values[9]	65	1			T39	18		T237	7		T195	7
minimum	18101	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	2		T130	13		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T135	1		T197	16		T106	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	1		T25	22		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	1		T25	21		T138	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	11		T11	1		T133	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T109	1		T133	3		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T129	11		T30	1		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	16		T43	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T25	8		T129	5		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	1		T38	1		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	14		T29	8		T200	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	3		T138	14		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T3	2		T4	3		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T130	3		T14	11		T223	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T39	7		T131	1		T223	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	9		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T1	4		T12	1		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T149	4		T33	7		T146	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T39	18		T202	10		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T237	1		T195	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T247	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T130	10		T135	4		T50	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T135	15		T197	10		T106	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	2		T215	4		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	10		T132	10		T32	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	12		T133	12		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T109	3		T133	12		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	18		T30	1		T205	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	13		T194	21		T147	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T129	8		T194	10		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	7		T38	11		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	12		T29	5		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	8		T138	14		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T3	9		T4	3		T26	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	4		T14	10		T32	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	1		T201	6		T275	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	11		T134	8		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	11		T12	2		T109	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T149	9		T33	4		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T202	10		T250	7		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T237	6		T195	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T199	8		T285	1		T286	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T287	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T288	1		T289	6		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T199	12		T226	1		T85	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	2		T130	13		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T135	1		T197	16		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	1		T99	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	21		T138	9		T106	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	2		T25	22		T133	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T109	1		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	11		T129	11		T198	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	16		T194	14		T106	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T25	8		T30	1		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T38	1		T43	1		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T7	14		T29	8		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T133	14		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	1		T145	1		T204	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	3		T130	3		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T3	2		T4	3		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	9		T154	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T1	4		T12	1		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T149	4		T33	7		T146	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T199	3		T291	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T289	1		T290	7		T292	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T199	10		T226	5		T85	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T130	10		T135	4		T50	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T135	15		T197	10		T213	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T99	9		T148	6		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T106	5		T132	10		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	2		T133	12		T129	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	10		T109	3		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	12		T129	18		T198	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T194	21		T106	9		T147	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	1		T194	10		T205	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	11		T43	13		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	12		T29	5		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	7		T133	13		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T204	10		T139	2		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T38	8		T130	4		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T3	9		T4	3		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	11		T134	8		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	11		T12	2		T109	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T149	9		T33	4		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T4	2		T130	11		T135	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T135	16		T197	11		T106	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	3		T25	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	11		T25	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	13		T11	1		T133	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T109	4		T133	13		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T129	19		T30	2		T205	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T43	14		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T25	1		T129	9		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	8		T38	12		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	13		T29	10		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	9		T138	15		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T3	11		T4	5		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T130	5		T14	11		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	1		T131	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	17		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	12		T12	3		T109	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T149	10		T33	9		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T39	1		T202	11		T250	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T237	7		T195	7		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T247	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T130	12		T50	2		T100	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T197	15		T106	5		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T25	21		T215	3		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T25	20		T138	8		T200	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	10		T133	13		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T133	2		T14	10		T106	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T129	10		T198	12		T146	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	15		T194	13		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T25	7		T129	4		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	13		T138	9		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	13		T29	3		T200	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	2		T138	13		T107	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T4	1		T37	7		T214	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T130	2		T14	10		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	6		T223	8		T218	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	3		T136	18		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	3		T200	9		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T149	3		T33	2		T146	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T39	17		T202	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T199	4		T285	1		T286	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T287	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T288	1		T289	6		T290	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T199	11		T226	6		T85	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	2		T130	11		T135	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T135	16		T197	11		T213	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T29	1		T99	10		T148	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	1		T138	1		T106	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	4		T25	1		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	11		T109	4		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	13		T129	19		T198	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T194	22		T106	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T25	1		T30	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T38	12		T43	14		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T7	13		T29	10		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	8		T133	14		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T39	1		T145	1		T204	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T38	9		T130	5		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T3	11		T4	5		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	17		T154	1		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	12		T12	3		T109	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T149	10		T33	9		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T199	7		T291	20		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T287	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T199	11		T85	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T130	12		T50	2		T100	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T197	15		T213	9		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T215	3		T91	4		T293	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	20		T138	8		T106	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T25	21		T133	13		T129	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T133	2		T200	11		T14	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	10		T129	10		T198	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	15		T194	13		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	7		T136	2		T194	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T138	9		T197	4		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	13		T29	3		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T133	13		T138	13		T107	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T204	10		T139	2		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T38	2		T130	2		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T4	1		T37	7		T200	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	3		T136	18		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	3		T39	23		T194	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T149	3		T33	2		T146	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13