Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23702

1

T3

11

T4

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3738

1

T1

15

T2

11

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21401

1

T4

18

T5

11

T6

11

auto[1]

6039

1

T1

15

T2

11

T3

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T150	10		T177	1		T294	12
values[0]	51	1			T221	26		T259	22		T184	2
values[1]	789	1			T1	15		T4	6		T11	1
values[2]	561	1			T7	26		T11	3		T12	3
values[3]	797	1			T25	22		T133	26		T130	23
values[4]	697	1			T11	8		T38	12		T109	9
values[5]	2989	1			T3	11		T24	3		T25	21
values[6]	699	1			T2	11		T109	16		T29	1
values[7]	824	1			T25	8		T39	7		T138	19
values[8]	615	1			T133	15		T154	1		T31	9
values[9]	1288	1			T4	2		T8	20		T10	23
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1041	1			T1	15		T7	26		T11	1
values[1]	526	1			T4	6		T11	3		T109	4
values[2]	698	1			T25	22		T38	12		T39	18
values[3]	3065	1			T3	11		T11	8		T24	3
values[4]	706	1			T29	14		T129	13		T155	1
values[5]	751	1			T2	11		T109	16		T130	7
values[6]	732	1			T25	8		T39	7		T138	19
values[7]	703	1			T133	15		T138	28		T31	9
values[8]	892	1			T4	2		T8	20		T10	23
values[9]	213	1			T138	9		T136	19		T194	35
minimum	18113	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T129	9		T200	10		T14	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	4		T7	14		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	1		T109	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T4	3		T134	1		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	22		T133	14		T106	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T38	1		T39	18		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T3	2		T24	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	1		T25	21		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	1		T129	5		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T29	8		T197	16		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T130	3		T131	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T109	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T99	1		T165	12		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T25	8		T39	7		T138	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T107	14		T32	8		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T133	3		T138	14		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	11		T135	1		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	2		T8	9		T13	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T138	9		T136	19		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T194	14		T198	11		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17955	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T129	8		T14	10		T197	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	11		T7	12		T12	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	2		T109	3		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	3		T134	8		T213	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T133	12		T106	5		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	11		T194	7		T33	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T3	9		T26	15		T137	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	7		T129	18		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T129	8		T132	10		T148	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T29	5		T197	10		T50	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T130	4		T99	9		T106	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	10		T109	15		T194	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T201	1		T27	11		T161	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T138	9		T135	17		T14	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	11		T147	7		T158	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T133	12		T138	14		T31	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	12		T135	4		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	11		T32	2		T261	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T132	15		T206	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T194	21		T198	9		T142	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T295	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T150	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T177	1		T294	7		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T221	26		T184	2		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T259	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T39	1		T14	11		T197	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	4		T4	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T109	1		T133	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	14		T12	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T25	22		T133	14		T106	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T130	13		T194	8		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T109	1		T43	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T38	1		T39	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T3	2		T24	3		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T25	21		T29	8		T197	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	1		T130	3		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T109	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T99	1		T201	1		T158	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T25	8		T39	7		T138	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T107	14		T145	11		T32	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	3		T154	1		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T10	11		T138	9		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T4	2		T8	9		T13	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T150	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T294	5		T296	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	10		T197	5		T204	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	11		T4	3		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	2		T109	3		T133	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	12		T12	2		T134	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T133	12		T106	5		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	10		T194	7		T33	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T109	8		T43	13		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	7		T38	11		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T3	9		T26	15		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T29	5		T197	10		T100	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T130	4		T99	9		T106	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	10		T109	15		T50	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T201	1		T158	12		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	9		T135	17		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T145	10		T32	11		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	12		T31	5		T156	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T10	12		T135	4		T132	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	11		T138	14		T194	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T129	9		T200	1		T14	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	12		T7	13		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	3		T109	4		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	5		T134	9		T213	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	1		T133	13		T106	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T38	12		T39	1		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T3	11		T24	3		T26	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	8		T25	1		T129	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	1		T129	9		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T29	10		T197	11		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T130	5		T131	1		T99	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	11		T109	16		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T99	1		T165	1		T201	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	1		T39	1		T138	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T107	1		T32	13		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T133	13		T138	15		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	13		T135	5		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	2		T8	17		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T138	1		T136	1		T132	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T194	22		T198	10		T142	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18099	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T295	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T129	8		T200	9		T14	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	3		T7	13		T200	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T133	13		T149	11		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T4	1		T213	9		T149	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T25	21		T133	13		T106	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	17		T194	7		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T37	7		T38	2		T214	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	20		T129	10		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T129	4		T147	2		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	3		T197	15		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T130	2		T106	12		T215	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T194	12		T100	3		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T165	11		T151	11		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T25	7		T39	6		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T107	13		T32	6		T158	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	2		T138	13		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	10		T145	10		T204	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	3		T13	15		T157	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T138	8		T136	18		T206	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T194	13		T198	10		T212	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T150	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T177	1		T294	6		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T221	1		T184	1		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T259	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T39	1		T14	11		T197	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	12		T4	5		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	3		T109	4		T133	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T12	3		T134	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	1		T133	13		T106	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	11		T194	8		T33	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T109	9		T43	14		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	8		T38	12		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T3	11		T24	3		T26	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T25	1		T29	10		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T29	1		T130	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T2	11		T109	16		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T99	1		T201	2		T158	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T25	1		T39	1		T138	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T107	1		T145	11		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	13		T154	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T10	13		T138	1		T135	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T4	2		T8	17		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T150	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T294	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T221	25		T184	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T259	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	10		T197	4		T210	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	3		T4	1		T200	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	13		T129	8		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	13		T213	9		T149	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	21		T133	13		T106	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T130	12		T194	7		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T50	5		T139	8		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T39	17		T129	10		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T37	7		T38	2		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T25	20		T29	3		T197	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T130	2		T106	12		T222	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	2		T198	2		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T158	11		T151	11		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T25	7		T39	6		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T107	13		T145	10		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T133	2		T210	10		T223	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T10	10		T138	8		T136	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T8	3		T13	15		T138	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13