Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23607

1

T3

11

T4

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3833

1

T1

15

T2

11

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21428

1

T1

15

T4

12

T5

11

auto[1]

6012

1

T2

11

T3

11

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	330	1			T2	11		T39	1		T135	5
values[0]	45	1			T39	18		T200	8		T99	10
values[1]	849	1			T7	26		T13	16		T43	14
values[2]	799	1			T8	20		T10	23		T11	3
values[3]	509	1			T25	22		T133	15		T135	16
values[4]	762	1			T4	2		T29	1		T30	2
values[5]	3074	1			T3	11		T24	3		T25	21
values[6]	853	1			T11	8		T38	11		T39	7
values[7]	541	1			T1	15		T109	20		T130	7
values[8]	631	1			T25	8		T129	17		T154	1
values[9]	951	1			T4	6		T11	1		T29	13
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	786	1			T8	20		T13	16		T38	12
values[1]	652	1			T10	23		T11	3		T12	3
values[2]	626	1			T4	2		T25	22		T133	15
values[3]	2997	1			T3	11		T24	3		T26	17
values[4]	909	1			T25	21		T133	26		T129	13
values[5]	692	1			T11	8		T38	11		T109	4
values[6]	596	1			T1	15		T109	16		T129	17
values[7]	630	1			T11	1		T25	8		T154	1
values[8]	1012	1			T2	11		T4	6		T29	13
values[9]	134	1			T39	1		T200	10		T35	16
minimum	18406	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T43	1		T200	12		T14	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	9		T13	16		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T12	1		T194	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	11		T109	1		T129	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	22		T133	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	2		T135	1		T210	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T3	2		T24	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T29	1		T30	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	21		T129	5		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T133	14		T138	10		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T109	1		T39	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T38	3		T138	14		T197	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T138	9		T151	12		T162	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	4		T109	1		T129	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T154	1		T134	1		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	1		T25	8		T204	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T29	8		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	1		T4	3		T136	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T200	10		T35	11		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T39	1		T17	2		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18038	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T7	14		T200	8		T131	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	13		T14	8		T194	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	11		T38	11		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T11	2		T12	2		T194	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	12		T109	8		T129	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T133	12		T100	10		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T135	15		T198	9		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T3	9		T26	15		T137	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	1		T132	15		T147	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T129	8		T135	2		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T133	12		T138	9		T14	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	7		T109	3		T130	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	8		T138	14		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T162	12		T219	17		T208	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	11		T109	15		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T134	8		T50	5		T156	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T204	13		T201	6		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T29	5		T135	4		T204	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	10		T4	3		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T35	5		T298	13		T284	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T249	7		T202	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	12		T99	9		T147	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T135	1		T200	10		T147	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T2	1		T39	1		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T223	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T39	18		T200	8		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T43	1		T200	12		T14	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	14		T13	16		T130	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	1		T12	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T8	9		T10	11		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	22		T133	3		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T135	1		T132	9		T210	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	3		T106	13		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	2		T29	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T3	2		T24	3		T25	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T133	14		T138	10		T14	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	1		T39	7		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T38	3		T138	14		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T109	1		T130	3		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	4		T109	1		T106	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T154	1		T134	1		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	8		T129	9		T204	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T29	8		T30	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	3		T11	1		T136	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T135	4		T147	2		T144	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T2	10		T145	10		T34	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T99	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T43	13		T14	8		T194	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	12		T130	10		T213	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	2		T12	2		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	11		T10	12		T38	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T133	12		T100	10		T215	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	15		T132	9		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T50	11		T106	9		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T30	1		T132	15		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T3	9		T26	15		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T133	12		T138	9		T14	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	7		T129	8		T135	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T38	8		T138	14		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T109	3		T130	4		T197	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	11		T109	15		T106	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T134	8		T50	5		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T129	8		T204	13		T257	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T29	5		T204	3		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	3		T201	6		T15	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T43	14		T200	1		T14	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	17		T13	1		T38	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T11	3		T12	3		T194	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	13		T109	9		T129	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T25	1		T133	13		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	2		T135	16		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T3	11		T24	3		T26	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T29	1		T30	2		T132	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T25	1		T129	9		T135	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T133	13		T138	10		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	8		T109	4		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T38	9		T138	15		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T138	1		T151	1		T162	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	12		T109	16		T129	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T154	1		T134	9		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	1		T25	1		T204	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T29	10		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	11		T4	5		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T200	1		T35	8		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T39	1		T17	1		T249	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18164	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	13		T200	1		T131	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T200	11		T14	10		T194	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	3		T13	15		T39	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T194	7		T146	4		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	10		T129	10		T106	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T25	21		T133	2		T100	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T210	16		T198	10		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T37	7		T214	24		T230	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T223	14		T165	11		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T25	20		T129	4		T149	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T133	13		T138	9		T14	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	6		T130	2		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	2		T138	13		T197	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T138	8		T151	11		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T1	3		T129	8		T106	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	5		T156	16		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	7		T204	14		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T29	3		T204	2		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	1		T136	2		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T200	9		T35	8		T284	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T17	1		T202	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T136	18		T223	8		T204	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T7	13		T200	7		T147	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T135	5		T200	1		T147	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T2	11		T39	1		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T223	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T39	1		T200	1		T99	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T43	14		T200	1		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	13		T13	1		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	3		T12	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T8	17		T10	13		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T25	1		T133	13		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	16		T132	10		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T50	12		T106	10		T32	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	2		T29	1		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T3	11		T24	3		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T133	13		T138	10		T14	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	8		T39	1		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T38	9		T138	15		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T109	4		T130	5		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	12		T109	16		T106	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	1		T134	9		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	1		T129	9		T204	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T29	10		T30	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	5		T11	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T200	9		T144	17		T283	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T145	10		T212	3		T17	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T223	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T39	17		T200	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T200	11		T14	10		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	13		T13	15		T130	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T194	7		T107	13		T231	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	3		T10	10		T133	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T25	21		T133	2		T100	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T132	8		T210	16		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T50	2		T106	12		T157	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T223	14		T198	10		T165	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T25	20		T37	7		T214	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	13		T138	9		T14	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T39	6		T129	4		T146	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T38	2		T138	13		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	2		T138	8		T197	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T1	3		T106	5		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T50	5		T156	16		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	7		T129	8		T204	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	3		T204	2		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T136	2		T15	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13