Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23549

1

T2

11

T3

11

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3891

1

T1

15

T4

6

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21372

1

T1

15

T4

12

T5

11

auto[1]

6068

1

T2

11

T3

11

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T12	3		T29	1		T129	29
values[0]	56	1			T227	7		T225	11		T176	18
values[1]	609	1			T25	22		T130	23		T200	12
values[2]	2998	1			T3	11		T4	2		T13	16
values[3]	781	1			T11	4		T109	9		T43	14
values[4]	499	1			T38	11		T109	16		T39	7
values[5]	961	1			T7	26		T10	23		T11	8
values[6]	727	1			T8	20		T29	13		T133	26
values[7]	901	1			T25	8		T39	19		T138	9
values[8]	548	1			T4	6		T129	13		T130	7
values[9]	1037	1			T1	15		T2	11		T38	12
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	705	1			T4	2		T25	22		T200	12
values[1]	3026	1			T3	11		T13	16		T24	3
values[2]	687	1			T11	4		T38	11		T109	9
values[3]	578	1			T11	8		T109	16		T39	7
values[4]	928	1			T7	26		T10	23		T109	4
values[5]	746	1			T8	20		T29	13		T129	17
values[6]	920	1			T25	8		T39	19		T138	9
values[7]	520	1			T4	6		T129	13		T130	7
values[8]	906	1			T1	15		T2	11		T12	3
values[9]	169	1			T129	29		T50	14		T32	19
minimum	18255	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	2		T200	12		T14	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T25	22		T131	1		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T3	2		T24	3		T25	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	16		T138	14		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T38	3		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	1		T43	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T109	1		T39	7		T50	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T36	2		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	14		T133	14		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	11		T109	1		T133	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T148	1		T139	9		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	9		T29	8		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T25	8		T39	18		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T39	1		T138	9		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	5		T130	3		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	3		T132	9		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T12	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	4		T30	1		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T129	11		T50	3		T156	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T32	8		T228	3		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17991	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T130	13		T223	9		T161	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	10		T32	14		T232	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T32	1		T15	2		T260	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T3	9		T26	15		T137	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	14		T33	4		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T38	8		T109	8		T106	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	2		T43	13		T198	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T109	15		T50	5		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	7		T36	1		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	12		T133	13		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	12		T109	3		T133	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T148	4		T139	9		T142	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	11		T29	5		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T135	15		T194	7		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T135	2		T14	8		T106	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T129	8		T130	4		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	3		T132	9		T32	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	10		T12	2		T38	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	11		T138	9		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T129	18		T50	11		T156	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T32	11		T228	1		T249	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T130	10		T161	12		T225	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T12	1		T29	1		T129	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T194	13		T159	1		T218	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T227	3		T176	16		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	1		T182	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T200	12		T131	1		T31	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T25	22		T130	13		T223	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T3	2		T4	2		T24	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	16		T138	14		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	1		T109	1		T136	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	1		T43	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T38	3		T109	1		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T146	14		T36	2		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	14		T133	14		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	11		T11	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T194	8		T148	1		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	9		T29	8		T133	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T25	8		T39	18		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T39	1		T138	9		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T129	5		T130	3		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	3		T132	9		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	1		T38	1		T210	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	4		T30	1		T138	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T12	2		T129	18		T30	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T194	10		T218	6		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T227	4		T176	2		T298	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	10		T182	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T31	5		T100	10		T32	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T130	10		T15	2		T161	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T3	9		T26	15		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	14		T32	1		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T109	8		T106	9		T32	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	2		T43	13		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	8		T109	15		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T36	1		T160	2		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	12		T133	13		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	12		T11	7		T109	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T194	7		T148	4		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	11		T29	5		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T135	15		T132	10		T204	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T135	2		T14	8		T106	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T129	8		T130	4		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T4	3		T132	9		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	10		T38	11		T198	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T1	11		T138	9		T197	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	2		T200	1		T14	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	1		T131	1		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T3	11		T24	3		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T138	15		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T38	9		T109	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	3		T43	14		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T109	16		T39	1		T50	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	8		T36	3		T160	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	13		T133	14		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T10	13		T109	4		T133	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T148	5		T139	10		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T8	17		T29	10		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	1		T39	1		T135	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	1		T138	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T129	9		T130	5		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	5		T132	10		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	11		T12	3		T38	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	12		T30	1		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T129	19		T50	12		T156	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T32	13		T228	4		T249	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18148	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T130	11		T223	1		T161	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T200	11		T14	10		T32	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T25	21		T15	7		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T25	20		T37	7		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	15		T138	13		T200	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T38	2		T136	2		T106	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T198	10		T213	9		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	6		T50	5		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	1		T96	20		T243	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	13		T133	13		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	10		T133	15		T200	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T139	8		T142	14		T224	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	3		T29	3		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T25	7		T39	17		T194	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T138	8		T14	10		T106	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T129	4		T130	2		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	1		T132	8		T147	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T210	16		T204	10		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	3		T138	9		T197	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T129	10		T50	2		T156	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T32	6		T245	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T100	3		T161	8		T227	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T130	12		T223	8		T161	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T12	3		T29	1		T129	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T194	11		T159	1		T218	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T227	5		T176	3		T298	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T225	11		T182	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T200	1		T131	1		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T25	1		T130	11		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T3	11		T4	2		T24	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T138	15		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T109	9		T136	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	3		T43	14		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	9		T109	16		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T146	1		T36	3		T160	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T7	13		T133	14		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T10	13		T11	8		T109	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T194	8		T148	5		T139	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	17		T29	10		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	1		T39	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T39	1		T138	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	9		T130	5		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	5		T132	10		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T2	11		T38	12		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T1	12		T30	1		T138	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T129	10		T50	2		T156	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T194	12		T218	2		T143	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T227	2		T176	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T200	11		T100	3		T32	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	21		T130	12		T223	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T25	20		T37	7		T14	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	15		T138	13		T200	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T136	20		T106	9		T149	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T198	10		T213	9		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T38	2		T39	6		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	13		T143	15		T17	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	13		T133	13		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	10		T133	2		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T194	7		T139	8		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	3		T29	3		T133	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	7		T39	17		T210	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T138	8		T14	10		T106	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T129	4		T130	2		T204	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	1		T132	8		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T210	16		T198	2		T204	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	3		T138	9		T197	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13