Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21813

1

T1

15

T4

16

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

5627

1

T2

11

T3

11

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21277

1

T1

15

T4

12

T5

11

auto[1]

6163

1

T2

11

T3

11

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	287	1			T159	1		T141	1		T17	2
values[0]	20	1			T1	15		T132	1		T225	3
values[1]	504	1			T25	22		T130	7		T200	12
values[2]	610	1			T11	4		T38	12		T130	23
values[3]	943	1			T2	11		T13	16		T109	9
values[4]	891	1			T7	26		T8	20		T133	27
values[5]	682	1			T25	8		T38	11		T109	4
values[6]	701	1			T4	6		T12	3		T30	1
values[7]	847	1			T39	25		T133	26		T129	46
values[8]	679	1			T10	23		T25	21		T29	1
values[9]	3180	1			T3	11		T4	2		T11	8
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	442	1			T130	23		T50	11		T194	15
values[1]	2962	1			T3	11		T11	4		T24	3
values[2]	945	1			T2	11		T13	16		T39	1
values[3]	814	1			T7	26		T8	20		T133	27
values[4]	690	1			T25	8		T38	11		T109	4
values[5]	674	1			T4	6		T12	3		T129	29
values[6]	855	1			T39	25		T133	26		T129	17
values[7]	648	1			T10	23		T25	21		T43	14
values[8]	935	1			T4	2		T11	8		T109	16
values[9]	121	1			T158	24		T159	1		T17	2
minimum	18354	1			T1	15		T4	10		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T132	1		T223	15		T215	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	13		T50	6		T194	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	2		T109	1		T29	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1586	1			T3	2		T24	3		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	16		T39	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	1		T129	5		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T134	1		T194	13		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	14		T8	9		T133	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T38	3		T138	10		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T25	8		T109	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	3		T12	1		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T99	1		T132	9		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T133	14		T129	9		T200	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T39	25		T32	2		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	11		T43	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T25	21		T29	1		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T109	1		T155	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	2		T11	1		T223	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T17	2		T226	1		T289	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T158	12		T159	1		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18035	1			T1	4		T4	10		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T200	12		T213	10		T224	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T215	4		T147	8		T218	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T130	10		T50	5		T194	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T109	8		T29	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1044	1			T3	9		T26	15		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T133	12		T30	1		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	10		T129	8		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T134	8		T194	10		T132	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	12		T8	11		T133	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	8		T138	9		T197	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T109	3		T135	4		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	3		T12	2		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T132	9		T148	4		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T133	12		T129	8		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	1		T201	7		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	12		T43	13		T135	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T16	3		T212	10		T199	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T109	15		T135	15		T194	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	7		T219	12		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T226	10		T289	1		T299	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T158	12		T208	2		T195	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	11		T8	1		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T213	11		T228	1		T300	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T141	1		T17	2		T208	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T159	1		T208	1		T222	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T1	4		T132	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	1		T169	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	22		T130	3		T136	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T200	12		T50	6		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	2		T138	9		T197	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T38	1		T130	13		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T13	16		T109	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T2	1		T129	5		T198	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T194	13		T204	15		T157	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	14		T8	9		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T38	3		T138	10		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T25	8		T109	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	3		T12	1		T197	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	1		T99	1		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T133	14		T129	20		T200	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	25		T32	2		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	11		T135	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	21		T29	1		T154	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T109	1		T43	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1585	1			T3	2		T4	2		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T208	11		T298	12		T289	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T208	2		T301	12		T302	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T1	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T130	4		T205	1		T215	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T50	5		T213	11		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	2		T197	5		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	11		T130	10		T194	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T109	8		T29	5		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	10		T129	8		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T194	10		T204	13		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	12		T8	11		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	8		T138	9		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T109	3		T135	4		T14	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	3		T12	2		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T132	9		T148	4		T139	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T133	12		T129	26		T14	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	1		T201	7		T150	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	12		T135	2		T100	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	1		T160	7		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T109	15		T43	13		T135	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1046	1			T3	9		T11	7		T26	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T132	1		T223	1		T215	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T130	11		T50	6		T194	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	4		T109	9		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1393	1			T3	11		T24	3		T26	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T39	1		T133	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	11		T129	9		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T134	9		T194	11		T132	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	13		T8	17		T133	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T38	9		T138	10		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T25	1		T109	4		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	5		T12	3		T129	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T99	1		T132	10		T148	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T133	13		T129	9		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	2		T32	3		T201	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	13		T43	14		T135	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	1		T29	1		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T109	16		T155	1		T135	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	2		T11	8		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T17	1		T226	11		T289	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T158	13		T159	1		T208	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T1	12		T4	10		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T200	1		T213	12		T224	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T223	14		T215	3		T231	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T130	12		T50	5		T194	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	3		T138	8		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1237	1			T37	7		T214	24		T230	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	15		T133	2		T50	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T129	4		T138	13		T149	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T194	12		T161	2		T162	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	13		T8	3		T133	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	2		T138	9		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T25	7		T215	11		T146	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	1		T129	10		T218	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	8		T139	2		T165	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T133	13		T129	8		T200	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	23		T231	8		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	10		T106	12		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T25	20		T16	2		T224	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T194	13		T149	11		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T223	8		T219	12		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T17	1		T289	1		T303	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T158	11		T222	12		T302	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T1	3		T25	21		T130	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T200	11		T213	9		T224	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T141	1		T17	1		T208	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T159	1		T208	3		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T1	12		T132	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T225	3		T169	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T25	1		T130	5		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T200	1		T50	6		T213	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	4		T138	1		T197	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	12		T130	11		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T109	9		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	11		T129	9		T198	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T194	11		T204	14		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	13		T8	17		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T38	9		T138	10		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	1		T109	4		T135	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	5		T12	3		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T30	1		T99	1		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T133	13		T129	28		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	2		T32	3		T201	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T10	13		T135	3		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	1		T29	1		T154	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T109	16		T43	14		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1395	1			T3	11		T4	2		T11	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T17	1		T298	1		T289	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T222	12		T233	14		T301	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T1	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T25	21		T130	2		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T200	11		T50	5		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	8		T197	4		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T130	12		T194	7		T107	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	15		T29	3		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T129	4		T198	10		T149	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T194	12		T204	14		T157	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	13		T8	3		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	2		T138	9		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T25	7		T14	10		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T197	15		T204	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	8		T139	2		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T133	13		T129	18		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	23		T150	2		T231	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	10		T100	3		T106	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T25	20		T36	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T194	13		T149	11		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1236	1			T37	7		T214	24		T230	42

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13