Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23838

1

T3

11

T4

18

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3602

1

T1

15

T2

11

T7

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

15

T2

11

T4

10

auto[1]

5905

1

T3

11

T4

8

T11

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	411	1			T39	7		T197	36		T106	11
values[0]	86	1			T109	16		T278	18		T268	37
values[1]	793	1			T4	6		T8	20		T11	3
values[2]	610	1			T129	17		T30	1		T107	14
values[3]	583	1			T10	23		T134	9		T200	10
values[4]	739	1			T1	15		T2	11		T29	14
values[5]	716	1			T4	2		T12	3		T38	11
values[6]	770	1			T25	43		T38	12		T109	9
values[7]	625	1			T11	8		T50	11		T223	15
values[8]	667	1			T11	1		T13	16		T30	2
values[9]	3344	1			T3	11		T7	26		T24	3
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	721	1			T4	6		T8	20		T133	27
values[1]	704	1			T10	23		T129	17		T30	1
values[2]	541	1			T29	13		T134	9		T200	20
values[3]	763	1			T1	15		T2	11		T38	11
values[4]	696	1			T4	2		T12	3		T109	9
values[5]	633	1			T25	43		T38	12		T133	15
values[6]	3095	1			T3	11		T11	9		T13	16
values[7]	583	1			T43	14		T133	26		T155	1
values[8]	1041	1			T7	26		T109	4		T39	7
values[9]	256	1			T197	10		T158	24		T142	11
minimum	18407	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	3		T8	9		T130	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T133	14		T14	12		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T100	4		T213	10		T215	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	11		T129	9		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T200	20		T198	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	8		T134	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T38	3		T39	18		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	4		T2	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	2		T12	1		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T109	1		T39	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	43		T38	1		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T129	5		T130	13		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T3	2		T11	1		T13	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T30	1		T194	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T133	14		T155	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	1		T135	1		T32	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T39	7		T135	1		T14	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	14		T109	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T197	5		T276	11		T242	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T158	13		T142	1		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18071	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T109	1		T215	4		T158	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	3		T8	11		T130	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T133	13		T14	8		T194	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T100	10		T213	11		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	12		T129	8		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T198	6		T80	17		T249	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T29	5		T134	8		T99	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T38	8		T132	9		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T1	11		T2	10		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T129	18		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	8		T132	10		T201	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T38	11		T133	12		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T129	8		T130	10		T106	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T3	9		T26	15		T137	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	7		T30	1		T194	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T133	12		T147	7		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	13		T135	15		T32	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T135	4		T14	10		T106	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	12		T109	3		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T197	5		T242	8		T304	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T158	11		T142	10		T208	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	1		T11	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T109	15		T215	4		T158	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	7		T197	5		T106	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T197	16		T147	5		T128	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T268	17		T220	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T109	1		T278	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	3		T8	9		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T133	14		T14	12		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T213	10		T139	3		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T129	9		T30	1		T107	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T100	4		T198	3		T215	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	11		T134	1		T200	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T154	1		T200	20		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	4		T2	1		T29	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	2		T12	1		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	1		T165	12		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	43		T38	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T109	1		T129	5		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T50	6		T223	15		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	1		T145	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T13	16		T215	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T30	1		T135	1		T194	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T3	2		T24	3		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T7	14		T109	1		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T197	5		T106	5		T198	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T197	10		T128	3		T229	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T268	20		T220	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T109	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	3		T8	11		T11	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	13		T14	8		T194	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T213	11		T139	2		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T129	8		T205	1		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T100	10		T198	6		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	12		T134	8		T194	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T132	9		T145	10		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	11		T2	10		T29	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	2		T38	8		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T201	7		T36	1		T142	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	11		T133	12		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T109	8		T129	8		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	5		T32	2		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	7		T147	12		T226	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T215	13		T147	7		T219	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	1		T135	15		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T3	9		T26	15		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	12		T109	3		T43	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	5		T8	17		T130	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T133	14		T14	10		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T100	11		T213	12		T215	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	13		T129	9		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T200	2		T198	7		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	10		T134	9		T99	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T38	9		T39	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	12		T2	11		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	2		T12	3		T129	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T109	9		T39	1		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T25	2		T38	12		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T129	9		T130	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T3	11		T11	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	8		T30	2		T194	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	13		T155	1		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T43	14		T135	16		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T39	1		T135	5		T14	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T7	13		T109	4		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T197	6		T276	1		T242	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T158	12		T142	11		T208	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18195	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T109	16		T215	5		T158	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	1		T8	3		T130	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T133	13		T14	10		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T100	3		T213	9		T215	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	10		T129	8		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T200	18		T198	2		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	3		T106	12		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T38	2		T39	17		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	3		T138	9		T149	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	10		T261	14		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T210	16		T151	11		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	41		T133	2		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	4		T130	12		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T13	15		T37	7		T214	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T194	12		T204	10		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	13		T227	2		T211	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	6		T212	3		T199	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T39	6		T14	10		T106	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	13		T197	15		T50	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T197	4		T276	10		T94	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T158	12		T91	9		T211	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T25	7		T265	7		T247	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T215	3		T158	11		T217	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T39	1		T197	6		T106	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T197	11		T147	3		T128	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T268	21		T220	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T109	16		T278	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	5		T8	17		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T133	14		T14	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T213	12		T139	3		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T129	9		T30	1		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T100	11		T198	7		T215	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	13		T134	9		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T154	1		T200	2		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	12		T2	11		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	2		T12	3		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	1		T165	1		T201	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T25	2		T38	12		T133	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T109	9		T129	9		T130	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	6		T223	1		T32	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	8		T145	1		T147	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T13	1		T215	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	2		T135	16		T194	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T3	11		T24	3		T26	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T7	13		T109	4		T43	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	6		T197	4		T106	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T197	15		T147	2		T91	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T268	16		T220	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T278	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T8	3		T25	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T133	13		T14	10		T194	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T213	9		T139	2		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T129	8		T107	13		T223	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T100	3		T198	2		T215	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	10		T200	9		T194	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T200	18		T136	2		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	3		T29	3		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T38	2		T39	17		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T165	11		T151	11		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	41		T133	2		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	4		T130	12		T138	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	5		T223	14		T161	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T224	12		T222	13		T221	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	15		T215	17		T186	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T194	12		T204	10		T212	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T37	7		T133	13		T14	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	13		T50	2		T32	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13