Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	12		T25	1		T130	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T130	11		T200	1		T50	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	4		T109	9		T29	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1397	1			T3	11		T24	3		T26	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	1		T39	1		T133	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	11		T129	9		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T134	9		T136	1		T194	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	13		T8	17		T133	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	9		T138	10		T197	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T25	1		T109	4		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	5		T12	3		T129	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T99	1		T132	10		T139	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T133	13		T129	9		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	2		T32	3		T201	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	13		T135	3		T106	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T25	1		T29	1		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T109	16		T43	14		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	8		T223	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T194	22		T17	1		T226	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T4	2		T158	13		T208	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	3		T25	21		T130	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T130	12		T200	11		T50	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	3		T138	8		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1240	1			T37	7		T214	24		T230	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	15		T133	2		T50	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T129	4		T138	13		T198	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	2		T194	12		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	13		T8	3		T133	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	2		T138	9		T197	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T25	7		T215	11		T146	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	1		T129	10		T215	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	8		T139	2		T165	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T133	13		T129	8		T200	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	23		T231	8		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	10		T106	12		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T25	20		T35	8		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T149	11		T232	8		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T223	8		T219	12		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T194	13		T17	1		T144	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T158	11		T222	12		T233	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T224	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T141	1		T174	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T132	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T224	1		T225	3		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	12		T25	1		T130	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T200	1		T50	6		T213	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T138	1		T197	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T38	12		T130	11		T194	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	1		T109	9		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T129	9		T210	1		T198	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	1		T131	1		T50	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T2	11		T7	13		T8	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T38	9		T138	10		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	1		T109	4		T135	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	5		T12	3		T14	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	1		T99	1		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T133	13		T129	28		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T39	2		T32	3		T201	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T10	13		T100	11		T106	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T25	1		T29	1		T154	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T109	16		T43	14		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1468	1			T3	11		T4	2		T11	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T174	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T224	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	3		T25	21		T130	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T200	11		T50	5		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T138	8		T197	4		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	12		T194	7		T107	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	3		T133	2		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T129	4		T210	16		T198	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	15		T50	2		T194	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	13		T8	3		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	2		T138	9		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T25	7		T14	10		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	1		T14	10		T197	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	8		T139	2		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T133	13		T129	18		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	23		T150	2		T231	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	10		T100	3		T106	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T25	20		T35	8		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T194	13		T149	11		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1337	1			T37	7		T214	24		T230	42

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13