Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23648

1

T1

15

T2

11

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3792

1

T4

6

T7

26

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21227

1

T2

11

T4

12

T5

11

auto[1]

6213

1

T1

15

T3

11

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	698	1			T38	12		T40	5		T39	7
values[0]	1	1			T240	1		-	-		-	-
values[1]	622	1			T200	10		T106	11		T32	7
values[2]	2950	1			T3	11		T8	20		T11	8
values[3]	897	1			T2	11		T13	16		T109	16
values[4]	691	1			T7	26		T12	3		T133	27
values[5]	804	1			T43	14		T129	29		T30	1
values[6]	669	1			T4	2		T25	22		T109	9
values[7]	731	1			T10	23		T25	21		T200	12
values[8]	661	1			T4	6		T11	3		T38	11
values[9]	1069	1			T1	15		T11	1		T25	8
minimum	17647	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	667	1			T8	20		T200	10		T106	11
values[1]	3037	1			T3	11		T11	8		T13	16
values[2]	808	1			T2	11		T109	16		T39	1
values[3]	764	1			T7	26		T12	3		T133	27
values[4]	760	1			T43	14		T133	41		T129	29
values[5]	641	1			T4	2		T25	22		T109	9
values[6]	655	1			T4	6		T10	23		T11	3
values[7]	649	1			T11	1		T38	11		T109	4
values[8]	1060	1			T1	15		T25	8		T38	12
values[9]	130	1			T39	7		T241	3		T147	5
minimum	18269	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T106	6		T32	9		T149	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	9		T200	10		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T3	2		T24	3		T26	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	1		T13	16		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T39	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T109	1		T129	5		T194	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T133	14		T135	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	14		T12	1		T200	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T43	1		T133	3		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T133	14		T14	11		T197	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	2		T200	12		T210	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	22		T109	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	11		T131	1		T132	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	3		T11	1		T25	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T38	3		T109	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	1		T30	1		T210	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	4		T38	1		T39	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T25	8		T129	9		T130	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T39	7		T241	3		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T141	1		T212	1		T18	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18002	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T161	3		T17	2		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T106	5		T32	15		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	11		T32	9		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T3	9		T26	15		T137	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	7		T31	5		T106	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	10		T134	8		T50	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T109	15		T129	8		T194	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T133	13		T135	15		T50	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	12		T12	2		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T43	13		T133	12		T129	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T133	12		T14	10		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T148	4		T147	5		T199	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T109	8		T138	14		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	12		T132	9		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	3		T11	2		T198	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	8		T109	3		T194	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T30	1		T142	15		T176	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	11		T38	11		T29	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T129	8		T130	4		T204	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T147	2		T243	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T212	12		T18	3		T206	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T161	5		T17	1		T242	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	513	1			T38	1		T40	5		T39	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T204	3		T151	12		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T240	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T106	6		T32	4		T149	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T200	10		T33	1		T161	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T3	2		T24	3		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	9		T11	1		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T39	1		T138	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	16		T109	1		T129	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T133	14		T135	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	14		T12	1		T200	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T43	1		T129	11		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	11		T197	16		T32	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	2		T133	3		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T25	22		T109	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	11		T200	12		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T25	21		T198	3		T213	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T38	3		T109	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	3		T11	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	4		T39	18		T138	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T11	1		T25	8		T129	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17505	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T38	11		T29	5		T14	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T204	3		T18	3		T244	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T106	5		T32	3		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	2		T161	5		T162	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T3	9		T26	15		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	11		T11	7		T31	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	10		T138	9		T134	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T109	15		T129	8		T194	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	13		T135	15		T50	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	12		T12	2		T204	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	13		T129	18		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	10		T197	10		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T133	12		T135	4		T194	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T109	8		T133	12		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	12		T132	9		T201	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T198	6		T213	11		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T38	8		T109	3		T198	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T4	3		T11	2		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	11		T135	2		T194	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T129	8		T130	4		T139	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T106	6		T32	19		T149	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	17		T200	1		T32	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T3	11		T24	3		T26	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	8		T13	1		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	11		T39	1		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T109	16		T129	9		T194	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T133	14		T135	16		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	13		T12	3		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T43	14		T133	13		T129	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T133	13		T14	11		T197	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	2		T200	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	1		T109	9		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	13		T131	1		T132	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	5		T11	3		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T38	9		T109	4		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T30	2		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	12		T38	12		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T25	1		T129	9		T130	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T39	1		T241	1		T147	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T141	1		T212	13		T18	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18153	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T161	6		T17	2		T242	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T106	5		T32	5		T149	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T8	3		T200	9		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T37	7		T130	12		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	15		T106	12		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	5		T100	3		T35	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T129	4		T194	13		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T133	13		T50	2		T157	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	13		T200	7		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T133	2		T129	10		T194	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	13		T14	10		T197	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T200	11		T210	10		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T25	21		T138	13		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	10		T132	8		T198	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	1		T25	20		T136	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	2		T194	7		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T210	16		T151	9		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	3		T39	17		T29	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T25	7		T129	8		T130	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T39	6		T241	2		T243	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T18	2		T206	11		T245	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T246	2		T167	12		T247	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T161	2		T17	1		T221	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	535	1			T38	12		T40	5		T39	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T204	4		T151	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T240	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T106	6		T32	7		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T200	1		T33	3		T161	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T3	11		T24	3		T26	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	17		T11	8		T31	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T2	11		T39	1		T138	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T109	16		T129	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T133	14		T135	16		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	13		T12	3		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	14		T129	19		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	11		T197	11		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	2		T133	13		T135	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T25	1		T109	9		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	13		T200	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	1		T198	7		T213	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	9		T109	4		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	5		T11	3		T30	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	12		T39	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T11	1		T25	1		T129	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17647	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T39	6		T29	3		T14	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T204	2		T151	11		T18	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T106	5		T149	3		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T200	9		T161	2		T162	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T37	7		T130	12		T197	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	3		T146	23		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	9		T136	2		T100	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	15		T129	4		T194	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	13		T50	7		T157	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	13		T200	7		T204	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T129	10		T149	11		T215	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	10		T197	15		T32	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T133	2		T194	12		T156	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T25	21		T133	13		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	10		T200	11		T132	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T25	20		T198	2		T213	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	2		T198	10		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T136	18		T210	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	3		T39	17		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T25	7		T129	8		T130	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13