Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23815

1

T1

15

T3

11

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3625

1

T2

11

T8

20

T11

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21136

1

T2

11

T4

18

T5

11

auto[1]

6304

1

T1

15

T3

11

T10

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	244	1			T140	1		T141	1		T161	18
values[0]	27	1			T226	6		T85	16		T248	5
values[1]	693	1			T4	2		T135	21		T197	26
values[2]	606	1			T25	43		T29	1		T130	23
values[3]	700	1			T2	11		T11	4		T109	4
values[4]	702	1			T10	23		T13	16		T129	29
values[5]	909	1			T25	8		T38	12		T43	14
values[6]	932	1			T7	26		T11	8		T29	13
values[7]	480	1			T38	11		T39	1		T130	7
values[8]	3148	1			T3	11		T4	6		T8	20
values[9]	903	1			T1	15		T12	3		T109	16
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	684	1			T4	2		T130	23		T135	21
values[1]	575	1			T11	3		T25	43		T29	1
values[2]	822	1			T2	11		T10	23		T11	1
values[3]	696	1			T13	16		T43	14		T129	29
values[4]	897	1			T11	8		T25	8		T38	12
values[5]	833	1			T7	26		T38	11		T29	13
values[6]	2767	1			T3	11		T4	6		T24	3
values[7]	842	1			T8	20		T109	9		T39	7
values[8]	1017	1			T1	15		T12	3		T109	16
values[9]	24	1			T249	11		T250	8		T171	3
minimum	18283	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	2		T130	13		T135	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T197	16		T106	6		T213	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T25	22		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	21		T138	9		T200	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	11		T11	1		T133	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T109	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T129	11		T30	1		T198	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	16		T43	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T25	8		T129	5		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	1		T38	1		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	14		T29	8		T200	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	3		T133	14		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T3	2		T4	3		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T130	3		T14	11		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T109	1		T39	7		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	9		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T1	4		T12	1		T39	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T109	1		T149	4		T33	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T250	1		T171	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	1		T239	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18000	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T147	1		T15	11		T85	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T130	10		T135	19		T99	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T197	10		T106	5		T213	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	2		T215	4		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T132	10		T32	9		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	12		T133	12		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	10		T109	3		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	18		T30	1		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	13		T194	21		T147	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T129	8		T194	10		T205	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	7		T38	11		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	12		T29	5		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T38	8		T133	13		T138	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T3	9		T4	3		T26	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T130	4		T14	10		T32	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T109	8		T32	1		T201	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	11		T134	8		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	11		T12	2		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T109	15		T149	9		T33	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T250	7		T171	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T249	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T147	1		T15	2		T85	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T199	8		T195	1		T222	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T140	1		T141	1		T161	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T226	1		T85	14		T248	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	2		T135	2		T50	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T197	16		T106	6		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T25	22		T29	1		T130	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T25	21		T138	9		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	2		T133	14		T129	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T109	1		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	11		T129	11		T198	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	16		T194	14		T106	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T25	8		T30	1		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T38	1		T43	1		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	14		T29	8		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T133	14		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	1		T145	1		T204	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	3		T130	3		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T3	2		T4	3		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T8	9		T30	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	4		T12	1		T39	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T109	1		T149	4		T33	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T199	3		T195	4		T202	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T161	9		T219	17		T195	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T226	5		T85	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T135	19		T50	11		T100	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T197	10		T106	5		T213	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	10		T99	9		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T132	10		T148	6		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	2		T133	12		T129	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	10		T109	3		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	12		T129	18		T198	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T194	21		T106	9		T147	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	1		T194	10		T205	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	11		T43	13		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	12		T29	5		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	7		T133	13		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T204	10		T139	2		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	8		T130	4		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T3	9		T4	3		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	11		T134	8		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	11		T12	2		T194	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T109	15		T149	9		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[values[9]]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	2		T130	11		T135	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T197	11		T106	6		T213	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	3		T25	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T25	1		T138	1		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	13		T11	1		T133	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	11		T109	4		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T129	19		T30	2		T198	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	1		T43	14		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T25	1		T129	9		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	8		T38	12		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	13		T29	10		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T38	9		T133	14		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T3	11		T4	5		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T130	5		T14	11		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T109	9		T39	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	17		T30	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	12		T12	3		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T109	16		T149	10		T33	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T250	8		T171	3		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T249	11		T239	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18189	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T147	2		T15	6		T85	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T130	12		T100	3		T156	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T197	15		T106	5		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T25	21		T215	3		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T25	20		T138	8		T200	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	10		T133	13		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	2		T14	10		T106	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T129	10		T198	12		T146	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	15		T194	13		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T25	7		T129	4		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	9		T197	4		T158	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	13		T29	3		T200	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	2		T133	13		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T4	1		T37	7		T214	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T130	2		T14	10		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	6		T223	8		T218	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	3		T136	18		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	3		T39	17		T200	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T149	3		T33	2		T146	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T50	2		T227	3		T211	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T15	7		T85	12		T247	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T199	4		T195	5		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T140	1		T141	1		T161	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T226	6		T85	4		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	2		T135	21		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T197	11		T106	6		T213	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T25	1		T29	1		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T25	1		T138	1		T132	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	4		T133	13		T129	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	11		T109	4		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	13		T129	19		T198	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	1		T194	22		T106	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T25	1		T30	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T38	12		T43	14		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T7	13		T29	10		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	8		T133	14		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	1		T145	1		T204	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	9		T130	5		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T3	11		T4	5		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	17		T30	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	12		T12	3		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T109	16		T149	10		T33	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T199	7		T222	12		T202	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T161	8		T219	16		T209	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T85	12		T248	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T50	2		T100	3		T156	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T197	15		T106	5		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	21		T130	12		T215	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T25	20		T138	8		T157	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T133	13		T129	8		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T133	2		T200	11		T14	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	10		T129	10		T198	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	15		T194	13		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T25	7		T136	2		T194	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T138	9		T197	4		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	13		T29	3		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	13		T138	13		T107	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T204	10		T139	2		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T38	2		T130	2		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T4	1		T37	7		T214	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	3		T136	18		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	3		T39	23		T200	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T149	3		T33	2		T146	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13