Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23435

1

T1

15

T3

11

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

4005

1

T2

11

T4

2

T7

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20835

1

T2

11

T4

10

T5

11

auto[1]

6605

1

T1

15

T3

11

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	533	1			T38	12		T40	5		T39	18
values[0]	6	1			T32	3		T228	3		-	-
values[1]	619	1			T200	10		T106	11		T32	15
values[2]	2966	1			T3	11		T8	20		T11	8
values[3]	880	1			T2	11		T13	16		T109	16
values[4]	698	1			T7	26		T12	3		T133	27
values[5]	758	1			T43	14		T30	1		T154	1
values[6]	654	1			T4	2		T25	22		T109	9
values[7]	741	1			T4	6		T10	23		T25	21
values[8]	754	1			T11	3		T38	11		T109	4
values[9]	1184	1			T1	15		T11	1		T25	8
minimum	17647	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	804	1			T8	20		T200	10		T106	11
values[1]	3012	1			T3	11		T11	8		T13	16
values[2]	833	1			T2	11		T109	16		T39	1
values[3]	739	1			T7	26		T12	3		T133	27
values[4]	784	1			T4	2		T43	14		T133	41
values[5]	608	1			T25	22		T109	9		T29	1
values[6]	726	1			T4	6		T10	23		T11	3
values[7]	692	1			T11	1		T38	11		T109	4
values[8]	915	1			T1	15		T25	8		T38	12
values[9]	217	1			T39	7		T132	1		T241	3
minimum	18110	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T106	6		T32	11		T149	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	9		T200	10		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T3	2		T24	3		T26	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	1		T13	16		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	1		T100	4		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	1		T109	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T133	14		T200	8		T50	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	14		T12	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T133	3		T30	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	2		T43	1		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T200	12		T148	1		T147	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T25	22		T109	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	3		T136	19		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	11		T11	1		T25	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	1		T131	1		T201	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	1		T38	3		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	4		T38	1		T39	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T25	8		T129	9		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T39	7		T241	3		T243	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T132	1		T139	9		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17957	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T252	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T106	5		T32	24		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	11		T32	2		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T3	9		T26	15		T137	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	7		T31	5		T106	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T100	10		T35	5		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	10		T109	15		T129	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T133	13		T50	11		T132	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	12		T12	2		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	12		T135	19		T14	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	13		T133	12		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T148	4		T147	5		T199	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T109	8		T138	14		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	3		T132	9		T201	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	12		T11	2		T198	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	1		T201	8		T15	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	8		T109	3		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	11		T38	11		T29	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T129	8		T147	2		T253	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T243	1		T249	6		T254	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T139	9		T212	12		T199	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	1		T43	1		T29	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T38	1		T40	5		T39	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T151	12		T225	1		T255	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T32	2		T228	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T106	6		T32	2		T149	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T200	10		T32	2		T161	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T3	2		T24	3		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	9		T11	1		T146	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	1		T138	10		T136	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	1		T13	16		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T133	14		T135	1		T200	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	14		T12	1		T50	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T30	1		T154	1		T14	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T43	1		T131	1		T197	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	3		T135	1		T194	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	2		T25	22		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	3		T200	12		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	11		T25	21		T210	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	1		T136	19		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	1		T38	3		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	4		T39	7		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T11	1		T25	8		T129	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17505	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T38	11		T237	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T225	10		T255	13		T256	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T32	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T106	5		T32	9		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T32	2		T161	5		T162	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T3	9		T26	15		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	11		T11	7		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T138	9		T99	9		T100	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	10		T109	15		T129	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	13		T135	15		T50	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	12		T12	2		T50	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	10		T232	10		T215	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	13		T197	10		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	12		T135	4		T194	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T109	8		T133	12		T129	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	3		T132	9		T201	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	12		T198	6		T213	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	1		T201	8		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	2		T38	8		T109	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	11		T29	5		T130	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T129	8		T194	7		T139	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T106	6		T32	30		T149	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T8	17		T200	1		T32	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T3	11		T24	3		T26	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	8		T13	1		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T39	1		T100	11		T35	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T2	11		T109	16		T129	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T133	14		T200	1		T50	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	13		T12	3		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T133	13		T30	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	2		T43	14		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T200	1		T148	5		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T25	1		T109	9		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	5		T136	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	13		T11	3		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	2		T131	1		T201	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T38	9		T109	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	12		T38	12		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T25	1		T129	9		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T39	1		T241	1		T243	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T132	1		T139	10		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18100	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T106	5		T32	5		T149	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	3		T200	9		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T37	7		T130	12		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	15		T106	12		T146	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T100	3		T35	8		T191	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T129	4		T50	5		T194	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T133	13		T200	7		T50	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	13		T204	10		T149	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T133	2		T14	10		T194	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T133	13		T129	10		T197	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T200	11		T147	3		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T25	21		T138	13		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	1		T136	18		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	10		T25	20		T198	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T147	2		T15	7		T218	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	2		T194	7		T210	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T39	17		T29	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T25	7		T129	8		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T39	6		T241	2		T243	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T139	8		T199	11		T206	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T17	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T252	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T38	12		T40	5		T39	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T151	1		T225	11		T255	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T32	3		T228	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T106	6		T32	11		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T200	1		T32	4		T161	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T3	11		T24	3		T26	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T8	17		T11	8		T146	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T39	1		T138	10		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T2	11		T13	1		T109	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T133	14		T135	16		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T12	3		T50	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	1		T154	1		T14	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T43	14		T131	1		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T133	13		T135	5		T194	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	2		T25	1		T109	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	5		T200	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	13		T25	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T30	2		T136	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	3		T38	9		T109	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	12		T39	1		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T11	1		T25	1		T129	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17647	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T39	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T151	11		T255	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T106	5		T149	3		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T200	9		T161	2		T162	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T37	7		T130	12		T197	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	3		T146	27		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T138	9		T136	2		T100	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	15		T129	4		T194	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	13		T200	7		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	13		T50	5		T204	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	10		T232	8		T215	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T197	15		T32	6		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T133	2		T194	12		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T25	21		T133	13		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	1		T200	11		T132	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	10		T25	20		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	18		T15	7		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	2		T210	16		T198	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	3		T39	6		T29	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T25	7		T129	8		T194	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13