Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23523

1

T2

11

T3

11

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

3917

1

T1

15

T4

6

T8

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21360

1

T1

15

T4

12

T5

11

auto[1]

6080

1

T2

11

T3

11

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T29	1		T238	1		-	-
values[0]	123	1			T131	1		T100	14		T161	25
values[1]	548	1			T25	22		T130	23		T200	12
values[2]	3005	1			T3	11		T4	2		T13	16
values[3]	678	1			T11	4		T109	9		T43	14
values[4]	603	1			T38	11		T109	16		T39	7
values[5]	907	1			T7	26		T10	23		T11	8
values[6]	817	1			T8	20		T29	13		T133	26
values[7]	867	1			T25	8		T39	19		T138	9
values[8]	556	1			T4	6		T129	13		T130	7
values[9]	1238	1			T1	15		T2	11		T12	3
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T4	2		T25	22		T130	23
values[1]	3038	1			T3	11		T13	16		T24	3
values[2]	610	1			T11	4		T38	11		T109	9
values[3]	663	1			T11	8		T109	16		T39	7
values[4]	807	1			T7	26		T10	23		T109	4
values[5]	800	1			T8	20		T29	13		T129	17
values[6]	958	1			T25	8		T39	19		T154	1
values[7]	531	1			T4	6		T129	13		T130	7
values[8]	796	1			T1	15		T2	11		T12	3
values[9]	237	1			T38	12		T129	29		T50	14
minimum	18118	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T4	2		T200	12		T14	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T25	22		T130	13		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T3	2		T24	3		T25	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	16		T138	14		T200	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	1		T38	3		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	1		T43	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T109	1		T39	7		T50	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	1		T36	2		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	14		T133	14		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	11		T109	1		T133	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T139	9		T218	10		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	9		T29	8		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T25	8		T39	18		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T39	1		T154	1		T14	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T129	5		T130	3		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	3		T132	9		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T12	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	4		T30	1		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T38	1		T129	11		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T132	1		T32	8		T228	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T225	1		T258	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	10		T31	5		T100	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T130	10		T32	1		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T3	9		T26	15		T137	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	14		T145	10		T33	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	8		T109	8		T32	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	2		T43	13		T198	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T109	15		T50	5		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	7		T36	1		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	12		T133	13		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	12		T109	3		T133	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T139	9		T142	15		T193	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	11		T29	5		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T135	15		T194	7		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	8		T106	9		T201	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T129	8		T130	4		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	3		T132	9		T32	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	10		T12	2		T30	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	11		T138	9		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T38	11		T129	18		T50	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T132	15		T32	11		T228	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T225	10		T258	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T29	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T131	1		T100	4		T227	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T161	13		T182	1		T259	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T200	12		T31	4		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	22		T130	13		T223	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T3	2		T4	2		T24	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	16		T138	14		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	1		T109	1		T136	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	1		T43	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	3		T109	1		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T213	10		T146	25		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	14		T133	14		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	11		T11	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T194	8		T148	1		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	9		T29	8		T133	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T25	8		T39	18		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T39	1		T138	9		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T129	5		T130	3		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	3		T132	9		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T2	1		T12	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	4		T30	1		T138	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T100	10		T227	4		T176	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T161	12		T182	5		T259	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T31	5		T32	14		T201	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T130	10		T15	2		T260	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T3	9		T26	15		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T138	14		T32	1		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T109	8		T32	2		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	2		T43	13		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	8		T109	15		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T213	11		T146	10		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	12		T133	13		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	12		T11	7		T109	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T194	7		T148	4		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	11		T29	5		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T135	15		T132	10		T204	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T135	2		T14	8		T106	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T129	8		T130	4		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T4	3		T132	9		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	10		T12	2		T38	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	11		T138	9		T197	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	2		T200	1		T14	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	1		T130	11		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T3	11		T24	3		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T138	15		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	1		T38	9		T109	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	3		T43	14		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T109	16		T39	1		T50	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	8		T36	3		T160	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	13		T133	14		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T10	13		T109	4		T133	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T139	10		T218	1		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T8	17		T29	10		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	1		T39	1		T135	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T39	1		T154	1		T14	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T129	9		T130	5		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	5		T132	10		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	11		T12	3		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	12		T30	1		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T38	12		T129	19		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T132	16		T32	13		T228	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T225	11		T258	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T200	11		T14	10		T100	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T25	21		T130	12		T223	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T25	20		T37	7		T136	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	15		T138	13		T200	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T38	2		T149	3		T261	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T198	10		T213	9		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	6		T50	5		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T262	4		T96	20		T243	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	13		T133	13		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	10		T133	15		T200	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T139	8		T218	9		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	3		T29	3		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T25	7		T39	17		T194	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	10		T106	12		T107	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	4		T130	2		T210	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	1		T132	8		T147	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T204	10		T257	11		T218	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	3		T138	9		T197	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T129	10		T50	2		T156	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T32	6		T245	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T258	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T29	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T131	1		T100	11		T227	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T161	13		T182	6		T259	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T200	1		T31	9		T32	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T25	1		T130	11		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T3	11		T4	2		T24	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	1		T138	15		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T109	9		T136	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	3		T43	14		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	9		T109	16		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T213	12		T146	12		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	13		T133	14		T149	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T10	13		T11	8		T109	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T194	8		T148	5		T139	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T8	17		T29	10		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T25	1		T39	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T39	1		T138	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T129	9		T130	5		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	5		T132	10		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T2	11		T12	3		T38	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T1	12		T30	1		T138	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T100	3		T227	2		T176	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T161	12		T259	21		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T200	11		T32	5		T161	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	21		T130	12		T223	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T25	20		T37	7		T14	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	15		T138	13		T200	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T136	20		T149	3		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T198	10		T145	10		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T38	2		T39	6		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T213	9		T146	23		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	13		T133	13		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	10		T133	2		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T194	7		T139	8		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	3		T29	3		T133	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	7		T39	17		T210	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T138	8		T14	10		T106	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T129	4		T130	2		T204	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	1		T132	8		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T129	10		T50	2		T210	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	3		T138	9		T197	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13