Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23848

1

T2

11

T3

11

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3592

1

T1

15

T7

26

T12

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21286

1

T2

11

T4

10

T5

11

auto[1]

6154

1

T1

15

T3

11

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T154	1		T132	11		T210	11
values[0]	2	1			T235	1		T238	1		-	-
values[1]	747	1			T8	20		T136	3		T194	58
values[2]	659	1			T7	26		T38	12		T29	1
values[3]	796	1			T13	16		T38	11		T43	14
values[4]	2985	1			T3	11		T4	2		T24	3
values[5]	735	1			T4	6		T12	3		T25	22
values[6]	650	1			T11	8		T25	21		T50	14
values[7]	687	1			T1	15		T129	13		T130	23
values[8]	875	1			T2	11		T11	3		T39	7
values[9]	977	1			T10	23		T11	1		T25	8
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	765	1			T8	20		T38	12		T29	1
values[1]	650	1			T7	26		T13	16		T38	11
values[2]	744	1			T43	14		T133	15		T30	3
values[3]	3024	1			T3	11		T4	2		T24	3
values[4]	728	1			T4	6		T12	3		T25	22
values[5]	701	1			T1	15		T11	8		T25	21
values[6]	599	1			T2	11		T129	13		T130	23
values[7]	894	1			T11	4		T39	7		T129	46
values[8]	923	1			T25	8		T133	53		T138	19
values[9]	134	1			T10	23		T135	3		T194	15
minimum	18278	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	9		T29	1		T136	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T38	1		T194	13		T106	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T155	1		T132	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	14		T13	16		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T133	3		T30	2		T107	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T43	1		T136	19		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T3	2		T4	2		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T130	3		T134	1		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	3		T39	18		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T25	22		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	1		T25	21		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	4		T213	10		T215	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	1		T129	5		T200	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T130	13		T138	9		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	2		T129	20		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T39	7		T14	11		T197	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T25	8		T138	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T133	28		T106	10		T210	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T10	11		T194	8		T204	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T135	1		T142	15		T263	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18001	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T146	5		T264	12		T265	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	11		T194	21		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	11		T194	10		T106	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T132	15		T148	4		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	12		T38	8		T135	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	12		T30	1		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	13		T31	5		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T3	9		T26	15		T137	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	4		T134	8		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	3		T50	11		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	2		T109	18		T29	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	7		T138	14		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	11		T213	11		T215	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	10		T129	8		T212	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T130	10		T135	4		T14	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	2		T129	26		T99	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	10		T197	5		T106	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T138	9		T50	5		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T133	25		T106	9		T198	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T10	12		T194	7		T204	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T135	2		T142	15		T263	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T146	2		T264	6		T266	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T154	1		T132	1		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T210	11		T151	10		T199	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	9		T136	3		T194	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T194	13		T204	11		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T29	1		T155	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	14		T38	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T133	3		T30	1		T107	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	16		T38	3		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T3	2		T4	2		T24	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T130	3		T136	19		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	3		T109	1		T39	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	1		T25	22		T109	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T25	21		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T99	1		T213	10		T215	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T129	5		T138	14		T200	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	4		T130	13		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T11	1		T129	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T39	7		T138	9		T106	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	11		T11	1		T25	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T133	28		T135	1		T14	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T132	10		T147	1		T267	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T199	10		T164	1		T263	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	11		T194	21		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T194	10		T204	10		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T132	15		T148	4		T33	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	12		T38	11		T135	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T133	12		T30	1		T149	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T38	8		T43	13		T162	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T3	9		T26	15		T137	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T130	4		T31	5		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	3		T109	8		T160	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	2		T109	18		T29	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	7		T50	11		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T213	11		T215	13		T15	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T129	8		T138	14		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	11		T130	10		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	10		T11	2		T129	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T106	9		T32	11		T35	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	12		T138	9		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	25		T135	2		T14	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	17		T29	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	12		T194	11		T106	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T155	1		T132	16		T148	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	13		T13	1		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	13		T30	3		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T43	14		T136	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T3	11		T4	2		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T130	5		T134	9		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	5		T39	1		T50	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	3		T25	1		T109	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	8		T25	1		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	12		T213	12		T215	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	11		T129	9		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T130	11		T138	1		T135	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T11	4		T129	28		T99	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T39	1		T14	11		T197	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T25	1		T138	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	27		T106	10		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T10	13		T194	8		T204	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T135	3		T142	16		T263	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18168	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T146	3		T264	7		T265	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	3		T136	2		T194	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T194	12		T106	5		T204	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T149	3		T33	2		T215	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	13		T13	15		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T133	2		T107	13		T149	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T136	18		T157	13		T162	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T37	7		T200	18		T214	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T130	2		T145	10		T232	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	1		T39	17		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	21		T29	3		T27	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	20		T138	13		T132	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	3		T213	9		T215	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T129	4		T200	9		T165	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	12		T138	8		T14	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	18		T32	5		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	6		T14	10		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T25	7		T138	9		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T133	26		T106	9		T210	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T10	10		T194	7		T204	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T142	14		T263	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T168	3		T268	7		T269	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T146	4		T264	11		T266	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T154	1		T132	11		T147	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T210	1		T151	1		T199	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	17		T136	1		T194	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T194	11		T204	11		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T29	1		T155	1		T132	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	13		T38	12		T135	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T133	13		T30	2		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	1		T38	9		T43	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T3	11		T4	2		T24	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T130	5		T136	1		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	5		T109	9		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	3		T25	1		T109	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	8		T25	1		T50	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T99	1		T213	12		T215	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T129	9		T138	15		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	12		T130	11		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T2	11		T11	3		T129	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	1		T138	1		T106	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T10	13		T11	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T133	27		T135	3		T14	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T91	12		T267	1		T270	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T210	10		T151	9		T199	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	3		T136	2		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T194	12		T204	10		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T33	2		T215	11		T161	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	13		T106	5		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	2		T107	13		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	15		T38	2		T157	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T37	7		T200	18		T214	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T130	2		T136	18		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T39	17		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	21		T29	3		T158	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	20		T50	2		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T213	9		T215	17		T15	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T129	4		T138	13		T200	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	3		T130	12		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T129	18		T32	5		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	6		T138	8		T106	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	10		T25	7		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T133	26		T14	10		T106	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13