Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27440

1

T1

15

T2

11

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23857

1

T3

11

T4

18

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3583

1

T1

15

T2

11

T10

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21415

1

T1

15

T2

11

T4

10

auto[1]

6025

1

T3

11

T4

8

T11

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258

1

T1

4

T2

1

T3

2

auto[1]

4182

1

T1

11

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T271	1		T234	13		-	-
values[0]	165	1			T109	16		T34	7		T158	24
values[1]	661	1			T4	6		T8	20		T11	3
values[2]	671	1			T129	17		T30	1		T14	20
values[3]	620	1			T10	23		T29	14		T134	9
values[4]	700	1			T1	15		T2	11		T138	19
values[5]	752	1			T4	2		T12	3		T25	22
values[6]	689	1			T25	21		T38	12		T109	9
values[7]	624	1			T11	8		T50	11		T132	16
values[8]	690	1			T11	1		T13	16		T30	2
values[9]	3758	1			T3	11		T7	26		T24	3
minimum	18096	1			T4	10		T5	11		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1017	1			T4	6		T8	20		T109	16
values[1]	687	1			T10	23		T129	17		T30	1
values[2]	526	1			T29	13		T134	9		T200	20
values[3]	790	1			T1	15		T2	11		T38	11
values[4]	701	1			T12	3		T109	9		T39	1
values[5]	639	1			T4	2		T25	43		T38	12
values[6]	3028	1			T3	11		T11	1		T13	16
values[7]	659	1			T11	8		T43	14		T133	26
values[8]	887	1			T7	26		T109	4		T39	7
values[9]	386	1			T197	10		T201	7		T35	16
minimum	18120	1			T4	10		T5	11		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

4201

1

T1

3

T4

1

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T4	3		T8	9		T130	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T109	1		T133	14		T14	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T100	4		T213	10		T215	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	11		T129	9		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T200	20		T99	1		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	8		T134	1		T106	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T38	3		T39	18		T136	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	4		T2	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T129	11		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T109	1		T39	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	2		T25	21		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	22		T130	13		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T3	2		T11	1		T13	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	1		T194	13		T224	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T133	14		T147	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	1		T43	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T7	14		T39	7		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T109	1		T154	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T197	5		T229	1		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T201	1		T35	11		T158	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17963	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T11	1		T236	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	3		T8	11		T130	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T109	15		T133	13		T14	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T100	10		T213	11		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	12		T129	8		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T99	9		T32	1		T80	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T29	5		T134	8		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	8		T132	9		T204	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	11		T2	10		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	2		T129	18		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T109	8		T132	10		T148	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	11		T133	12		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T130	10		T106	9		T132	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T3	9		T26	15		T137	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T30	1		T194	10		T226	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	12		T147	7		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	7		T43	13		T135	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	12		T135	4		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T109	3		T197	10		T50	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T197	5		T229	2		T242	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T201	6		T35	5		T158	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T11	2		T236	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T271	1		T234	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T161	13		T273	1		T268	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T109	1		T34	5		T158	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	3		T8	9		T25	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T133	14		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T213	10		T156	17		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T129	9		T30	1		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T99	1		T100	4		T215	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	11		T29	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T200	20		T136	3		T132	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	4		T2	1		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	2		T12	1		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T25	22		T39	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	21		T38	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T109	1		T130	13		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T50	6		T223	15		T157	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	1		T132	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	1		T13	16		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	1		T135	1		T194	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1827	1			T3	2		T7	14		T24	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T109	1		T43	1		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T234	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T161	12		T268	20		T274	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T109	15		T34	2		T158	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	3		T8	11		T130	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	2		T133	13		T194	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T213	11		T156	1		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T129	8		T14	8		T205	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T99	9		T100	10		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	12		T29	5		T134	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T132	9		T32	1		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	11		T2	10		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	2		T38	8		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T148	4		T201	7		T142	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	11		T133	12		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T109	8		T130	10		T106	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	5		T16	1		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	7		T132	15		T147	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	2		T215	13		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	1		T135	15		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T3	9		T7	12		T26	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T109	3		T43	13		T197	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T43	1		T29	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	5		T8	17		T130	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T109	16		T133	14		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T100	11		T213	12		T215	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	13		T129	9		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T200	2		T99	10		T32	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	10		T134	9		T106	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T38	9		T39	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	12		T2	11		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	3		T129	19		T135	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T109	9		T39	1		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	2		T25	1		T38	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	1		T130	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T3	11		T11	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	2		T194	11		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T133	13		T147	8		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	8		T43	14		T135	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	13		T39	1		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T109	4		T154	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T197	6		T229	3		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T201	7		T35	8		T158	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T4	10		T5	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T11	3		T236	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	1		T8	3		T130	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T133	13		T14	10		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T100	3		T213	9		T215	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	10		T129	8		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T200	18		T143	15		T275	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T29	3		T106	12		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	2		T39	17		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	3		T138	9		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	10		T261	14		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T210	16		T151	11		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T25	20		T133	2		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	21		T130	12		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T13	15		T37	7		T214	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T194	12		T224	12		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T133	13		T212	3		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T204	10		T32	6		T199	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	13		T39	6		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T197	15		T50	2		T150	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T197	4		T276	10		T94	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T35	8		T158	12		T209	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T25	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T271	1		T234	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T161	13		T273	1		T268	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T109	16		T34	7		T158	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	5		T8	17		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	3		T133	14		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T213	12		T156	2		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T129	9		T30	1		T14	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T99	10		T100	11		T215	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	13		T29	11		T134	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T200	2		T136	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	12		T2	11		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	2		T12	3		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T25	1		T39	1		T148	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T25	1		T38	12		T133	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T109	9		T130	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	6		T223	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	8		T132	16		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	1		T13	1		T32	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	2		T135	16		T194	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T3	11		T7	13		T24	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	429	1			T109	4		T43	14		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18096	1			T4	10		T5	11		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T234	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T161	12		T268	16		T277	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T158	11		T278	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	1		T8	3		T25	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T133	13		T194	13		T215	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T213	9		T156	16		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T129	8		T14	10		T107	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T100	3		T215	11		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	10		T29	3		T200	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T200	18		T136	2		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	3		T138	9		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	2		T39	17		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	21		T165	11		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	20		T133	2		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T130	12		T138	8		T136	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T50	5		T223	14		T157	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T231	12		T224	12		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	15		T215	17		T212	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T194	12		T204	10		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T7	13		T37	7		T39	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T197	15		T50	2		T150	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23239

1

T1

12

T2

11

T3

11

auto[1]

auto[0]

4201

1

T1

3

T4

1

T7

13