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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 919
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T322 /workspace/coverage/default/2.adc_ctrl_fsm_reset.3521326773 Jul 17 05:31:42 PM PDT 24 Jul 17 05:43:55 PM PDT 24 136304238806 ps
T792 /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3293039471 Jul 17 05:33:50 PM PDT 24 Jul 17 05:35:46 PM PDT 24 166088460558 ps
T793 /workspace/coverage/default/22.adc_ctrl_stress_all.2187677231 Jul 17 05:34:52 PM PDT 24 Jul 17 05:35:36 PM PDT 24 43187581879 ps
T794 /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3335909813 Jul 17 05:32:56 PM PDT 24 Jul 17 05:34:37 PM PDT 24 165959026717 ps
T47 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1375099555 Jul 17 05:26:47 PM PDT 24 Jul 17 05:27:47 PM PDT 24 17317284370 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.834317867 Jul 17 05:26:44 PM PDT 24 Jul 17 05:26:46 PM PDT 24 400659369 ps
T51 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1259543296 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:53 PM PDT 24 5000742592 ps
T48 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.23063983 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:52 PM PDT 24 4216334094 ps
T795 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.548229043 Jul 17 05:27:42 PM PDT 24 Jul 17 05:27:44 PM PDT 24 347803437 ps
T87 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.35359511 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:47 PM PDT 24 604761921 ps
T49 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.68808523 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 2289792986 ps
T796 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.382761429 Jul 17 05:29:06 PM PDT 24 Jul 17 05:29:08 PM PDT 24 439583477 ps
T797 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3131507913 Jul 17 05:27:39 PM PDT 24 Jul 17 05:27:41 PM PDT 24 435883675 ps
T55 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1016091236 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 581420081 ps
T68 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2866213437 Jul 17 05:26:43 PM PDT 24 Jul 17 05:26:45 PM PDT 24 766267194 ps
T52 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3017147084 Jul 17 05:26:48 PM PDT 24 Jul 17 05:27:00 PM PDT 24 8598174839 ps
T60 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1765100720 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:57 PM PDT 24 470632758 ps
T88 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1624731282 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:55 PM PDT 24 594230912 ps
T798 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1772740212 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:21 PM PDT 24 362126165 ps
T799 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2394284359 Jul 17 05:32:43 PM PDT 24 Jul 17 05:32:44 PM PDT 24 309753680 ps
T122 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1720940690 Jul 17 05:28:42 PM PDT 24 Jul 17 05:28:45 PM PDT 24 2462719999 ps
T53 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1642091196 Jul 17 05:26:44 PM PDT 24 Jul 17 05:27:05 PM PDT 24 8238352559 ps
T63 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4163848315 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:22 PM PDT 24 425393309 ps
T69 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.396488940 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:49 PM PDT 24 446995091 ps
T127 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2064991757 Jul 17 05:27:17 PM PDT 24 Jul 17 05:27:22 PM PDT 24 1080866873 ps
T800 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.100479461 Jul 17 05:33:52 PM PDT 24 Jul 17 05:33:57 PM PDT 24 542800154 ps
T801 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.958966434 Jul 17 05:29:57 PM PDT 24 Jul 17 05:29:59 PM PDT 24 542157852 ps
T111 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4215810396 Jul 17 05:27:34 PM PDT 24 Jul 17 05:27:38 PM PDT 24 888760975 ps
T802 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.251195812 Jul 17 05:29:57 PM PDT 24 Jul 17 05:30:00 PM PDT 24 515525222 ps
T803 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1479607980 Jul 17 05:32:43 PM PDT 24 Jul 17 05:32:45 PM PDT 24 416827910 ps
T61 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2596732382 Jul 17 05:26:47 PM PDT 24 Jul 17 05:26:54 PM PDT 24 478044482 ps
T306 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3457518735 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:31 PM PDT 24 4526173695 ps
T123 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2147577445 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:53 PM PDT 24 441772029 ps
T804 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4064445247 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:57 PM PDT 24 717311275 ps
T805 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1533819053 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 448108361 ps
T124 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2151532616 Jul 17 05:27:16 PM PDT 24 Jul 17 05:27:33 PM PDT 24 4876324634 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2599577051 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:55 PM PDT 24 592237622 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2553309817 Jul 17 05:26:45 PM PDT 24 Jul 17 05:27:19 PM PDT 24 51509595948 ps
T62 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4192012715 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:56 PM PDT 24 388213393 ps
T807 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2146845400 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:49 PM PDT 24 491531445 ps
T125 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3103333502 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:53 PM PDT 24 515311320 ps
T113 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.224834528 Jul 17 05:26:46 PM PDT 24 Jul 17 05:27:10 PM PDT 24 52478488552 ps
T808 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4107641224 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 627994611 ps
T809 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.137122408 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:54 PM PDT 24 647516649 ps
T72 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1157576124 Jul 17 05:26:49 PM PDT 24 Jul 17 05:27:03 PM PDT 24 8480335494 ps
T126 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.630256284 Jul 17 05:27:24 PM PDT 24 Jul 17 05:27:30 PM PDT 24 2417991289 ps
T810 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.179562483 Jul 17 05:27:42 PM PDT 24 Jul 17 05:27:44 PM PDT 24 324125068 ps
T114 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3273933034 Jul 17 05:27:17 PM PDT 24 Jul 17 05:27:20 PM PDT 24 544723433 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1725553386 Jul 17 05:26:42 PM PDT 24 Jul 17 05:26:44 PM PDT 24 534776453 ps
T115 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.581423119 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 428006572 ps
T812 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3067544987 Jul 17 05:28:15 PM PDT 24 Jul 17 05:28:19 PM PDT 24 371568286 ps
T70 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1079094636 Jul 17 05:28:42 PM PDT 24 Jul 17 05:29:03 PM PDT 24 8438119175 ps
T813 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.53595693 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:21 PM PDT 24 3285779599 ps
T64 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.281271337 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:22 PM PDT 24 384691119 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4142487998 Jul 17 05:26:49 PM PDT 24 Jul 17 05:27:11 PM PDT 24 22039160205 ps
T814 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2801593319 Jul 17 05:26:48 PM PDT 24 Jul 17 05:27:05 PM PDT 24 3878629908 ps
T815 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.182690959 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 869604479 ps
T816 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1573024854 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:55 PM PDT 24 4253304989 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1943212794 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:49 PM PDT 24 384027170 ps
T818 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2438488825 Jul 17 05:26:44 PM PDT 24 Jul 17 05:26:49 PM PDT 24 915240091 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3256955284 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 2009704059 ps
T71 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1987325813 Jul 17 05:27:16 PM PDT 24 Jul 17 05:27:19 PM PDT 24 514536669 ps
T820 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3937132540 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 4950091438 ps
T821 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1302605442 Jul 17 05:27:36 PM PDT 24 Jul 17 05:27:39 PM PDT 24 545282824 ps
T822 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.613087261 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:20 PM PDT 24 472881997 ps
T823 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1015015740 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:59 PM PDT 24 1826163149 ps
T824 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1852850697 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:58 PM PDT 24 2806701896 ps
T305 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1550684191 Jul 17 05:26:48 PM PDT 24 Jul 17 05:27:12 PM PDT 24 7565467784 ps
T825 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3750856191 Jul 17 05:27:42 PM PDT 24 Jul 17 05:27:43 PM PDT 24 316648502 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1092591847 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:57 PM PDT 24 526013947 ps
T827 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3455258818 Jul 17 05:26:47 PM PDT 24 Jul 17 05:26:52 PM PDT 24 605345605 ps
T828 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1598633678 Jul 17 05:26:49 PM PDT 24 Jul 17 05:27:07 PM PDT 24 4393797302 ps
T829 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.976647311 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:26 PM PDT 24 4455424057 ps
T830 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2940153437 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:20 PM PDT 24 482987826 ps
T831 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2831704165 Jul 17 05:28:15 PM PDT 24 Jul 17 05:28:19 PM PDT 24 305234855 ps
T832 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3636858295 Jul 17 05:27:42 PM PDT 24 Jul 17 05:27:43 PM PDT 24 353109252 ps
T833 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3933337094 Jul 17 05:28:40 PM PDT 24 Jul 17 05:28:53 PM PDT 24 2610723852 ps
T834 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2922182495 Jul 17 05:30:28 PM PDT 24 Jul 17 05:30:30 PM PDT 24 301353821 ps
T835 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.882415869 Jul 17 05:27:19 PM PDT 24 Jul 17 05:27:23 PM PDT 24 5289965153 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3278532611 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:55 PM PDT 24 539737197 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4102973351 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:51 PM PDT 24 351746216 ps
T838 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.787594879 Jul 17 05:26:49 PM PDT 24 Jul 17 05:27:02 PM PDT 24 1865542931 ps
T839 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3758308982 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:58 PM PDT 24 437639158 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1329029870 Jul 17 05:26:44 PM PDT 24 Jul 17 05:26:49 PM PDT 24 1320862625 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.379187237 Jul 17 05:26:47 PM PDT 24 Jul 17 05:26:53 PM PDT 24 350287523 ps
T841 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2853677829 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:55 PM PDT 24 416334946 ps
T118 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3408384624 Jul 17 05:26:45 PM PDT 24 Jul 17 05:27:03 PM PDT 24 24641230439 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3917782879 Jul 17 05:26:49 PM PDT 24 Jul 17 05:27:04 PM PDT 24 8265091093 ps
T843 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3854230391 Jul 17 05:26:48 PM PDT 24 Jul 17 05:27:02 PM PDT 24 7616039463 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2660774458 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:56 PM PDT 24 8395001543 ps
T845 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4004480757 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 329559040 ps
T846 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.121180215 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:55 PM PDT 24 593888632 ps
T847 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2293924936 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 353062309 ps
T848 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3046032706 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:49 PM PDT 24 509086119 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3943885902 Jul 17 05:28:42 PM PDT 24 Jul 17 05:28:44 PM PDT 24 681697314 ps
T850 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.231342461 Jul 17 05:27:34 PM PDT 24 Jul 17 05:27:38 PM PDT 24 453572467 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.365141454 Jul 17 05:27:14 PM PDT 24 Jul 17 05:27:16 PM PDT 24 425733822 ps
T852 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3611140845 Jul 17 05:27:19 PM PDT 24 Jul 17 05:27:26 PM PDT 24 2378730172 ps
T853 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.950000594 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:49 PM PDT 24 408918101 ps
T854 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3494102158 Jul 17 05:27:15 PM PDT 24 Jul 17 05:27:18 PM PDT 24 546393150 ps
T855 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.272060359 Jul 17 05:26:43 PM PDT 24 Jul 17 05:26:55 PM PDT 24 7901856687 ps
T121 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1247613619 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:54 PM PDT 24 468370317 ps
T856 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2597583461 Jul 17 05:30:24 PM PDT 24 Jul 17 05:30:26 PM PDT 24 449220560 ps
T857 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.564571822 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 460323939 ps
T119 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3863670945 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:50 PM PDT 24 378289176 ps
T858 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.318925701 Jul 17 05:33:46 PM PDT 24 Jul 17 05:33:49 PM PDT 24 381539302 ps
T859 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2736551844 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 299249408 ps
T860 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1035608797 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:51 PM PDT 24 718396897 ps
T861 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1804439071 Jul 17 05:26:50 PM PDT 24 Jul 17 05:27:03 PM PDT 24 4595740608 ps
T862 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.932529913 Jul 17 05:32:11 PM PDT 24 Jul 17 05:32:13 PM PDT 24 396671421 ps
T863 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2594382913 Jul 17 05:27:34 PM PDT 24 Jul 17 05:27:36 PM PDT 24 291840268 ps
T864 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.747334837 Jul 17 05:26:41 PM PDT 24 Jul 17 05:26:43 PM PDT 24 701899953 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3198060838 Jul 17 05:26:42 PM PDT 24 Jul 17 05:26:45 PM PDT 24 668031719 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2379764358 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 514555824 ps
T867 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.516489131 Jul 17 05:26:43 PM PDT 24 Jul 17 05:26:44 PM PDT 24 449609671 ps
T868 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2159799857 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:58 PM PDT 24 4488234693 ps
T869 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4211716134 Jul 17 05:27:42 PM PDT 24 Jul 17 05:27:43 PM PDT 24 347533895 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1698814589 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:50 PM PDT 24 4387035735 ps
T871 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1637954340 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:51 PM PDT 24 418196714 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.883567380 Jul 17 05:27:34 PM PDT 24 Jul 17 05:27:45 PM PDT 24 4379256384 ps
T873 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2373356022 Jul 17 05:30:55 PM PDT 24 Jul 17 05:30:57 PM PDT 24 415228262 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4151008058 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:54 PM PDT 24 501211999 ps
T875 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1924911522 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:49 PM PDT 24 361346139 ps
T876 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3043670517 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:57 PM PDT 24 485690678 ps
T120 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3548956783 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:54 PM PDT 24 447624438 ps
T877 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3129068379 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:53 PM PDT 24 293646001 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2845870809 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:49 PM PDT 24 430765732 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2316737640 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:21 PM PDT 24 464750773 ps
T880 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1243969185 Jul 17 05:27:39 PM PDT 24 Jul 17 05:27:41 PM PDT 24 531187627 ps
T881 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4040989476 Jul 17 05:27:44 PM PDT 24 Jul 17 05:27:47 PM PDT 24 471330282 ps
T882 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3591226541 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:54 PM PDT 24 361024837 ps
T883 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4280283324 Jul 17 05:26:49 PM PDT 24 Jul 17 05:27:06 PM PDT 24 4477116487 ps
T884 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1093206389 Jul 17 05:26:43 PM PDT 24 Jul 17 05:26:47 PM PDT 24 1385617506 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2212065129 Jul 17 05:26:46 PM PDT 24 Jul 17 05:27:09 PM PDT 24 8162454099 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.642010251 Jul 17 05:27:17 PM PDT 24 Jul 17 05:27:23 PM PDT 24 9174043832 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3900893319 Jul 17 05:26:44 PM PDT 24 Jul 17 05:26:48 PM PDT 24 1084960460 ps
T888 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1027478273 Jul 17 05:30:55 PM PDT 24 Jul 17 05:30:57 PM PDT 24 423726611 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1742613095 Jul 17 05:27:18 PM PDT 24 Jul 17 05:27:31 PM PDT 24 4295521373 ps
T890 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3924106631 Jul 17 05:27:45 PM PDT 24 Jul 17 05:27:49 PM PDT 24 510129613 ps
T891 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2971023782 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:49 PM PDT 24 617756430 ps
T892 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.271522697 Jul 17 05:27:37 PM PDT 24 Jul 17 05:27:39 PM PDT 24 466688890 ps
T893 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3556885278 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:54 PM PDT 24 499747696 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2249100521 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:49 PM PDT 24 563487920 ps
T895 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.955604063 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:59 PM PDT 24 619044566 ps
T896 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1002319827 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 437462594 ps
T897 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.464929712 Jul 17 05:30:28 PM PDT 24 Jul 17 05:30:30 PM PDT 24 400396561 ps
T898 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1050406044 Jul 17 05:29:42 PM PDT 24 Jul 17 05:29:45 PM PDT 24 535728024 ps
T899 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2569808303 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:57 PM PDT 24 683552346 ps
T900 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3210817367 Jul 17 05:26:50 PM PDT 24 Jul 17 05:27:00 PM PDT 24 9049360373 ps
T73 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2296678104 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:59 PM PDT 24 4406205567 ps
T901 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1845198263 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:54 PM PDT 24 332399365 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.411467732 Jul 17 05:26:41 PM PDT 24 Jul 17 05:26:43 PM PDT 24 751010594 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4190446806 Jul 17 05:27:34 PM PDT 24 Jul 17 05:27:41 PM PDT 24 3907003268 ps
T904 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3339866321 Jul 17 05:26:44 PM PDT 24 Jul 17 05:26:46 PM PDT 24 584050984 ps
T905 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.820515680 Jul 17 05:27:34 PM PDT 24 Jul 17 05:27:37 PM PDT 24 1151456525 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1897786376 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:51 PM PDT 24 1042497275 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2028135419 Jul 17 05:26:44 PM PDT 24 Jul 17 05:26:46 PM PDT 24 369982136 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1747426669 Jul 17 05:26:48 PM PDT 24 Jul 17 05:26:55 PM PDT 24 427715931 ps
T909 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2907226049 Jul 17 05:26:47 PM PDT 24 Jul 17 05:26:51 PM PDT 24 395006966 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2133789723 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:49 PM PDT 24 509215472 ps
T911 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1988125304 Jul 17 05:29:49 PM PDT 24 Jul 17 05:29:51 PM PDT 24 465252289 ps
T912 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3842599064 Jul 17 05:26:45 PM PDT 24 Jul 17 05:26:48 PM PDT 24 458037920 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4291350694 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:50 PM PDT 24 499224269 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2152911722 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:49 PM PDT 24 1319479175 ps
T915 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3575535084 Jul 17 05:28:38 PM PDT 24 Jul 17 05:28:41 PM PDT 24 418500019 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2147517873 Jul 17 05:26:46 PM PDT 24 Jul 17 05:26:49 PM PDT 24 421681423 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1072922286 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 469939106 ps
T918 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2874238167 Jul 17 05:33:46 PM PDT 24 Jul 17 05:33:47 PM PDT 24 475458659 ps
T919 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2989572635 Jul 17 05:27:54 PM PDT 24 Jul 17 05:27:56 PM PDT 24 470284750 ps

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3934116373
Short name T8
Test name
Test status
Simulation time 288017338049 ps
CPU time 132.49 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:38:20 PM PDT 24
Peak memory 209896 kb
Host smart-f7fe0a8d-3b43-43f1-ba02-bd97548e3d9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934116373 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3934116373
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3126151975
Short name T25
Test name
Test status
Simulation time 495756216865 ps
CPU time 202.48 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:39:45 PM PDT 24
Peak memory 201588 kb
Host smart-d1945712-1fb1-4c35-992c-f9d725450b10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126151975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3126151975
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3505304200
Short name T14
Test name
Test status
Simulation time 415694925222 ps
CPU time 318.54 seconds
Started Jul 17 05:35:28 PM PDT 24
Finished Jul 17 05:40:48 PM PDT 24
Peak memory 210176 kb
Host smart-5da0ef3f-4544-47d5-8af2-98b8db97975c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505304200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3505304200
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3625781920
Short name T147
Test name
Test status
Simulation time 1420547731118 ps
CPU time 332.97 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:40:44 PM PDT 24
Peak memory 211204 kb
Host smart-0bbd13b7-6863-4a4d-be06-ecc6bd83e03a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625781920 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3625781920
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.279091957
Short name T32
Test name
Test status
Simulation time 1260486482592 ps
CPU time 161.42 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:39:37 PM PDT 24
Peak memory 212268 kb
Host smart-263226a1-dfa6-429c-943d-59367c78ff7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279091957 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.279091957
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1557553549
Short name T31
Test name
Test status
Simulation time 109931676966 ps
CPU time 129.32 seconds
Started Jul 17 05:33:59 PM PDT 24
Finished Jul 17 05:36:09 PM PDT 24
Peak memory 217596 kb
Host smart-85ace595-6062-44e6-a380-d83b4cb89e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557553549 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1557553549
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.277554532
Short name T109
Test name
Test status
Simulation time 490696663146 ps
CPU time 289.99 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:40:29 PM PDT 24
Peak memory 201560 kb
Host smart-6c5a0929-c666-49df-a09b-01d4cb77b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277554532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.277554532
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1740732453
Short name T204
Test name
Test status
Simulation time 508120221748 ps
CPU time 1252.26 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:55:02 PM PDT 24
Peak memory 201452 kb
Host smart-d3c5b38a-f7c2-412e-80ff-37017cf04524
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740732453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1740732453
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1493595244
Short name T149
Test name
Test status
Simulation time 485964260403 ps
CPU time 266.09 seconds
Started Jul 17 05:36:31 PM PDT 24
Finished Jul 17 05:40:59 PM PDT 24
Peak memory 201444 kb
Host smart-2095e37d-50f7-40c4-aa66-7e542a07d31d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493595244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1493595244
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1290754237
Short name T219
Test name
Test status
Simulation time 521060448399 ps
CPU time 722.98 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:45:59 PM PDT 24
Peak memory 201476 kb
Host smart-3b2d3363-52c2-4960-a1ac-7e783b96205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290754237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1290754237
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2368370083
Short name T215
Test name
Test status
Simulation time 519295132801 ps
CPU time 1093.3 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:55:35 PM PDT 24
Peak memory 201540 kb
Host smart-0037d3f5-7bd3-47b7-8da3-5b636e0c58f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368370083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2368370083
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4082030226
Short name T3
Test name
Test status
Simulation time 329778573497 ps
CPU time 574.98 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:45:57 PM PDT 24
Peak memory 201384 kb
Host smart-ab28fb50-7c81-4d7d-870d-8a3ca9b99e57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082030226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4082030226
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4163848315
Short name T63
Test name
Test status
Simulation time 425393309 ps
CPU time 1.92 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:22 PM PDT 24
Peak memory 201480 kb
Host smart-b944369d-765e-4448-8f20-651d0873ed95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163848315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.4163848315
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.813834705
Short name T142
Test name
Test status
Simulation time 330690356264 ps
CPU time 783.58 seconds
Started Jul 17 05:37:45 PM PDT 24
Finished Jul 17 05:50:51 PM PDT 24
Peak memory 201520 kb
Host smart-d3d10e90-60fb-427c-8999-1f27a141a64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813834705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
813834705
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3921255708
Short name T17
Test name
Test status
Simulation time 51920001097 ps
CPU time 102.06 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:39:03 PM PDT 24
Peak memory 217948 kb
Host smart-1017ac15-5f9e-4d41-b73c-1fd1a7805e72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921255708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3921255708
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.880665086
Short name T67
Test name
Test status
Simulation time 525333104 ps
CPU time 1.72 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:33:57 PM PDT 24
Peak memory 201276 kb
Host smart-37185739-9954-46d1-bdae-e79d646e7968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880665086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.880665086
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2553309817
Short name T112
Test name
Test status
Simulation time 51509595948 ps
CPU time 32.78 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:27:19 PM PDT 24
Peak memory 201788 kb
Host smart-1e57d70a-5a25-4b21-8437-a606d42e54bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553309817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2553309817
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3031931556
Short name T132
Test name
Test status
Simulation time 650427238334 ps
CPU time 306.19 seconds
Started Jul 17 05:34:18 PM PDT 24
Finished Jul 17 05:39:26 PM PDT 24
Peak memory 201516 kb
Host smart-1ac0b021-3016-400b-9bd9-38adc37480cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031931556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3031931556
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1157576124
Short name T72
Test name
Test status
Simulation time 8480335494 ps
CPU time 8.6 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:27:03 PM PDT 24
Peak memory 201716 kb
Host smart-ad5a5238-a908-4c32-a2cf-c9fc7037f38d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157576124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1157576124
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3618908172
Short name T200
Test name
Test status
Simulation time 545421531742 ps
CPU time 582.61 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:43:51 PM PDT 24
Peak memory 201500 kb
Host smart-4b7dfb25-60b0-438f-9f3e-f492a7216b35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618908172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3618908172
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3420746108
Short name T158
Test name
Test status
Simulation time 512784171834 ps
CPU time 226.35 seconds
Started Jul 17 05:33:01 PM PDT 24
Finished Jul 17 05:36:48 PM PDT 24
Peak memory 201508 kb
Host smart-5b685475-f4d3-4c4d-bdbe-2b92cb9a1f2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420746108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3420746108
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3546310442
Short name T199
Test name
Test status
Simulation time 533360736003 ps
CPU time 1187.26 seconds
Started Jul 17 05:34:02 PM PDT 24
Finished Jul 17 05:53:50 PM PDT 24
Peak memory 201448 kb
Host smart-bf596d12-773c-4a3e-acd0-6a358bd37f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546310442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3546310442
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4246837297
Short name T146
Test name
Test status
Simulation time 506502190197 ps
CPU time 157.02 seconds
Started Jul 17 05:35:20 PM PDT 24
Finished Jul 17 05:37:58 PM PDT 24
Peak memory 201588 kb
Host smart-9c554172-020b-497e-baee-750e39903e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246837297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4246837297
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2238025839
Short name T227
Test name
Test status
Simulation time 486002584362 ps
CPU time 89.29 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:35:45 PM PDT 24
Peak memory 201464 kb
Host smart-f664ff51-b684-4199-8471-4fe99be4d726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238025839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2238025839
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4118825953
Short name T156
Test name
Test status
Simulation time 352812018613 ps
CPU time 414.7 seconds
Started Jul 17 05:33:22 PM PDT 24
Finished Jul 17 05:40:17 PM PDT 24
Peak memory 201516 kb
Host smart-4a859474-1932-4f87-8f6a-dae61adfaa47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118825953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4118825953
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1743684977
Short name T75
Test name
Test status
Simulation time 4255947043 ps
CPU time 3.4 seconds
Started Jul 17 05:31:30 PM PDT 24
Finished Jul 17 05:31:36 PM PDT 24
Peak memory 217080 kb
Host smart-4580e109-02eb-4220-ab13-69f32aa8de12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743684977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1743684977
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3620125461
Short name T39
Test name
Test status
Simulation time 565159854675 ps
CPU time 1163.18 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:53:29 PM PDT 24
Peak memory 201540 kb
Host smart-2c38163d-1434-4b0c-b532-5702eb87b7a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620125461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3620125461
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3644635825
Short name T225
Test name
Test status
Simulation time 491997786621 ps
CPU time 577.97 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:44:49 PM PDT 24
Peak memory 201612 kb
Host smart-2ea1d48e-6761-4749-997a-1fff915b70ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644635825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3644635825
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.387219077
Short name T174
Test name
Test status
Simulation time 540502567051 ps
CPU time 165.24 seconds
Started Jul 17 05:33:23 PM PDT 24
Finished Jul 17 05:36:09 PM PDT 24
Peak memory 201616 kb
Host smart-6ce9e09c-65f5-4265-af51-ece9d321e6f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387219077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.387219077
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3407063101
Short name T194
Test name
Test status
Simulation time 501579880120 ps
CPU time 92.53 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:33:28 PM PDT 24
Peak memory 201596 kb
Host smart-1dc39f15-8cea-4357-8e02-52563c7b30fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407063101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3407063101
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1950275059
Short name T247
Test name
Test status
Simulation time 508644619280 ps
CPU time 519.23 seconds
Started Jul 17 05:36:42 PM PDT 24
Finished Jul 17 05:45:22 PM PDT 24
Peak memory 201544 kb
Host smart-dab3e0e9-de24-4853-b292-a15fa720191c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950275059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1950275059
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1643865719
Short name T197
Test name
Test status
Simulation time 431748803386 ps
CPU time 242.39 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:39:22 PM PDT 24
Peak memory 201604 kb
Host smart-fa3db305-75fa-45d6-9d57-0cf9ba67da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643865719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1643865719
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2757329762
Short name T259
Test name
Test status
Simulation time 378159985337 ps
CPU time 882.72 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 201452 kb
Host smart-bc58e751-5b89-470d-b5cb-af2bae4155b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757329762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2757329762
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.281271337
Short name T64
Test name
Test status
Simulation time 384691119 ps
CPU time 2.82 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:22 PM PDT 24
Peak memory 201652 kb
Host smart-45ff36e6-1107-4e29-9b4a-5d0bceff1378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281271337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.281271337
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3218798056
Short name T208
Test name
Test status
Simulation time 481193280938 ps
CPU time 1066.68 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:53:54 PM PDT 24
Peak memory 201528 kb
Host smart-cc371b31-fc58-4676-8ac6-531f81c37235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218798056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3218798056
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2056611377
Short name T85
Test name
Test status
Simulation time 408808475952 ps
CPU time 274.54 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:38:52 PM PDT 24
Peak memory 210308 kb
Host smart-ecd88be0-a4b8-4254-8ffe-6dbd71c42402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056611377 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2056611377
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2085780528
Short name T234
Test name
Test status
Simulation time 506203687497 ps
CPU time 277.83 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:39:49 PM PDT 24
Peak memory 201548 kb
Host smart-875fab8b-ef14-4cc0-b4d3-98f84e514781
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085780528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2085780528
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3403038468
Short name T236
Test name
Test status
Simulation time 268704835867 ps
CPU time 267.01 seconds
Started Jul 17 05:31:39 PM PDT 24
Finished Jul 17 05:36:07 PM PDT 24
Peak memory 201904 kb
Host smart-38d7d499-7049-42b5-b84c-e8c0d41734e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403038468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3403038468
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.140079392
Short name T161
Test name
Test status
Simulation time 493044965608 ps
CPU time 1213.89 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:54:24 PM PDT 24
Peak memory 201556 kb
Host smart-791b04fb-c3f4-4b32-8bac-a0365972d77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140079392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.140079392
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3779330296
Short name T42
Test name
Test status
Simulation time 77632257070 ps
CPU time 389.57 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:40:41 PM PDT 24
Peak memory 201888 kb
Host smart-3e4efabf-e5d7-4d9a-ad67-08cb7c8bcbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779330296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3779330296
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.120316060
Short name T239
Test name
Test status
Simulation time 327271209762 ps
CPU time 632.75 seconds
Started Jul 17 05:36:38 PM PDT 24
Finished Jul 17 05:47:11 PM PDT 24
Peak memory 201480 kb
Host smart-747ae2fc-bc04-4ac1-9047-f1abd24ade1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120316060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.120316060
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2846883066
Short name T224
Test name
Test status
Simulation time 509050440519 ps
CPU time 876.54 seconds
Started Jul 17 05:35:07 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 201544 kb
Host smart-5359a0f2-6a35-47f9-99c4-b62dc0c2f1b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846883066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2846883066
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2480725861
Short name T35
Test name
Test status
Simulation time 310994811950 ps
CPU time 178.35 seconds
Started Jul 17 05:33:21 PM PDT 24
Finished Jul 17 05:36:21 PM PDT 24
Peak memory 209800 kb
Host smart-ffc123e7-7b27-43f3-84e1-8e03d5f3544a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480725861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2480725861
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1381088963
Short name T206
Test name
Test status
Simulation time 384196557147 ps
CPU time 486.57 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:41:05 PM PDT 24
Peak memory 201536 kb
Host smart-2897035d-b13f-4efe-bfbd-5278f4b1a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381088963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1381088963
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2147577445
Short name T123
Test name
Test status
Simulation time 441772029 ps
CPU time 0.99 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:53 PM PDT 24
Peak memory 201432 kb
Host smart-b413fa4b-55e6-46c9-a3a8-5e89d49ecd63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147577445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2147577445
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.502927732
Short name T251
Test name
Test status
Simulation time 284229416641 ps
CPU time 338.52 seconds
Started Jul 17 05:36:17 PM PDT 24
Finished Jul 17 05:41:56 PM PDT 24
Peak memory 201884 kb
Host smart-930539b8-835c-4408-b5d0-54e7efb25cad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502927732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
502927732
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2057609188
Short name T238
Test name
Test status
Simulation time 336778168850 ps
CPU time 203.58 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:37:29 PM PDT 24
Peak memory 201500 kb
Host smart-a962cbe2-744b-4095-ad6f-7db3a5311159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057609188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2057609188
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2540831572
Short name T223
Test name
Test status
Simulation time 356790031456 ps
CPU time 172.61 seconds
Started Jul 17 05:32:09 PM PDT 24
Finished Jul 17 05:35:02 PM PDT 24
Peak memory 201492 kb
Host smart-84f6781e-01cf-4088-acf8-54faef44e277
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540831572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2540831572
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3561992451
Short name T351
Test name
Test status
Simulation time 199134222440 ps
CPU time 315.76 seconds
Started Jul 17 05:33:57 PM PDT 24
Finished Jul 17 05:39:15 PM PDT 24
Peak memory 201512 kb
Host smart-387b589c-bc20-4367-ae21-9211ddba598d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561992451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3561992451
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1156508279
Short name T150
Test name
Test status
Simulation time 165515282793 ps
CPU time 115.51 seconds
Started Jul 17 05:36:34 PM PDT 24
Finished Jul 17 05:38:30 PM PDT 24
Peak memory 201412 kb
Host smart-f6815ad9-2c72-47f3-a7cd-726c12c7b21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156508279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1156508279
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.633098613
Short name T38
Test name
Test status
Simulation time 356774836136 ps
CPU time 96.19 seconds
Started Jul 17 05:37:10 PM PDT 24
Finished Jul 17 05:38:48 PM PDT 24
Peak memory 201564 kb
Host smart-a3bf67bc-9a3b-4217-b546-b25647df8b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633098613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.633098613
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.601726807
Short name T289
Test name
Test status
Simulation time 86874671839 ps
CPU time 179.94 seconds
Started Jul 17 05:34:00 PM PDT 24
Finished Jul 17 05:37:01 PM PDT 24
Peak memory 209920 kb
Host smart-bbaa1733-9e13-4c57-878e-7b2c4edaa2c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601726807 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.601726807
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2437594470
Short name T27
Test name
Test status
Simulation time 464117716191 ps
CPU time 1436.33 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:57:51 PM PDT 24
Peak memory 210260 kb
Host smart-da64de30-34a8-4844-a514-cb39f4e65ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437594470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2437594470
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.958660556
Short name T139
Test name
Test status
Simulation time 336905179761 ps
CPU time 733.53 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:47:30 PM PDT 24
Peak memory 201476 kb
Host smart-9ff04889-340b-43c1-b231-0fe92a45d105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958660556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.958660556
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2364753243
Short name T34
Test name
Test status
Simulation time 73168696130 ps
CPU time 171.57 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:34:47 PM PDT 24
Peak memory 210048 kb
Host smart-dcf512fb-1d6e-4de5-a604-8b7025c9f7f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364753243 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2364753243
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1296212193
Short name T220
Test name
Test status
Simulation time 484780513723 ps
CPU time 135.79 seconds
Started Jul 17 05:35:25 PM PDT 24
Finished Jul 17 05:37:42 PM PDT 24
Peak memory 201512 kb
Host smart-70b8fbc9-ebfb-46ce-97d5-bc2ff1a577ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296212193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1296212193
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2574770576
Short name T280
Test name
Test status
Simulation time 653498247613 ps
CPU time 367.77 seconds
Started Jul 17 05:37:32 PM PDT 24
Finished Jul 17 05:43:42 PM PDT 24
Peak memory 201584 kb
Host smart-812cebc7-3115-418d-81d5-616b782e10c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574770576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2574770576
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.857844897
Short name T252
Test name
Test status
Simulation time 551649417712 ps
CPU time 1332.65 seconds
Started Jul 17 05:37:47 PM PDT 24
Finished Jul 17 06:00:01 PM PDT 24
Peak memory 201444 kb
Host smart-7be76cee-95ea-4e7d-8550-94d9488f86d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857844897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.857844897
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1678475540
Short name T179
Test name
Test status
Simulation time 489238674016 ps
CPU time 315.65 seconds
Started Jul 17 05:32:05 PM PDT 24
Finished Jul 17 05:37:22 PM PDT 24
Peak memory 201528 kb
Host smart-80789f33-74a8-4107-815a-941ba9528450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678475540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1678475540
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2392159052
Short name T240
Test name
Test status
Simulation time 491284277060 ps
CPU time 300.69 seconds
Started Jul 17 05:34:45 PM PDT 24
Finished Jul 17 05:39:46 PM PDT 24
Peak memory 201592 kb
Host smart-9446b230-b630-4a1c-b5de-7b214418e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392159052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2392159052
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1856772200
Short name T287
Test name
Test status
Simulation time 357683295369 ps
CPU time 498.88 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:43:31 PM PDT 24
Peak memory 201516 kb
Host smart-1cf61eee-09dc-492a-8e69-fd117e1e17a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856772200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1856772200
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1583014531
Short name T295
Test name
Test status
Simulation time 166855214231 ps
CPU time 180.13 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:39:56 PM PDT 24
Peak memory 201592 kb
Host smart-21f71dfb-15df-47d2-9c89-3cf04397dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583014531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1583014531
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1079094636
Short name T70
Test name
Test status
Simulation time 8438119175 ps
CPU time 20.34 seconds
Started Jul 17 05:28:42 PM PDT 24
Finished Jul 17 05:29:03 PM PDT 24
Peak memory 201780 kb
Host smart-d5e1ec2e-465e-4559-b171-a1c0d29365ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079094636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1079094636
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2273481337
Short name T313
Test name
Test status
Simulation time 296991294006 ps
CPU time 991.47 seconds
Started Jul 17 05:33:08 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 201888 kb
Host smart-59d6d9b2-2eae-4195-83a2-71bae219f48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273481337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2273481337
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1237493317
Short name T235
Test name
Test status
Simulation time 323170418237 ps
CPU time 335.26 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:39:32 PM PDT 24
Peak memory 201532 kb
Host smart-9d455284-9734-46ad-b386-d184313d66e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237493317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1237493317
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3999116622
Short name T249
Test name
Test status
Simulation time 496982805094 ps
CPU time 628.51 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:44:23 PM PDT 24
Peak memory 201588 kb
Host smart-d8a4df52-3da8-40c9-a875-10adb4a6d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999116622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3999116622
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2947390619
Short name T99
Test name
Test status
Simulation time 334174797705 ps
CPU time 386.37 seconds
Started Jul 17 05:31:46 PM PDT 24
Finished Jul 17 05:38:13 PM PDT 24
Peak memory 201508 kb
Host smart-6e071e99-021c-4ee7-bcbb-1e8cc205b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947390619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2947390619
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3325790360
Short name T728
Test name
Test status
Simulation time 269499056496 ps
CPU time 313.6 seconds
Started Jul 17 05:34:29 PM PDT 24
Finished Jul 17 05:39:43 PM PDT 24
Peak memory 212832 kb
Host smart-b8052fdc-5c0d-456d-b08a-afd0b5819a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325790360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3325790360
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2961784995
Short name T171
Test name
Test status
Simulation time 477574820339 ps
CPU time 302.48 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:39:49 PM PDT 24
Peak memory 201600 kb
Host smart-d09ae7ad-b693-4d79-8726-5cad12e4604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961784995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2961784995
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.614477343
Short name T29
Test name
Test status
Simulation time 109395480732 ps
CPU time 226.86 seconds
Started Jul 17 05:35:41 PM PDT 24
Finished Jul 17 05:39:28 PM PDT 24
Peak memory 209892 kb
Host smart-d8ee6fbf-c08f-4e1b-82c1-280088d69974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614477343 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.614477343
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3016511074
Short name T294
Test name
Test status
Simulation time 619015876212 ps
CPU time 1300.28 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:58:03 PM PDT 24
Peak memory 201440 kb
Host smart-d0279323-18ac-46b6-8afc-2e031b6b2525
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016511074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3016511074
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3950700213
Short name T1
Test name
Test status
Simulation time 167809386911 ps
CPU time 103.01 seconds
Started Jul 17 05:36:42 PM PDT 24
Finished Jul 17 05:38:26 PM PDT 24
Peak memory 201524 kb
Host smart-bb046131-dc2e-4596-b9bf-7d82f79aaa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950700213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3950700213
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3467791527
Short name T444
Test name
Test status
Simulation time 546891956685 ps
CPU time 338.64 seconds
Started Jul 17 05:37:57 PM PDT 24
Finished Jul 17 05:43:37 PM PDT 24
Peak memory 201456 kb
Host smart-a1cd15a2-d7cb-4c9f-ae7b-88933425d351
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467791527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3467791527
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2866213437
Short name T68
Test name
Test status
Simulation time 766267194 ps
CPU time 1.19 seconds
Started Jul 17 05:26:43 PM PDT 24
Finished Jul 17 05:26:45 PM PDT 24
Peak memory 201528 kb
Host smart-94bcce12-81fb-4cd8-91d7-08d44e64ed9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866213437 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2866213437
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1650512563
Short name T221
Test name
Test status
Simulation time 524076700083 ps
CPU time 249.6 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:37:50 PM PDT 24
Peak memory 201596 kb
Host smart-b43dd430-572b-401e-86c1-17f79cb14301
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650512563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1650512563
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2102043295
Short name T255
Test name
Test status
Simulation time 336473033670 ps
CPU time 803.51 seconds
Started Jul 17 05:33:43 PM PDT 24
Finished Jul 17 05:47:07 PM PDT 24
Peak memory 201528 kb
Host smart-907a843a-6230-4344-8010-6a0f6c9b2d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102043295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2102043295
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2395476888
Short name T281
Test name
Test status
Simulation time 169421643658 ps
CPU time 192.52 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:37:21 PM PDT 24
Peak memory 201468 kb
Host smart-1d886699-205b-4c0e-bc79-8f1e3a86f96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395476888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2395476888
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1753673638
Short name T237
Test name
Test status
Simulation time 360699787799 ps
CPU time 734.82 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:46:31 PM PDT 24
Peak memory 201448 kb
Host smart-423fd658-386b-4a37-818c-dd1690ce89a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753673638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1753673638
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.300169174
Short name T315
Test name
Test status
Simulation time 111712465661 ps
CPU time 573.48 seconds
Started Jul 17 05:34:15 PM PDT 24
Finished Jul 17 05:43:52 PM PDT 24
Peak memory 201904 kb
Host smart-8b3ac8a3-f026-46d6-a708-0dc57612b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300169174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.300169174
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3521326773
Short name T322
Test name
Test status
Simulation time 136304238806 ps
CPU time 731.46 seconds
Started Jul 17 05:31:42 PM PDT 24
Finished Jul 17 05:43:55 PM PDT 24
Peak memory 201872 kb
Host smart-6ebb3821-41c1-472f-91c6-29fe0d351cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521326773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3521326773
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3691104094
Short name T448
Test name
Test status
Simulation time 493444644694 ps
CPU time 1047.46 seconds
Started Jul 17 05:34:28 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 201532 kb
Host smart-e0e64090-3d48-44cf-9022-440c2e84cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691104094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3691104094
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3310723246
Short name T41
Test name
Test status
Simulation time 131812054969 ps
CPU time 692.3 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:46:19 PM PDT 24
Peak memory 201952 kb
Host smart-21615620-43bd-4775-be19-818837a52331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310723246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3310723246
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3644247340
Short name T317
Test name
Test status
Simulation time 109492334622 ps
CPU time 387.92 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:39:40 PM PDT 24
Peak memory 201904 kb
Host smart-d8cf23d1-4f8f-44d7-a904-8ef67e5f6632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644247340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3644247340
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2043784974
Short name T278
Test name
Test status
Simulation time 385265867886 ps
CPU time 839.58 seconds
Started Jul 17 05:36:24 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 201612 kb
Host smart-48d13f88-ea47-46c7-b5ab-016fbf482c91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043784974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2043784974
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.4065816577
Short name T258
Test name
Test status
Simulation time 395987524502 ps
CPU time 168.58 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:34:44 PM PDT 24
Peak memory 201580 kb
Host smart-5d81be00-e711-4063-a5ca-3b44b042a419
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065816577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.4065816577
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2394796278
Short name T323
Test name
Test status
Simulation time 130112087414 ps
CPU time 584.93 seconds
Started Jul 17 05:31:52 PM PDT 24
Finished Jul 17 05:41:38 PM PDT 24
Peak memory 202076 kb
Host smart-77ba4e0f-bdfc-4cce-98ff-af6a6926de7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394796278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2394796278
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2071054435
Short name T316
Test name
Test status
Simulation time 331609430546 ps
CPU time 166.77 seconds
Started Jul 17 05:36:31 PM PDT 24
Finished Jul 17 05:39:19 PM PDT 24
Peak memory 210160 kb
Host smart-509b7b69-711e-4b90-ba23-6e21c36d6c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071054435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2071054435
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3900893319
Short name T887
Test name
Test status
Simulation time 1084960460 ps
CPU time 3.06 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:26:48 PM PDT 24
Peak memory 201664 kb
Host smart-c52bf098-69fe-4c86-a8b5-166b5a2d84d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900893319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3900893319
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.224834528
Short name T113
Test name
Test status
Simulation time 52478488552 ps
CPU time 22.65 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:27:10 PM PDT 24
Peak memory 201784 kb
Host smart-1b151d5b-2572-4139-9b66-9d4924f7c754
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224834528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.224834528
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1035608797
Short name T860
Test name
Test status
Simulation time 718396897 ps
CPU time 2.42 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:51 PM PDT 24
Peak memory 201416 kb
Host smart-bba98faf-5a12-4184-8aac-4c71ecdd189f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035608797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1035608797
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2989572635
Short name T919
Test name
Test status
Simulation time 470284750 ps
CPU time 1.18 seconds
Started Jul 17 05:27:54 PM PDT 24
Finished Jul 17 05:27:56 PM PDT 24
Peak memory 201392 kb
Host smart-d3d2901e-d3f1-45c7-a197-4cfed865556c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989572635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2989572635
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3575535084
Short name T915
Test name
Test status
Simulation time 418500019 ps
CPU time 1.67 seconds
Started Jul 17 05:28:38 PM PDT 24
Finished Jul 17 05:28:41 PM PDT 24
Peak memory 201300 kb
Host smart-94cd05dc-5cec-40fe-8060-a0ae263681ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575535084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3575535084
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.976647311
Short name T829
Test name
Test status
Simulation time 4455424057 ps
CPU time 7.3 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:26 PM PDT 24
Peak memory 201796 kb
Host smart-167f34ba-a38c-4d79-9ca9-9d1a0f9048ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976647311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.976647311
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4102973351
Short name T837
Test name
Test status
Simulation time 351746216 ps
CPU time 2.42 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:51 PM PDT 24
Peak memory 209892 kb
Host smart-8d3ec1e9-56e6-409b-be72-c694c591fc04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102973351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4102973351
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.272060359
Short name T855
Test name
Test status
Simulation time 7901856687 ps
CPU time 11.03 seconds
Started Jul 17 05:26:43 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201788 kb
Host smart-0998483f-d821-4214-b44e-c4c32e338227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272060359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.272060359
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2064991757
Short name T127
Test name
Test status
Simulation time 1080866873 ps
CPU time 4.66 seconds
Started Jul 17 05:27:17 PM PDT 24
Finished Jul 17 05:27:22 PM PDT 24
Peak memory 201652 kb
Host smart-eef2327c-d77a-44ce-8e3c-b6c8eadfdad7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064991757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2064991757
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1093206389
Short name T884
Test name
Test status
Simulation time 1385617506 ps
CPU time 2.65 seconds
Started Jul 17 05:26:43 PM PDT 24
Finished Jul 17 05:26:47 PM PDT 24
Peak memory 201436 kb
Host smart-60b0921c-9e26-4fe6-8206-cdc0d0a7ce4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093206389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1093206389
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2249100521
Short name T894
Test name
Test status
Simulation time 563487920 ps
CPU time 1.21 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201516 kb
Host smart-276f1c50-a416-4d4e-a91d-3ba5871061fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249100521 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2249100521
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3339866321
Short name T904
Test name
Test status
Simulation time 584050984 ps
CPU time 1.09 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:26:46 PM PDT 24
Peak memory 201448 kb
Host smart-d2a2211b-e51a-45ed-87d1-5fe7fcc3384f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339866321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3339866321
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1725553386
Short name T811
Test name
Test status
Simulation time 534776453 ps
CPU time 0.74 seconds
Started Jul 17 05:26:42 PM PDT 24
Finished Jul 17 05:26:44 PM PDT 24
Peak memory 201308 kb
Host smart-9334ecfa-b19f-497d-8605-1b844910d6ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725553386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1725553386
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3933337094
Short name T833
Test name
Test status
Simulation time 2610723852 ps
CPU time 12.53 seconds
Started Jul 17 05:28:40 PM PDT 24
Finished Jul 17 05:28:53 PM PDT 24
Peak memory 201484 kb
Host smart-ceb04625-2f0c-457a-8188-71c65b5b4a4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933337094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3933337094
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1747426669
Short name T908
Test name
Test status
Simulation time 427715931 ps
CPU time 2.29 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201648 kb
Host smart-ea4dc7d6-1319-402e-81ee-aa0aec34a484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747426669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1747426669
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1698814589
Short name T870
Test name
Test status
Simulation time 4387035735 ps
CPU time 4.04 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:50 PM PDT 24
Peak memory 201760 kb
Host smart-081ab910-00ab-4c2f-a3b4-05e11994f20f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698814589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1698814589
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4107641224
Short name T808
Test name
Test status
Simulation time 627994611 ps
CPU time 2.36 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201668 kb
Host smart-d9cc86b2-843a-42d1-be89-3fabc5d5864d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107641224 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4107641224
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1002319827
Short name T896
Test name
Test status
Simulation time 437462594 ps
CPU time 1.76 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201604 kb
Host smart-ab6e52dd-6918-4836-9491-653a723279da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002319827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1002319827
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4151008058
Short name T874
Test name
Test status
Simulation time 501211999 ps
CPU time 0.81 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201308 kb
Host smart-3245cdb0-5754-4505-882d-f86d995ed6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151008058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4151008058
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1015015740
Short name T823
Test name
Test status
Simulation time 1826163149 ps
CPU time 2.79 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:59 PM PDT 24
Peak memory 201420 kb
Host smart-fae08abc-98b8-4f4d-bc1e-cd0824b11395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015015740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1015015740
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2569808303
Short name T899
Test name
Test status
Simulation time 683552346 ps
CPU time 2.23 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201836 kb
Host smart-7ef4195f-7e5e-4478-b273-2f18333ec5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569808303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2569808303
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3937132540
Short name T820
Test name
Test status
Simulation time 4950091438 ps
CPU time 2.51 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201736 kb
Host smart-f4823572-7f7a-4e69-b0d8-8e1428443121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937132540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3937132540
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2853677829
Short name T841
Test name
Test status
Simulation time 416334946 ps
CPU time 1.72 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201520 kb
Host smart-5346b938-9ba6-412b-b701-c171eb806a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853677829 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2853677829
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3278532611
Short name T836
Test name
Test status
Simulation time 539737197 ps
CPU time 0.79 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201368 kb
Host smart-e6365f07-dd45-4ec8-9498-3fc3db80d433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278532611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3278532611
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1852850697
Short name T824
Test name
Test status
Simulation time 2806701896 ps
CPU time 3.61 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:58 PM PDT 24
Peak memory 201748 kb
Host smart-ded271f0-89ae-4d81-89f1-c9dea11ef7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852850697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1852850697
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.955604063
Short name T895
Test name
Test status
Simulation time 619044566 ps
CPU time 3.91 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:59 PM PDT 24
Peak memory 201692 kb
Host smart-825618e1-f50c-4833-b572-a28adfc86ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955604063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.955604063
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3210817367
Short name T900
Test name
Test status
Simulation time 9049360373 ps
CPU time 4.32 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:27:00 PM PDT 24
Peak memory 201696 kb
Host smart-efa82965-0475-4a96-b5ee-3e8534126ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210817367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3210817367
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.396488940
Short name T69
Test name
Test status
Simulation time 446995091 ps
CPU time 0.9 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201504 kb
Host smart-0d853b7b-79cd-43e7-b6dc-575178cc3afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396488940 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.396488940
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3863670945
Short name T119
Test name
Test status
Simulation time 378289176 ps
CPU time 1.52 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:50 PM PDT 24
Peak memory 201392 kb
Host smart-ad008d1c-7194-4c9b-8318-aaa164c95025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863670945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3863670945
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2146845400
Short name T807
Test name
Test status
Simulation time 491531445 ps
CPU time 0.93 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201360 kb
Host smart-8b02ff67-e932-4736-9f1e-89c34ef03394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146845400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2146845400
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.23063983
Short name T48
Test name
Test status
Simulation time 4216334094 ps
CPU time 4.01 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:52 PM PDT 24
Peak memory 201760 kb
Host smart-e99741b5-1d4e-48a5-a58f-04405fe6a1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ct
rl_same_csr_outstanding.23063983
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4192012715
Short name T62
Test name
Test status
Simulation time 388213393 ps
CPU time 3.15 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 209888 kb
Host smart-0ee8307a-dfa4-46a2-bc37-0daf378f63c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192012715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4192012715
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1550684191
Short name T305
Test name
Test status
Simulation time 7565467784 ps
CPU time 19.89 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:27:12 PM PDT 24
Peak memory 201764 kb
Host smart-a421bf71-524c-4448-8616-fad18c9bd414
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550684191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1550684191
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2845870809
Short name T878
Test name
Test status
Simulation time 430765732 ps
CPU time 1.4 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201476 kb
Host smart-6427f8d1-5e47-4dc0-9a23-8f2b11815b07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845870809 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2845870809
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.950000594
Short name T853
Test name
Test status
Simulation time 408918101 ps
CPU time 0.9 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201436 kb
Host smart-4c19b797-667f-490f-8d47-3e7c1b28f828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950000594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.950000594
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2907226049
Short name T909
Test name
Test status
Simulation time 395006966 ps
CPU time 1.52 seconds
Started Jul 17 05:26:47 PM PDT 24
Finished Jul 17 05:26:51 PM PDT 24
Peak memory 201312 kb
Host smart-c8645f93-d6a1-43c9-ac76-25b500da357b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907226049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2907226049
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.53595693
Short name T813
Test name
Test status
Simulation time 3285779599 ps
CPU time 1.75 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:21 PM PDT 24
Peak memory 201784 kb
Host smart-b3fb00e3-ea35-4fbc-b15c-2c407821824a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53595693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ct
rl_same_csr_outstanding.53595693
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2971023782
Short name T891
Test name
Test status
Simulation time 617756430 ps
CPU time 2.26 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201704 kb
Host smart-ba1fd537-cefd-47dc-9cf5-cdddabb8d046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971023782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2971023782
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1259543296
Short name T51
Test name
Test status
Simulation time 5000742592 ps
CPU time 4.5 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:53 PM PDT 24
Peak memory 201784 kb
Host smart-6fff8f53-165b-48c6-a32b-6bca7fff0ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259543296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1259543296
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3046032706
Short name T848
Test name
Test status
Simulation time 509086119 ps
CPU time 1.88 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201428 kb
Host smart-dccd4ae2-b019-4537-b968-c3e21df107c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046032706 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3046032706
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3842599064
Short name T912
Test name
Test status
Simulation time 458037920 ps
CPU time 1.09 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:48 PM PDT 24
Peak memory 201340 kb
Host smart-e229f081-d0cf-4988-9687-a2a0efb787ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842599064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3842599064
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1943212794
Short name T817
Test name
Test status
Simulation time 384027170 ps
CPU time 1.29 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201276 kb
Host smart-7e241c0c-04c5-4990-ac87-d02c00442a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943212794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1943212794
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2801593319
Short name T814
Test name
Test status
Simulation time 3878629908 ps
CPU time 13.09 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:27:05 PM PDT 24
Peak memory 201724 kb
Host smart-72534756-c5e9-4d54-9c6b-7c03c228102a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801593319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2801593319
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1016091236
Short name T55
Test name
Test status
Simulation time 581420081 ps
CPU time 2.49 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201628 kb
Host smart-2a14ce4c-b0f9-4571-b068-3d1ee9847a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016091236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1016091236
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1742613095
Short name T889
Test name
Test status
Simulation time 4295521373 ps
CPU time 11.35 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:31 PM PDT 24
Peak memory 201784 kb
Host smart-5092dc9f-3efb-480f-8504-7a23a2c3978f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742613095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1742613095
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1624731282
Short name T88
Test name
Test status
Simulation time 594230912 ps
CPU time 1.27 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201484 kb
Host smart-5e17496e-8452-4de0-b998-26f7989a63f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624731282 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1624731282
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.581423119
Short name T115
Test name
Test status
Simulation time 428006572 ps
CPU time 1.63 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201420 kb
Host smart-6a26b608-2deb-4589-82ed-55abfc630e38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581423119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.581423119
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1092591847
Short name T826
Test name
Test status
Simulation time 526013947 ps
CPU time 1.64 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201316 kb
Host smart-676a1cc4-3bb1-4872-8320-0247f9d390ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092591847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1092591847
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.883567380
Short name T872
Test name
Test status
Simulation time 4379256384 ps
CPU time 10.46 seconds
Started Jul 17 05:27:34 PM PDT 24
Finished Jul 17 05:27:45 PM PDT 24
Peak memory 201756 kb
Host smart-259a71aa-e581-493c-a842-c88ad51bd234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883567380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.883567380
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2379764358
Short name T866
Test name
Test status
Simulation time 514555824 ps
CPU time 2.6 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201684 kb
Host smart-98fc0871-517c-4a18-addd-ef86f303fd68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379764358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2379764358
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3917782879
Short name T842
Test name
Test status
Simulation time 8265091093 ps
CPU time 9.74 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:27:04 PM PDT 24
Peak memory 201692 kb
Host smart-5c2f2663-bc09-45bc-b65b-6e6b9a11b706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917782879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3917782879
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2599577051
Short name T806
Test name
Test status
Simulation time 592237622 ps
CPU time 1.96 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201488 kb
Host smart-c5bc3853-d46b-4483-8f7d-fe5a68cb3138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599577051 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2599577051
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3455258818
Short name T827
Test name
Test status
Simulation time 605345605 ps
CPU time 0.75 seconds
Started Jul 17 05:26:47 PM PDT 24
Finished Jul 17 05:26:52 PM PDT 24
Peak memory 201392 kb
Host smart-da298617-f80c-4792-9cc8-6314d6eb7f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455258818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3455258818
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1533819053
Short name T805
Test name
Test status
Simulation time 448108361 ps
CPU time 1.6 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201344 kb
Host smart-23f2686a-3463-465a-8efa-f0dc6e0a5bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533819053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1533819053
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2151532616
Short name T124
Test name
Test status
Simulation time 4876324634 ps
CPU time 15.52 seconds
Started Jul 17 05:27:16 PM PDT 24
Finished Jul 17 05:27:33 PM PDT 24
Peak memory 201760 kb
Host smart-92584729-64ce-4ee6-93f2-63bd4e3aee72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151532616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2151532616
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3043670517
Short name T876
Test name
Test status
Simulation time 485690678 ps
CPU time 3.87 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 217624 kb
Host smart-91f11c7e-c82e-4c52-9eb4-1bf0d133d985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043670517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3043670517
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1598633678
Short name T828
Test name
Test status
Simulation time 4393797302 ps
CPU time 11.78 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:27:07 PM PDT 24
Peak memory 201728 kb
Host smart-2400bd8b-1ab2-4094-90fc-df400771ea19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598633678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1598633678
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.121180215
Short name T846
Test name
Test status
Simulation time 593888632 ps
CPU time 1.03 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201492 kb
Host smart-8d69c4ea-5e43-4a94-9a97-2840cf09b09c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121180215 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.121180215
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3103333502
Short name T125
Test name
Test status
Simulation time 515311320 ps
CPU time 1.34 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:53 PM PDT 24
Peak memory 201428 kb
Host smart-155b818f-ad7f-49b9-a786-2a7c782d838d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103333502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3103333502
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3591226541
Short name T882
Test name
Test status
Simulation time 361024837 ps
CPU time 0.8 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201364 kb
Host smart-ac89488d-4644-4292-851c-2a49181d06a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591226541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3591226541
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.882415869
Short name T835
Test name
Test status
Simulation time 5289965153 ps
CPU time 2.48 seconds
Started Jul 17 05:27:19 PM PDT 24
Finished Jul 17 05:27:23 PM PDT 24
Peak memory 201740 kb
Host smart-f7058b20-f81d-4a68-8dc2-5a1cb69a3135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882415869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.882415869
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1987325813
Short name T71
Test name
Test status
Simulation time 514536669 ps
CPU time 2.73 seconds
Started Jul 17 05:27:16 PM PDT 24
Finished Jul 17 05:27:19 PM PDT 24
Peak memory 217948 kb
Host smart-4bfa6070-5cd0-4916-a04b-6ec0676fc88e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987325813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1987325813
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.642010251
Short name T886
Test name
Test status
Simulation time 9174043832 ps
CPU time 5.24 seconds
Started Jul 17 05:27:17 PM PDT 24
Finished Jul 17 05:27:23 PM PDT 24
Peak memory 201812 kb
Host smart-65a42196-f71d-4eb3-8685-3a829e00cfc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642010251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.642010251
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1072922286
Short name T917
Test name
Test status
Simulation time 469939106 ps
CPU time 1.05 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201480 kb
Host smart-e72dfc86-9197-4639-84ef-9b8027a71b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072922286 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1072922286
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3758308982
Short name T839
Test name
Test status
Simulation time 437639158 ps
CPU time 1.81 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:58 PM PDT 24
Peak memory 201372 kb
Host smart-62b11323-b6dc-4767-a091-388c9c3bc959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758308982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3758308982
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2736551844
Short name T859
Test name
Test status
Simulation time 299249408 ps
CPU time 1.39 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201304 kb
Host smart-3a614cf1-986b-41da-a9af-09d1acd139c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736551844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2736551844
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2159799857
Short name T868
Test name
Test status
Simulation time 4488234693 ps
CPU time 4.4 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:58 PM PDT 24
Peak memory 201960 kb
Host smart-6d77ba04-01a1-4aa5-940c-f50651ce53aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159799857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2159799857
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2296678104
Short name T73
Test name
Test status
Simulation time 4406205567 ps
CPU time 4.24 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:59 PM PDT 24
Peak memory 201704 kb
Host smart-24fb7de1-48c5-4b85-9123-9424692e8a06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296678104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2296678104
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.182690959
Short name T815
Test name
Test status
Simulation time 869604479 ps
CPU time 1.1 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201632 kb
Host smart-a21409ab-6b00-4e89-b906-26ad4691f953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182690959 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.182690959
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1845198263
Short name T901
Test name
Test status
Simulation time 332399365 ps
CPU time 1.03 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201408 kb
Host smart-87dcb1af-d7e7-4ea6-89bb-ae8a7ba0ed53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845198263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1845198263
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4004480757
Short name T845
Test name
Test status
Simulation time 329559040 ps
CPU time 1.46 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201340 kb
Host smart-cfd8aeae-df13-487e-aad2-b86030ea3c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004480757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.4004480757
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.68808523
Short name T49
Test name
Test status
Simulation time 2289792986 ps
CPU time 2.23 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201532 kb
Host smart-4955a7d3-9249-4bd1-b012-2e546f3372a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68808523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ct
rl_same_csr_outstanding.68808523
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1765100720
Short name T60
Test name
Test status
Simulation time 470632758 ps
CPU time 1.63 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201884 kb
Host smart-dbeaf73f-b451-4aa3-96b0-ef50384fcbc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765100720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1765100720
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1329029870
Short name T117
Test name
Test status
Simulation time 1320862625 ps
CPU time 4.46 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201664 kb
Host smart-50244675-bb11-4327-9a51-86bd752029db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329029870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1329029870
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4142487998
Short name T116
Test name
Test status
Simulation time 22039160205 ps
CPU time 17.7 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:27:11 PM PDT 24
Peak memory 201732 kb
Host smart-ae48f01b-04a5-40af-91e6-0001a200925e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142487998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4142487998
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.820515680
Short name T905
Test name
Test status
Simulation time 1151456525 ps
CPU time 3.29 seconds
Started Jul 17 05:27:34 PM PDT 24
Finished Jul 17 05:27:37 PM PDT 24
Peak memory 201396 kb
Host smart-b84f0233-aa4b-45c7-a080-c2f482162d69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820515680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.820515680
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3494102158
Short name T854
Test name
Test status
Simulation time 546393150 ps
CPU time 1.97 seconds
Started Jul 17 05:27:15 PM PDT 24
Finished Jul 17 05:27:18 PM PDT 24
Peak memory 201464 kb
Host smart-6687f931-243f-4b85-9e46-fd7724312fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494102158 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3494102158
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.834317867
Short name T110
Test name
Test status
Simulation time 400659369 ps
CPU time 1.23 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:26:46 PM PDT 24
Peak memory 201364 kb
Host smart-35fab6c0-d521-4a66-9ce9-57a60e23e4c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834317867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.834317867
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.516489131
Short name T867
Test name
Test status
Simulation time 449609671 ps
CPU time 1.13 seconds
Started Jul 17 05:26:43 PM PDT 24
Finished Jul 17 05:26:44 PM PDT 24
Peak memory 201308 kb
Host smart-87aed3bd-35c2-47cb-a783-6bd348b6fbe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516489131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.516489131
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4190446806
Short name T903
Test name
Test status
Simulation time 3907003268 ps
CPU time 6.89 seconds
Started Jul 17 05:27:34 PM PDT 24
Finished Jul 17 05:27:41 PM PDT 24
Peak memory 201708 kb
Host smart-10c77e32-3694-40af-9aee-fee8dcd2a7ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190446806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4190446806
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3943885902
Short name T849
Test name
Test status
Simulation time 681697314 ps
CPU time 1.79 seconds
Started Jul 17 05:28:42 PM PDT 24
Finished Jul 17 05:28:44 PM PDT 24
Peak memory 201672 kb
Host smart-f12b223d-63e7-4e23-9fe3-8bd21ccb08e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943885902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3943885902
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1642091196
Short name T53
Test name
Test status
Simulation time 8238352559 ps
CPU time 20.01 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:27:05 PM PDT 24
Peak memory 201804 kb
Host smart-fa8fa9c2-bd05-4946-a7cc-099d57c1bd52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642091196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1642091196
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.548229043
Short name T795
Test name
Test status
Simulation time 347803437 ps
CPU time 0.86 seconds
Started Jul 17 05:27:42 PM PDT 24
Finished Jul 17 05:27:44 PM PDT 24
Peak memory 201308 kb
Host smart-a385b3ac-ddfd-4990-aa12-88b0e1c24bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548229043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.548229043
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.100479461
Short name T800
Test name
Test status
Simulation time 542800154 ps
CPU time 0.98 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:33:57 PM PDT 24
Peak memory 201300 kb
Host smart-06daba08-48f4-471d-9001-9e632a873ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100479461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.100479461
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1988125304
Short name T911
Test name
Test status
Simulation time 465252289 ps
CPU time 0.89 seconds
Started Jul 17 05:29:49 PM PDT 24
Finished Jul 17 05:29:51 PM PDT 24
Peak memory 201348 kb
Host smart-dc3d6619-a76d-43fe-9d0c-df01be285664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988125304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1988125304
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3067544987
Short name T812
Test name
Test status
Simulation time 371568286 ps
CPU time 0.8 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:19 PM PDT 24
Peak memory 201316 kb
Host smart-316fb61b-26ad-4985-b436-8b1f338fb097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067544987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3067544987
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4211716134
Short name T869
Test name
Test status
Simulation time 347533895 ps
CPU time 0.83 seconds
Started Jul 17 05:27:42 PM PDT 24
Finished Jul 17 05:27:43 PM PDT 24
Peak memory 201308 kb
Host smart-c96ddf1e-ccac-4f2e-a121-0e5fd89066c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211716134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4211716134
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1050406044
Short name T898
Test name
Test status
Simulation time 535728024 ps
CPU time 1.02 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 201344 kb
Host smart-460e766f-5344-4622-a94a-1a622fd8b81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050406044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1050406044
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.958966434
Short name T801
Test name
Test status
Simulation time 542157852 ps
CPU time 1.07 seconds
Started Jul 17 05:29:57 PM PDT 24
Finished Jul 17 05:29:59 PM PDT 24
Peak memory 201308 kb
Host smart-19747297-0708-4d85-bfde-06faed9b532e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958966434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.958966434
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1302605442
Short name T821
Test name
Test status
Simulation time 545282824 ps
CPU time 0.96 seconds
Started Jul 17 05:27:36 PM PDT 24
Finished Jul 17 05:27:39 PM PDT 24
Peak memory 201272 kb
Host smart-4f574c36-695a-4970-bd6c-cc00c4814da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302605442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1302605442
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3750856191
Short name T825
Test name
Test status
Simulation time 316648502 ps
CPU time 0.83 seconds
Started Jul 17 05:27:42 PM PDT 24
Finished Jul 17 05:27:43 PM PDT 24
Peak memory 201316 kb
Host smart-4064c5e6-d34e-441b-a021-a0360dfd3b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750856191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3750856191
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.179562483
Short name T810
Test name
Test status
Simulation time 324125068 ps
CPU time 1.42 seconds
Started Jul 17 05:27:42 PM PDT 24
Finished Jul 17 05:27:44 PM PDT 24
Peak memory 201328 kb
Host smart-a582f345-ebf9-449c-b532-b0333c6a207e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179562483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.179562483
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4215810396
Short name T111
Test name
Test status
Simulation time 888760975 ps
CPU time 3.9 seconds
Started Jul 17 05:27:34 PM PDT 24
Finished Jul 17 05:27:38 PM PDT 24
Peak memory 201604 kb
Host smart-37508ec0-9dea-4b6e-84f0-7ecf1fdf04bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215810396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4215810396
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3408384624
Short name T118
Test name
Test status
Simulation time 24641230439 ps
CPU time 17.18 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:27:03 PM PDT 24
Peak memory 201800 kb
Host smart-075b3bc7-8bcb-49ef-bc90-6096568ae866
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408384624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3408384624
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.411467732
Short name T902
Test name
Test status
Simulation time 751010594 ps
CPU time 1.07 seconds
Started Jul 17 05:26:41 PM PDT 24
Finished Jul 17 05:26:43 PM PDT 24
Peak memory 201456 kb
Host smart-d73a81ac-2eb7-4aba-9c12-9b3555d7f73f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411467732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.411467732
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4291350694
Short name T913
Test name
Test status
Simulation time 499224269 ps
CPU time 1.28 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:50 PM PDT 24
Peak memory 209924 kb
Host smart-6989d239-d07f-4874-8866-7208dd3778c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291350694 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4291350694
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2147517873
Short name T916
Test name
Test status
Simulation time 421681423 ps
CPU time 1.16 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201420 kb
Host smart-043b54e7-cf33-404c-b071-e46fe5dbed82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147517873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2147517873
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2028135419
Short name T907
Test name
Test status
Simulation time 369982136 ps
CPU time 1.43 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:26:46 PM PDT 24
Peak memory 201296 kb
Host smart-85445061-7224-42b0-ae8b-19716da5df47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028135419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2028135419
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.630256284
Short name T126
Test name
Test status
Simulation time 2417991289 ps
CPU time 5.79 seconds
Started Jul 17 05:27:24 PM PDT 24
Finished Jul 17 05:27:30 PM PDT 24
Peak memory 201536 kb
Host smart-ab86c48d-6042-4785-a94c-911259fa593f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630256284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.630256284
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1637954340
Short name T871
Test name
Test status
Simulation time 418196714 ps
CPU time 2.88 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:51 PM PDT 24
Peak memory 201716 kb
Host smart-4fe6c786-7102-4cdc-a6f7-a77ccfdcf5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637954340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1637954340
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2660774458
Short name T844
Test name
Test status
Simulation time 8395001543 ps
CPU time 7.53 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201760 kb
Host smart-89ba2575-2e0d-4603-b3ec-ae1a4e6e1e28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660774458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2660774458
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2373356022
Short name T873
Test name
Test status
Simulation time 415228262 ps
CPU time 0.88 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:30:57 PM PDT 24
Peak memory 201348 kb
Host smart-e8244db0-5c6c-46e3-ae43-98117c98060f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373356022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2373356022
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2922182495
Short name T834
Test name
Test status
Simulation time 301353821 ps
CPU time 1.04 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 201368 kb
Host smart-7b9b2126-8223-4119-be3b-ac1e74217bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922182495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2922182495
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1479607980
Short name T803
Test name
Test status
Simulation time 416827910 ps
CPU time 1.11 seconds
Started Jul 17 05:32:43 PM PDT 24
Finished Jul 17 05:32:45 PM PDT 24
Peak memory 201228 kb
Host smart-ead84b9a-8342-41c9-b192-10ae9705feb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479607980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1479607980
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2831704165
Short name T831
Test name
Test status
Simulation time 305234855 ps
CPU time 1.3 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:19 PM PDT 24
Peak memory 201312 kb
Host smart-1cbbfdf7-f417-48d8-96a0-dcaa3e556590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831704165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2831704165
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.318925701
Short name T858
Test name
Test status
Simulation time 381539302 ps
CPU time 1.55 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:33:49 PM PDT 24
Peak memory 201368 kb
Host smart-925583ea-a028-4d06-9756-dedf01d85f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318925701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.318925701
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2874238167
Short name T918
Test name
Test status
Simulation time 475458659 ps
CPU time 0.96 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:33:47 PM PDT 24
Peak memory 201372 kb
Host smart-34a9469e-b29d-4576-b421-569718a318c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874238167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2874238167
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2394284359
Short name T799
Test name
Test status
Simulation time 309753680 ps
CPU time 0.76 seconds
Started Jul 17 05:32:43 PM PDT 24
Finished Jul 17 05:32:44 PM PDT 24
Peak memory 201200 kb
Host smart-2b0420d2-a286-42a5-a814-ab5e404d66a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394284359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2394284359
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.932529913
Short name T862
Test name
Test status
Simulation time 396671421 ps
CPU time 1.47 seconds
Started Jul 17 05:32:11 PM PDT 24
Finished Jul 17 05:32:13 PM PDT 24
Peak memory 201360 kb
Host smart-7441e372-1d06-48e4-baa0-d3dc23f221bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932529913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.932529913
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.382761429
Short name T796
Test name
Test status
Simulation time 439583477 ps
CPU time 1.1 seconds
Started Jul 17 05:29:06 PM PDT 24
Finished Jul 17 05:29:08 PM PDT 24
Peak memory 201292 kb
Host smart-66244b6c-69e9-4863-91c6-a812c27fce62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382761429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.382761429
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1027478273
Short name T888
Test name
Test status
Simulation time 423726611 ps
CPU time 0.88 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:30:57 PM PDT 24
Peak memory 201348 kb
Host smart-95928d68-6ec1-4275-9372-c1c57b13ad33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027478273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1027478273
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2438488825
Short name T818
Test name
Test status
Simulation time 915240091 ps
CPU time 3.47 seconds
Started Jul 17 05:26:44 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201548 kb
Host smart-4853cd5c-b9cb-4ce5-aadd-52d59d297660
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438488825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2438488825
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1375099555
Short name T47
Test name
Test status
Simulation time 17317284370 ps
CPU time 58.1 seconds
Started Jul 17 05:26:47 PM PDT 24
Finished Jul 17 05:27:47 PM PDT 24
Peak memory 201760 kb
Host smart-e526b95c-87b6-49c1-8ec1-0a1c6aa94f41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375099555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1375099555
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1897786376
Short name T906
Test name
Test status
Simulation time 1042497275 ps
CPU time 2.96 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:51 PM PDT 24
Peak memory 201388 kb
Host smart-705a1d7e-05a4-493c-90a6-7c3cbaa00da1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897786376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1897786376
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3198060838
Short name T865
Test name
Test status
Simulation time 668031719 ps
CPU time 1.48 seconds
Started Jul 17 05:26:42 PM PDT 24
Finished Jul 17 05:26:45 PM PDT 24
Peak memory 209892 kb
Host smart-8c93f1b6-501a-4adf-bad4-0f348742a9f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198060838 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3198060838
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2133789723
Short name T910
Test name
Test status
Simulation time 509215472 ps
CPU time 0.86 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201444 kb
Host smart-0d7cc4ed-5a6b-4861-9f16-9102821a332b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133789723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2133789723
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.365141454
Short name T851
Test name
Test status
Simulation time 425733822 ps
CPU time 1.16 seconds
Started Jul 17 05:27:14 PM PDT 24
Finished Jul 17 05:27:16 PM PDT 24
Peak memory 201272 kb
Host smart-e8a007ed-740b-4434-9250-a91cc6bc9694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365141454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.365141454
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1573024854
Short name T816
Test name
Test status
Simulation time 4253304989 ps
CPU time 7.93 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 201800 kb
Host smart-bc58c92d-057b-4228-aa8b-e29bde4175fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573024854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1573024854
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.747334837
Short name T864
Test name
Test status
Simulation time 701899953 ps
CPU time 1.84 seconds
Started Jul 17 05:26:41 PM PDT 24
Finished Jul 17 05:26:43 PM PDT 24
Peak memory 201704 kb
Host smart-6220d4a3-5ad6-41ff-be8c-0186b77f2dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747334837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.747334837
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2212065129
Short name T885
Test name
Test status
Simulation time 8162454099 ps
CPU time 20.11 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:27:09 PM PDT 24
Peak memory 201760 kb
Host smart-e840126a-8059-4a54-8839-8d4b2527b7ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212065129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2212065129
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2594382913
Short name T863
Test name
Test status
Simulation time 291840268 ps
CPU time 1.14 seconds
Started Jul 17 05:27:34 PM PDT 24
Finished Jul 17 05:27:36 PM PDT 24
Peak memory 201312 kb
Host smart-2d74b643-63eb-44a9-b324-c31a149eff8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594382913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2594382913
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.251195812
Short name T802
Test name
Test status
Simulation time 515525222 ps
CPU time 1.71 seconds
Started Jul 17 05:29:57 PM PDT 24
Finished Jul 17 05:30:00 PM PDT 24
Peak memory 201312 kb
Host smart-ff510cf8-ed21-43c0-8ef2-e2fd14406c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251195812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.251195812
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1243969185
Short name T880
Test name
Test status
Simulation time 531187627 ps
CPU time 0.93 seconds
Started Jul 17 05:27:39 PM PDT 24
Finished Jul 17 05:27:41 PM PDT 24
Peak memory 201284 kb
Host smart-133349cb-2c04-41ff-9d23-d97fa2c2b5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243969185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1243969185
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3924106631
Short name T890
Test name
Test status
Simulation time 510129613 ps
CPU time 1.78 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:27:49 PM PDT 24
Peak memory 201368 kb
Host smart-eacf46e7-199d-4381-ba21-a0075f290c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924106631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3924106631
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2597583461
Short name T856
Test name
Test status
Simulation time 449220560 ps
CPU time 1.56 seconds
Started Jul 17 05:30:24 PM PDT 24
Finished Jul 17 05:30:26 PM PDT 24
Peak memory 201332 kb
Host smart-ff5e567d-d0ce-48ee-a744-7334a0bbb343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597583461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2597583461
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.271522697
Short name T892
Test name
Test status
Simulation time 466688890 ps
CPU time 0.88 seconds
Started Jul 17 05:27:37 PM PDT 24
Finished Jul 17 05:27:39 PM PDT 24
Peak memory 201364 kb
Host smart-40ce23e8-4fe3-4953-a1b4-7a6ec277648b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271522697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.271522697
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3131507913
Short name T797
Test name
Test status
Simulation time 435883675 ps
CPU time 0.95 seconds
Started Jul 17 05:27:39 PM PDT 24
Finished Jul 17 05:27:41 PM PDT 24
Peak memory 201344 kb
Host smart-af5038c2-b81a-442a-98e7-16f6b8d44a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131507913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3131507913
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3636858295
Short name T832
Test name
Test status
Simulation time 353109252 ps
CPU time 0.87 seconds
Started Jul 17 05:27:42 PM PDT 24
Finished Jul 17 05:27:43 PM PDT 24
Peak memory 201304 kb
Host smart-e6a1171c-3ce5-4b61-939a-cef96d2fa5cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636858295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3636858295
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.464929712
Short name T897
Test name
Test status
Simulation time 400396561 ps
CPU time 0.87 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 201368 kb
Host smart-6ec58ab0-ef64-4566-80f8-56135d287791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464929712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.464929712
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4040989476
Short name T881
Test name
Test status
Simulation time 471330282 ps
CPU time 1.75 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:27:47 PM PDT 24
Peak memory 201308 kb
Host smart-60642bf4-4db4-4081-938d-57083a1d4470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040989476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4040989476
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.35359511
Short name T87
Test name
Test status
Simulation time 604761921 ps
CPU time 1.14 seconds
Started Jul 17 05:26:45 PM PDT 24
Finished Jul 17 05:26:47 PM PDT 24
Peak memory 201428 kb
Host smart-0c0607ab-9557-499d-baeb-239f5635cf56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359511 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.35359511
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1924911522
Short name T875
Test name
Test status
Simulation time 361346139 ps
CPU time 1.52 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201420 kb
Host smart-d9573ae9-1edf-49fd-848e-6e148906ec2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924911522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1924911522
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2940153437
Short name T830
Test name
Test status
Simulation time 482987826 ps
CPU time 0.72 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:20 PM PDT 24
Peak memory 201368 kb
Host smart-7db59a13-8520-4fc0-867e-bbecdd1d16e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940153437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2940153437
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1720940690
Short name T122
Test name
Test status
Simulation time 2462719999 ps
CPU time 3.02 seconds
Started Jul 17 05:28:42 PM PDT 24
Finished Jul 17 05:28:45 PM PDT 24
Peak memory 201568 kb
Host smart-fb31f150-96fa-4c25-9812-2ea089d52880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720940690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1720940690
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2152911722
Short name T914
Test name
Test status
Simulation time 1319479175 ps
CPU time 1.56 seconds
Started Jul 17 05:26:46 PM PDT 24
Finished Jul 17 05:26:49 PM PDT 24
Peak memory 201640 kb
Host smart-11e90cf2-537e-4600-a80e-cec3dedc99a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152911722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2152911722
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.137122408
Short name T809
Test name
Test status
Simulation time 647516649 ps
CPU time 2.43 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201480 kb
Host smart-4096dd25-5418-4712-b144-927b37d4e168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137122408 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.137122408
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.564571822
Short name T857
Test name
Test status
Simulation time 460323939 ps
CPU time 1.5 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201392 kb
Host smart-f5bbccd5-9e1a-40d3-b129-702f69d0b34c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564571822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.564571822
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3556885278
Short name T893
Test name
Test status
Simulation time 499747696 ps
CPU time 0.9 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201316 kb
Host smart-62ce7c03-92b7-4b85-ae58-4038ad7399c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556885278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3556885278
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3256955284
Short name T819
Test name
Test status
Simulation time 2009704059 ps
CPU time 1.33 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201332 kb
Host smart-6271d9b8-ac80-4b4f-89fe-3c42aa218e8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256955284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3256955284
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2293924936
Short name T847
Test name
Test status
Simulation time 353062309 ps
CPU time 2.26 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 201624 kb
Host smart-76042c60-109c-47ed-a2f2-ae2c524a8ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293924936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2293924936
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3854230391
Short name T843
Test name
Test status
Simulation time 7616039463 ps
CPU time 9.63 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:27:02 PM PDT 24
Peak memory 201668 kb
Host smart-28238216-2dcc-4f59-8919-28070340e57f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854230391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3854230391
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2316737640
Short name T879
Test name
Test status
Simulation time 464750773 ps
CPU time 1.55 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:21 PM PDT 24
Peak memory 201480 kb
Host smart-dd2c2269-5e0b-48c4-8922-392535b6c3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316737640 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2316737640
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1247613619
Short name T121
Test name
Test status
Simulation time 468370317 ps
CPU time 1.8 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201420 kb
Host smart-df4f67a9-e774-45f9-a3ec-77231038aad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247613619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1247613619
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.379187237
Short name T840
Test name
Test status
Simulation time 350287523 ps
CPU time 1.43 seconds
Started Jul 17 05:26:47 PM PDT 24
Finished Jul 17 05:26:53 PM PDT 24
Peak memory 201348 kb
Host smart-bc68bed2-c373-44c0-adcb-8bae1f729a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379187237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.379187237
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.787594879
Short name T838
Test name
Test status
Simulation time 1865542931 ps
CPU time 7.82 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:27:02 PM PDT 24
Peak memory 201420 kb
Host smart-3811215a-ec5c-496e-8e4b-9ada7e17dc9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787594879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.787594879
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.231342461
Short name T850
Test name
Test status
Simulation time 453572467 ps
CPU time 2.81 seconds
Started Jul 17 05:27:34 PM PDT 24
Finished Jul 17 05:27:38 PM PDT 24
Peak memory 218000 kb
Host smart-93fb4539-dcc3-49be-80a4-8d222c9c0c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231342461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.231342461
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4280283324
Short name T883
Test name
Test status
Simulation time 4477116487 ps
CPU time 12.62 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:27:06 PM PDT 24
Peak memory 201728 kb
Host smart-4daf7ae2-1684-4dcb-a151-45c94ccf9351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280283324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4280283324
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.613087261
Short name T822
Test name
Test status
Simulation time 472881997 ps
CPU time 1.39 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:20 PM PDT 24
Peak memory 201480 kb
Host smart-6fc849a0-b0d8-44da-be5e-de9d88e91191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613087261 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.613087261
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3273933034
Short name T114
Test name
Test status
Simulation time 544723433 ps
CPU time 2.05 seconds
Started Jul 17 05:27:17 PM PDT 24
Finished Jul 17 05:27:20 PM PDT 24
Peak memory 201424 kb
Host smart-fe6f2fa9-37c4-40d8-8c3c-afdfc99d9807
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273933034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3273933034
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1772740212
Short name T798
Test name
Test status
Simulation time 362126165 ps
CPU time 1.47 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:21 PM PDT 24
Peak memory 201220 kb
Host smart-aa009415-8652-4bfe-8a20-83323fbcbc48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772740212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1772740212
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3611140845
Short name T852
Test name
Test status
Simulation time 2378730172 ps
CPU time 5.82 seconds
Started Jul 17 05:27:19 PM PDT 24
Finished Jul 17 05:27:26 PM PDT 24
Peak memory 201544 kb
Host smart-c28ac7a5-2d9e-4406-a932-892b1ec516f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611140845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3611140845
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3457518735
Short name T306
Test name
Test status
Simulation time 4526173695 ps
CPU time 12.11 seconds
Started Jul 17 05:27:18 PM PDT 24
Finished Jul 17 05:27:31 PM PDT 24
Peak memory 201780 kb
Host smart-b20cb4ed-d0b9-4f26-8359-cf2c30becfbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457518735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3457518735
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4064445247
Short name T804
Test name
Test status
Simulation time 717311275 ps
CPU time 1.05 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 201464 kb
Host smart-1680a556-cbea-4f47-8ffb-2a031dff13aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064445247 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4064445247
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3548956783
Short name T120
Test name
Test status
Simulation time 447624438 ps
CPU time 0.99 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201420 kb
Host smart-d72f6fcd-e41c-4c8c-9354-85dbf55445a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548956783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3548956783
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3129068379
Short name T877
Test name
Test status
Simulation time 293646001 ps
CPU time 0.85 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:26:53 PM PDT 24
Peak memory 201368 kb
Host smart-4f75038e-cef8-4065-b5e6-6202ce535758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129068379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3129068379
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1804439071
Short name T861
Test name
Test status
Simulation time 4595740608 ps
CPU time 6.81 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:27:03 PM PDT 24
Peak memory 201728 kb
Host smart-9b12386f-171c-48e9-af4e-b957f40404b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804439071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1804439071
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2596732382
Short name T61
Test name
Test status
Simulation time 478044482 ps
CPU time 2.29 seconds
Started Jul 17 05:26:47 PM PDT 24
Finished Jul 17 05:26:54 PM PDT 24
Peak memory 201740 kb
Host smart-e9dc9e3e-7f0c-468f-bf74-3402008f5681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596732382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2596732382
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3017147084
Short name T52
Test name
Test status
Simulation time 8598174839 ps
CPU time 7.1 seconds
Started Jul 17 05:26:48 PM PDT 24
Finished Jul 17 05:27:00 PM PDT 24
Peak memory 201756 kb
Host smart-77943686-06a6-47b8-a2a1-8c4bec6280da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017147084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3017147084
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.59164997
Short name T631
Test name
Test status
Simulation time 512043866 ps
CPU time 1.18 seconds
Started Jul 17 05:33:42 PM PDT 24
Finished Jul 17 05:33:45 PM PDT 24
Peak memory 201272 kb
Host smart-8b0d11d1-075c-4bd4-85b5-f6cbf88f19aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59164997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.59164997
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4021640224
Short name T213
Test name
Test status
Simulation time 160791153708 ps
CPU time 37.26 seconds
Started Jul 17 05:31:36 PM PDT 24
Finished Jul 17 05:32:14 PM PDT 24
Peak memory 201536 kb
Host smart-3a2709c3-75ab-4500-9788-7d628e555afa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021640224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4021640224
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1220409104
Short name T176
Test name
Test status
Simulation time 396544218451 ps
CPU time 214.99 seconds
Started Jul 17 05:31:30 PM PDT 24
Finished Jul 17 05:35:07 PM PDT 24
Peak memory 201552 kb
Host smart-d676ceea-5b2f-4674-b315-4778f5cbef3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220409104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1220409104
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1400117793
Short name T304
Test name
Test status
Simulation time 324594508624 ps
CPU time 728.6 seconds
Started Jul 17 05:31:40 PM PDT 24
Finished Jul 17 05:43:50 PM PDT 24
Peak memory 201532 kb
Host smart-4f39eea5-07d1-4a2e-a97b-6e9f8294d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400117793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1400117793
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2401245902
Short name T330
Test name
Test status
Simulation time 338243430977 ps
CPU time 207.1 seconds
Started Jul 17 05:31:31 PM PDT 24
Finished Jul 17 05:35:00 PM PDT 24
Peak memory 201480 kb
Host smart-a71ab8e3-9d25-4c93-b775-6d7789371b70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401245902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2401245902
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1786813455
Short name T140
Test name
Test status
Simulation time 488466595791 ps
CPU time 553.7 seconds
Started Jul 17 05:32:36 PM PDT 24
Finished Jul 17 05:41:51 PM PDT 24
Peak memory 201540 kb
Host smart-ab1d0620-bc15-4ab5-b8b3-c2a06b4c2613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786813455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1786813455
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2066090646
Short name T403
Test name
Test status
Simulation time 480845277428 ps
CPU time 1133.44 seconds
Started Jul 17 05:31:36 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 201536 kb
Host smart-d16e7a21-ccba-4330-93db-c588a585b676
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066090646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2066090646
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4058582696
Short name T509
Test name
Test status
Simulation time 198335799282 ps
CPU time 201.13 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:35:59 PM PDT 24
Peak memory 201516 kb
Host smart-deab22ee-32fe-4d93-b265-4147ce90fe34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058582696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4058582696
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2455529010
Short name T568
Test name
Test status
Simulation time 110475558998 ps
CPU time 569.54 seconds
Started Jul 17 05:33:38 PM PDT 24
Finished Jul 17 05:43:08 PM PDT 24
Peak memory 201976 kb
Host smart-ab26a0a8-747c-4569-8efd-89541b8e5bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455529010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2455529010
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.70100547
Short name T612
Test name
Test status
Simulation time 25171988225 ps
CPU time 4.13 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:41 PM PDT 24
Peak memory 201340 kb
Host smart-a4aa1293-1552-42df-99b0-40bae925dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70100547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.70100547
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3297602789
Short name T654
Test name
Test status
Simulation time 3673696840 ps
CPU time 3.11 seconds
Started Jul 17 05:31:37 PM PDT 24
Finished Jul 17 05:31:41 PM PDT 24
Peak memory 201336 kb
Host smart-9d52361d-eff0-4b19-b265-6715103f29b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297602789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3297602789
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1232434714
Short name T702
Test name
Test status
Simulation time 5957360072 ps
CPU time 3.93 seconds
Started Jul 17 05:31:36 PM PDT 24
Finished Jul 17 05:31:41 PM PDT 24
Peak memory 201352 kb
Host smart-d665d88d-6472-4392-897d-fbac438990a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232434714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1232434714
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2078542060
Short name T578
Test name
Test status
Simulation time 122003322336 ps
CPU time 465.82 seconds
Started Jul 17 05:31:33 PM PDT 24
Finished Jul 17 05:39:20 PM PDT 24
Peak memory 202072 kb
Host smart-a9315b60-9d52-4814-86a0-ea521f21a561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078542060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2078542060
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2171287933
Short name T243
Test name
Test status
Simulation time 205005433085 ps
CPU time 117.85 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:35:38 PM PDT 24
Peak memory 216280 kb
Host smart-5e25ea3f-e856-4902-b1cc-b94c30407115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171287933 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2171287933
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2644086231
Short name T719
Test name
Test status
Simulation time 394232256 ps
CPU time 1.12 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:31:44 PM PDT 24
Peak memory 201196 kb
Host smart-e6ae16e5-3e77-4527-87ec-3944a42cd809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644086231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2644086231
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2570901227
Short name T623
Test name
Test status
Simulation time 167699335271 ps
CPU time 364.88 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:37:47 PM PDT 24
Peak memory 201496 kb
Host smart-8287307e-3920-4064-bfb4-bda37ddf3b06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570901227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2570901227
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1988601632
Short name T2
Test name
Test status
Simulation time 160941106805 ps
CPU time 190.07 seconds
Started Jul 17 05:31:39 PM PDT 24
Finished Jul 17 05:34:51 PM PDT 24
Peak memory 201532 kb
Host smart-d6bd72a3-3bc7-4de0-a304-960fe7c168e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988601632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1988601632
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1361090212
Short name T632
Test name
Test status
Simulation time 330212481482 ps
CPU time 802.59 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:45:04 PM PDT 24
Peak memory 201444 kb
Host smart-20b835ec-b068-46a4-87fd-ecedc9d16620
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361090212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1361090212
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3336649618
Short name T368
Test name
Test status
Simulation time 329761070213 ps
CPU time 194.31 seconds
Started Jul 17 05:31:39 PM PDT 24
Finished Jul 17 05:34:54 PM PDT 24
Peak memory 201560 kb
Host smart-57fba041-f226-470f-9b9d-9aef9f5e780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336649618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3336649618
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.566755020
Short name T642
Test name
Test status
Simulation time 164341435667 ps
CPU time 337.64 seconds
Started Jul 17 05:31:40 PM PDT 24
Finished Jul 17 05:37:19 PM PDT 24
Peak memory 201516 kb
Host smart-8c8801e8-b144-4adc-b42d-0b9089e1169b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=566755020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.566755020
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.573829937
Short name T13
Test name
Test status
Simulation time 179770333851 ps
CPU time 220.51 seconds
Started Jul 17 05:31:38 PM PDT 24
Finished Jul 17 05:35:19 PM PDT 24
Peak memory 201468 kb
Host smart-c92e5cde-5e1d-4109-8418-90f5e67be069
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573829937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.573829937
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2919497034
Short name T92
Test name
Test status
Simulation time 199365356829 ps
CPU time 107.48 seconds
Started Jul 17 05:31:43 PM PDT 24
Finished Jul 17 05:33:31 PM PDT 24
Peak memory 201460 kb
Host smart-09f597f9-1fe6-4ccf-93b6-d14c0b26d413
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919497034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2919497034
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3848257252
Short name T308
Test name
Test status
Simulation time 104456393312 ps
CPU time 577.94 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:43:19 PM PDT 24
Peak memory 201868 kb
Host smart-f938c05f-5f42-4c06-baef-95685946a5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848257252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3848257252
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4263112008
Short name T369
Test name
Test status
Simulation time 36054386413 ps
CPU time 44.52 seconds
Started Jul 17 05:31:43 PM PDT 24
Finished Jul 17 05:32:28 PM PDT 24
Peak memory 201272 kb
Host smart-88ecddb1-77b9-42ae-a9e1-18c3117c3411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263112008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4263112008
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3730604693
Short name T436
Test name
Test status
Simulation time 5193550449 ps
CPU time 3.84 seconds
Started Jul 17 05:31:39 PM PDT 24
Finished Jul 17 05:31:44 PM PDT 24
Peak memory 201324 kb
Host smart-bcbed273-e979-4167-a62b-c79161c8130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730604693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3730604693
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4265202843
Short name T74
Test name
Test status
Simulation time 4312343602 ps
CPU time 5.71 seconds
Started Jul 17 05:31:42 PM PDT 24
Finished Jul 17 05:31:49 PM PDT 24
Peak memory 217348 kb
Host smart-857d322f-bf54-4db7-a7f8-c35e85059d3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265202843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4265202843
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.911625259
Short name T372
Test name
Test status
Simulation time 5907075167 ps
CPU time 14.02 seconds
Started Jul 17 05:31:40 PM PDT 24
Finished Jul 17 05:31:55 PM PDT 24
Peak memory 201284 kb
Host smart-1736d86a-6cae-4124-bc4a-758bae042935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911625259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.911625259
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.792647743
Short name T269
Test name
Test status
Simulation time 63772249730 ps
CPU time 88.24 seconds
Started Jul 17 05:31:40 PM PDT 24
Finished Jul 17 05:33:10 PM PDT 24
Peak memory 210224 kb
Host smart-aeedb09e-2db3-4529-b5d2-e719caf638d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792647743 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.792647743
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3966916282
Short name T514
Test name
Test status
Simulation time 396052839 ps
CPU time 0.78 seconds
Started Jul 17 05:33:13 PM PDT 24
Finished Jul 17 05:33:15 PM PDT 24
Peak memory 201276 kb
Host smart-1ca3256d-88ff-44bd-b586-156cc20ade6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966916282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3966916282
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2376057467
Short name T666
Test name
Test status
Simulation time 164788076641 ps
CPU time 118.95 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:35:56 PM PDT 24
Peak memory 201536 kb
Host smart-bc2cc359-adbb-40f1-9954-79ed7d202869
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376057467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2376057467
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3120985295
Short name T198
Test name
Test status
Simulation time 353956770128 ps
CPU time 861.53 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:48:35 PM PDT 24
Peak memory 201552 kb
Host smart-429613f0-bd71-4915-8afa-e63b8c08c94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120985295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3120985295
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3472346366
Short name T522
Test name
Test status
Simulation time 163524713769 ps
CPU time 93.8 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:35:47 PM PDT 24
Peak memory 201544 kb
Host smart-2c66d508-b90f-4e40-8c3f-67a76c5bc914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472346366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3472346366
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3131582058
Short name T412
Test name
Test status
Simulation time 166363994411 ps
CPU time 195.35 seconds
Started Jul 17 05:33:10 PM PDT 24
Finished Jul 17 05:36:26 PM PDT 24
Peak memory 201260 kb
Host smart-36feead2-3c09-4269-8f07-422f93352474
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131582058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3131582058
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1002686568
Short name T286
Test name
Test status
Simulation time 162587083665 ps
CPU time 101.15 seconds
Started Jul 17 05:32:57 PM PDT 24
Finished Jul 17 05:34:40 PM PDT 24
Peak memory 201536 kb
Host smart-101c83d6-4539-4b07-b281-462908a56e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002686568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1002686568
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3335909813
Short name T794
Test name
Test status
Simulation time 165959026717 ps
CPU time 100.16 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:34:37 PM PDT 24
Peak memory 201500 kb
Host smart-49ce0ab6-0c5f-4a02-b420-6234f1883b37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335909813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3335909813
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2946405961
Short name T755
Test name
Test status
Simulation time 473846452653 ps
CPU time 88.56 seconds
Started Jul 17 05:33:08 PM PDT 24
Finished Jul 17 05:34:37 PM PDT 24
Peak memory 201540 kb
Host smart-ef760392-de2d-49c7-b89d-dd8f43f5fccb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946405961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2946405961
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2309595148
Short name T433
Test name
Test status
Simulation time 200166916601 ps
CPU time 114.15 seconds
Started Jul 17 05:33:13 PM PDT 24
Finished Jul 17 05:35:08 PM PDT 24
Peak memory 201516 kb
Host smart-68d0b098-b000-4c28-98e3-0ec60322a39b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309595148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2309595148
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1415432919
Short name T583
Test name
Test status
Simulation time 109428492347 ps
CPU time 584.81 seconds
Started Jul 17 05:33:09 PM PDT 24
Finished Jul 17 05:42:55 PM PDT 24
Peak memory 201924 kb
Host smart-422265bf-6c61-46a5-9ab6-f649c49e4400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415432919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1415432919
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1680158808
Short name T681
Test name
Test status
Simulation time 45037257842 ps
CPU time 110.7 seconds
Started Jul 17 05:33:14 PM PDT 24
Finished Jul 17 05:35:06 PM PDT 24
Peak memory 201332 kb
Host smart-ffcda1c5-5565-462c-977b-06d9c6fa1141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680158808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1680158808
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.730663971
Short name T716
Test name
Test status
Simulation time 4979071771 ps
CPU time 6.37 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:33:18 PM PDT 24
Peak memory 201260 kb
Host smart-6e5cb995-1014-417e-99cb-a5dee6937d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730663971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.730663971
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3662568679
Short name T603
Test name
Test status
Simulation time 5656072312 ps
CPU time 6.82 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:33:05 PM PDT 24
Peak memory 201344 kb
Host smart-92014d5b-5fd5-4537-ae28-efb281a252f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662568679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3662568679
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2760590212
Short name T228
Test name
Test status
Simulation time 115679240798 ps
CPU time 141.51 seconds
Started Jul 17 05:33:10 PM PDT 24
Finished Jul 17 05:35:32 PM PDT 24
Peak memory 217772 kb
Host smart-469f6882-3d41-4295-8975-dfaffb3963e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760590212 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2760590212
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4077119925
Short name T748
Test name
Test status
Simulation time 336060205 ps
CPU time 1.01 seconds
Started Jul 17 05:33:21 PM PDT 24
Finished Jul 17 05:33:23 PM PDT 24
Peak memory 201276 kb
Host smart-3df96066-d042-4bf4-8d21-f059eb7ffaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077119925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4077119925
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.551952145
Short name T211
Test name
Test status
Simulation time 510207142683 ps
CPU time 944.55 seconds
Started Jul 17 05:33:14 PM PDT 24
Finished Jul 17 05:48:59 PM PDT 24
Peak memory 201528 kb
Host smart-0d55ea56-efc2-408d-af66-9f3a45767974
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551952145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.551952145
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4290958281
Short name T83
Test name
Test status
Simulation time 161472581688 ps
CPU time 183.65 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:36:16 PM PDT 24
Peak memory 201468 kb
Host smart-196ad48f-461b-4e84-a17a-0ed971a0a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290958281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4290958281
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.50117972
Short name T363
Test name
Test status
Simulation time 328556818352 ps
CPU time 791 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 201516 kb
Host smart-c4a836a4-b47b-4839-9942-d80ebe51bd85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=50117972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt
_fixed.50117972
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1267826753
Short name T477
Test name
Test status
Simulation time 329293430033 ps
CPU time 683.46 seconds
Started Jul 17 05:33:13 PM PDT 24
Finished Jul 17 05:44:37 PM PDT 24
Peak memory 201572 kb
Host smart-8ff3f29d-3a95-44d6-8f34-6d849c9139a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267826753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1267826753
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1517369117
Short name T695
Test name
Test status
Simulation time 184141022725 ps
CPU time 108.58 seconds
Started Jul 17 05:33:14 PM PDT 24
Finished Jul 17 05:35:03 PM PDT 24
Peak memory 201536 kb
Host smart-08b7fc02-ce35-4650-8a9d-24fea6385266
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517369117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1517369117
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3446889763
Short name T562
Test name
Test status
Simulation time 601693988241 ps
CPU time 1288.42 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:55:25 PM PDT 24
Peak memory 201504 kb
Host smart-270b6199-78a2-415c-afcf-593da7d7cf0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446889763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3446889763
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3616239925
Short name T309
Test name
Test status
Simulation time 88119437180 ps
CPU time 285.45 seconds
Started Jul 17 05:33:25 PM PDT 24
Finished Jul 17 05:38:11 PM PDT 24
Peak memory 201948 kb
Host smart-828c6c5d-9190-47ad-9fb9-c2aeb2b0610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616239925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3616239925
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.955988990
Short name T470
Test name
Test status
Simulation time 31062366726 ps
CPU time 36.43 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:33:48 PM PDT 24
Peak memory 201264 kb
Host smart-9fc1c168-742f-48fd-8238-007232420db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955988990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.955988990
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.402655546
Short name T542
Test name
Test status
Simulation time 5409441322 ps
CPU time 4.21 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:00 PM PDT 24
Peak memory 201328 kb
Host smart-4e96c6b6-4e7c-4fa2-9b68-ca084f3eba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402655546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.402655546
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3603450440
Short name T569
Test name
Test status
Simulation time 6014689061 ps
CPU time 7.33 seconds
Started Jul 17 05:33:09 PM PDT 24
Finished Jul 17 05:33:18 PM PDT 24
Peak memory 201272 kb
Host smart-b5ac57cd-4669-4c4c-b658-ad191733d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603450440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3603450440
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.401614512
Short name T423
Test name
Test status
Simulation time 458558746 ps
CPU time 1.67 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:34:13 PM PDT 24
Peak memory 201164 kb
Host smart-2c66146e-9994-4ba1-bcc8-467ba8922847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401614512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.401614512
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2203350284
Short name T708
Test name
Test status
Simulation time 591323978697 ps
CPU time 306.81 seconds
Started Jul 17 05:33:23 PM PDT 24
Finished Jul 17 05:38:30 PM PDT 24
Peak memory 201532 kb
Host smart-b575b6d6-16ae-4037-aed0-461a195e7b91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203350284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2203350284
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1355557434
Short name T166
Test name
Test status
Simulation time 492773601033 ps
CPU time 305.58 seconds
Started Jul 17 05:33:22 PM PDT 24
Finished Jul 17 05:38:28 PM PDT 24
Peak memory 201712 kb
Host smart-ae8f1cea-5172-4e01-82f9-aa3225d89074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355557434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1355557434
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4273975535
Short name T736
Test name
Test status
Simulation time 332307473344 ps
CPU time 175.74 seconds
Started Jul 17 05:33:24 PM PDT 24
Finished Jul 17 05:36:21 PM PDT 24
Peak memory 201516 kb
Host smart-01aa850c-1665-4168-998f-d8f2ea5271d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273975535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4273975535
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1616806970
Short name T519
Test name
Test status
Simulation time 326110834211 ps
CPU time 182.88 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:37:16 PM PDT 24
Peak memory 201608 kb
Host smart-73cb6b19-2afe-4fae-80e0-8a522cd421c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616806970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1616806970
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2968554010
Short name T513
Test name
Test status
Simulation time 484173518898 ps
CPU time 537.65 seconds
Started Jul 17 05:33:22 PM PDT 24
Finished Jul 17 05:42:21 PM PDT 24
Peak memory 201512 kb
Host smart-946fbeca-f067-4676-a0c8-84ea8b593db0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968554010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2968554010
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2267888098
Short name T248
Test name
Test status
Simulation time 495684522850 ps
CPU time 1070.82 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:52:00 PM PDT 24
Peak memory 201560 kb
Host smart-c1f71ea4-ecfe-451d-ad22-496dcd0a6d8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267888098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2267888098
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.910788176
Short name T686
Test name
Test status
Simulation time 576202248861 ps
CPU time 1258.79 seconds
Started Jul 17 05:34:00 PM PDT 24
Finished Jul 17 05:55:00 PM PDT 24
Peak memory 201580 kb
Host smart-ffffd509-aa7a-4895-a853-66de353a368d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910788176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.910788176
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3082462773
Short name T601
Test name
Test status
Simulation time 101966582674 ps
CPU time 536.22 seconds
Started Jul 17 05:34:01 PM PDT 24
Finished Jul 17 05:42:58 PM PDT 24
Peak memory 201976 kb
Host smart-b1d2a23c-7aa4-4938-99ea-3af707262ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082462773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3082462773
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1781747051
Short name T481
Test name
Test status
Simulation time 26614688977 ps
CPU time 61.87 seconds
Started Jul 17 05:33:21 PM PDT 24
Finished Jul 17 05:34:24 PM PDT 24
Peak memory 201260 kb
Host smart-187bf19d-afe1-4a13-96e9-3784c5d72a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781747051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1781747051
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1385260242
Short name T388
Test name
Test status
Simulation time 2927207353 ps
CPU time 2.25 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:34:13 PM PDT 24
Peak memory 201200 kb
Host smart-eed82325-2f5a-4625-b470-2db113045d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385260242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1385260242
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3199561048
Short name T742
Test name
Test status
Simulation time 5844196035 ps
CPU time 5.68 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:34:14 PM PDT 24
Peak memory 201300 kb
Host smart-7f8a2bae-cf12-46a3-82c4-f3fbc07bafad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199561048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3199561048
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3700760639
Short name T45
Test name
Test status
Simulation time 86617828817 ps
CPU time 416.24 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:41:10 PM PDT 24
Peak memory 209992 kb
Host smart-33e0b4c6-4664-4ec7-b08e-b31733ecf5f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700760639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3700760639
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3712609500
Short name T559
Test name
Test status
Simulation time 1284405690765 ps
CPU time 263.04 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:38:37 PM PDT 24
Peak memory 202244 kb
Host smart-9e9cd760-9228-42ea-aa58-cf584b9ccfeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712609500 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3712609500
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1166386957
Short name T586
Test name
Test status
Simulation time 444713554 ps
CPU time 1.6 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:07 PM PDT 24
Peak memory 201252 kb
Host smart-76948660-942c-4db5-bfa7-b850f38472e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166386957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1166386957
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3088359033
Short name T697
Test name
Test status
Simulation time 182951137997 ps
CPU time 80.92 seconds
Started Jul 17 05:33:41 PM PDT 24
Finished Jul 17 05:35:04 PM PDT 24
Peak memory 201468 kb
Host smart-025e23ee-8726-4176-84a8-27f8de46ec9f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088359033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3088359033
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.109835826
Short name T483
Test name
Test status
Simulation time 326678101183 ps
CPU time 701.39 seconds
Started Jul 17 05:33:22 PM PDT 24
Finished Jul 17 05:45:05 PM PDT 24
Peak memory 201580 kb
Host smart-9e67b22d-90a4-423c-ac03-1520f34352ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109835826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.109835826
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2744171998
Short name T336
Test name
Test status
Simulation time 484630215210 ps
CPU time 1205.51 seconds
Started Jul 17 05:34:01 PM PDT 24
Finished Jul 17 05:54:08 PM PDT 24
Peak memory 201524 kb
Host smart-82dfdcaf-4540-4dc9-aa7d-111d12ecab8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744171998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2744171998
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3925244951
Short name T131
Test name
Test status
Simulation time 493164991504 ps
CPU time 1106.5 seconds
Started Jul 17 05:33:23 PM PDT 24
Finished Jul 17 05:51:50 PM PDT 24
Peak memory 201520 kb
Host smart-b52661e6-2c0f-4a61-aac5-3652ea1826e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925244951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3925244951
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3097430241
Short name T360
Test name
Test status
Simulation time 163236316653 ps
CPU time 196.17 seconds
Started Jul 17 05:33:23 PM PDT 24
Finished Jul 17 05:36:40 PM PDT 24
Peak memory 201524 kb
Host smart-222789d9-a99e-4780-99ac-61abc700e3a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097430241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3097430241
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2135168306
Short name T630
Test name
Test status
Simulation time 213746982453 ps
CPU time 461.53 seconds
Started Jul 17 05:33:24 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 201532 kb
Host smart-8ccca8e7-5000-4919-a362-17b8b0ea2ef6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135168306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2135168306
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.548597543
Short name T93
Test name
Test status
Simulation time 123607483480 ps
CPU time 520.71 seconds
Started Jul 17 05:33:45 PM PDT 24
Finished Jul 17 05:42:26 PM PDT 24
Peak memory 201916 kb
Host smart-863ad2fb-ce57-4d07-9364-2e6877d415d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548597543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.548597543
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1583341703
Short name T629
Test name
Test status
Simulation time 31713543777 ps
CPU time 16.45 seconds
Started Jul 17 05:33:37 PM PDT 24
Finished Jul 17 05:33:55 PM PDT 24
Peak memory 201288 kb
Host smart-96532509-71a2-4c4c-af63-96ec325c8e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583341703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1583341703
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.231896141
Short name T622
Test name
Test status
Simulation time 4095888671 ps
CPU time 5.7 seconds
Started Jul 17 05:33:36 PM PDT 24
Finished Jul 17 05:33:42 PM PDT 24
Peak memory 201328 kb
Host smart-13696b4d-0525-4e41-9276-2bb17882f882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231896141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.231896141
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2379655162
Short name T653
Test name
Test status
Simulation time 6025621892 ps
CPU time 16.1 seconds
Started Jul 17 05:33:21 PM PDT 24
Finished Jul 17 05:33:38 PM PDT 24
Peak memory 201340 kb
Host smart-d03f914f-6571-43bc-9632-e52ea4081870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379655162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2379655162
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.866165105
Short name T254
Test name
Test status
Simulation time 112867017715 ps
CPU time 37.64 seconds
Started Jul 17 05:33:40 PM PDT 24
Finished Jul 17 05:34:19 PM PDT 24
Peak memory 209856 kb
Host smart-b91df9f4-feff-4862-9538-4acb982f3d45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866165105 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.866165105
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1741106148
Short name T527
Test name
Test status
Simulation time 414879014 ps
CPU time 0.79 seconds
Started Jul 17 05:33:41 PM PDT 24
Finished Jul 17 05:33:43 PM PDT 24
Peak memory 201196 kb
Host smart-544107a8-3ec9-469c-bace-aca567c7b4c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741106148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1741106148
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.977518430
Short name T178
Test name
Test status
Simulation time 495737138915 ps
CPU time 239.34 seconds
Started Jul 17 05:33:37 PM PDT 24
Finished Jul 17 05:37:37 PM PDT 24
Peak memory 201540 kb
Host smart-992730ba-d532-4234-872c-87122cc075eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977518430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.977518430
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3104062711
Short name T788
Test name
Test status
Simulation time 173538959872 ps
CPU time 115.19 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:35:48 PM PDT 24
Peak memory 201480 kb
Host smart-7d7c59d0-a7d5-4134-94e3-d9b3f42982f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104062711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3104062711
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3293039471
Short name T792
Test name
Test status
Simulation time 166088460558 ps
CPU time 112.55 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:35:46 PM PDT 24
Peak memory 201504 kb
Host smart-7935dc6f-6afd-4853-bb22-10ccb0772dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293039471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3293039471
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3832179004
Short name T660
Test name
Test status
Simulation time 334107745151 ps
CPU time 48.09 seconds
Started Jul 17 05:33:40 PM PDT 24
Finished Jul 17 05:34:30 PM PDT 24
Peak memory 201536 kb
Host smart-ba1eb691-6e22-4b60-b9fb-073cf1dd514f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832179004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3832179004
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3024996121
Short name T662
Test name
Test status
Simulation time 168446063919 ps
CPU time 79.63 seconds
Started Jul 17 05:33:37 PM PDT 24
Finished Jul 17 05:34:58 PM PDT 24
Peak memory 201536 kb
Host smart-07a0cedb-032d-4d34-8bb3-adcc1b94d65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024996121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3024996121
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3429575450
Short name T613
Test name
Test status
Simulation time 162432785348 ps
CPU time 91.28 seconds
Started Jul 17 05:33:37 PM PDT 24
Finished Jul 17 05:35:09 PM PDT 24
Peak memory 201524 kb
Host smart-c5836a44-421f-4b97-9e83-31ac99b7c7a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429575450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3429575450
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1506632134
Short name T538
Test name
Test status
Simulation time 375758347033 ps
CPU time 910.77 seconds
Started Jul 17 05:33:42 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 201212 kb
Host smart-4946520a-5213-4c7c-8d52-0e0cce691bf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506632134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1506632134
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1817721492
Short name T541
Test name
Test status
Simulation time 397848710111 ps
CPU time 96.13 seconds
Started Jul 17 05:33:59 PM PDT 24
Finished Jul 17 05:35:36 PM PDT 24
Peak memory 201464 kb
Host smart-5ef941f8-b184-44bf-97dd-029fbf5ca204
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817721492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1817721492
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2435063578
Short name T310
Test name
Test status
Simulation time 62270474227 ps
CPU time 373.86 seconds
Started Jul 17 05:33:36 PM PDT 24
Finished Jul 17 05:39:51 PM PDT 24
Peak memory 201884 kb
Host smart-a41d3521-ee3f-4d79-9029-10693ccf2540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435063578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2435063578
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.719200580
Short name T341
Test name
Test status
Simulation time 42069990681 ps
CPU time 25.43 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:34:20 PM PDT 24
Peak memory 201256 kb
Host smart-42a26735-c798-495c-9426-4c6feeb22fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719200580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.719200580
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2546747774
Short name T648
Test name
Test status
Simulation time 2805878855 ps
CPU time 1.36 seconds
Started Jul 17 05:33:36 PM PDT 24
Finished Jul 17 05:33:38 PM PDT 24
Peak memory 201500 kb
Host smart-acfde921-97ef-416c-97b8-2281f457a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546747774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2546747774
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2320745365
Short name T467
Test name
Test status
Simulation time 5729079454 ps
CPU time 6.91 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:13 PM PDT 24
Peak memory 201304 kb
Host smart-b765c62b-3f9f-4749-9c94-800633dfddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320745365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2320745365
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1829819913
Short name T725
Test name
Test status
Simulation time 239181070288 ps
CPU time 973.83 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:50:09 PM PDT 24
Peak memory 201836 kb
Host smart-5b9db5ac-a6c3-45be-9291-ea1c8503a10a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829819913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1829819913
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.914593193
Short name T274
Test name
Test status
Simulation time 330036223961 ps
CPU time 325.26 seconds
Started Jul 17 05:33:40 PM PDT 24
Finished Jul 17 05:39:07 PM PDT 24
Peak memory 201536 kb
Host smart-932e2ddd-cd9e-49f1-a29a-ba8ea24b38ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914593193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.914593193
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.328733082
Short name T638
Test name
Test status
Simulation time 163643080318 ps
CPU time 108.22 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:35:41 PM PDT 24
Peak memory 201592 kb
Host smart-20d9278a-a195-49fe-8dbf-038de9188cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328733082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.328733082
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4029721520
Short name T425
Test name
Test status
Simulation time 496675968585 ps
CPU time 476.02 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:42:11 PM PDT 24
Peak memory 201476 kb
Host smart-0f11d7f6-4d6e-4701-83dc-b7d4eef2ef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029721520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4029721520
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1673413148
Short name T703
Test name
Test status
Simulation time 327966455721 ps
CPU time 182.93 seconds
Started Jul 17 05:33:37 PM PDT 24
Finished Jul 17 05:36:41 PM PDT 24
Peak memory 201500 kb
Host smart-95523610-a958-41a5-b09d-de89ff5682ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673413148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1673413148
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1029677238
Short name T645
Test name
Test status
Simulation time 500745039470 ps
CPU time 401.19 seconds
Started Jul 17 05:33:37 PM PDT 24
Finished Jul 17 05:40:19 PM PDT 24
Peak memory 201492 kb
Host smart-eec85eed-1882-4573-a009-c80618922781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029677238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1029677238
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1618179474
Short name T669
Test name
Test status
Simulation time 329411879256 ps
CPU time 182.16 seconds
Started Jul 17 05:33:42 PM PDT 24
Finished Jul 17 05:36:46 PM PDT 24
Peak memory 201504 kb
Host smart-0d24e477-acdf-4478-88da-8b7fcdc560bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618179474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1618179474
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2522276870
Short name T785
Test name
Test status
Simulation time 199070173096 ps
CPU time 178 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:37:08 PM PDT 24
Peak memory 201424 kb
Host smart-cc261f8c-2e20-47f2-b30a-f2dd764c1d43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522276870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2522276870
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2652819500
Short name T536
Test name
Test status
Simulation time 393913879342 ps
CPU time 863.9 seconds
Started Jul 17 05:33:36 PM PDT 24
Finished Jul 17 05:48:01 PM PDT 24
Peak memory 201516 kb
Host smart-82096463-77d4-4d18-ac9c-4532ab3cb214
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652819500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2652819500
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.218670380
Short name T464
Test name
Test status
Simulation time 100988188876 ps
CPU time 413.63 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:40:46 PM PDT 24
Peak memory 201824 kb
Host smart-1e43e8c3-bc6f-4b14-be38-a9656ce38408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218670380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.218670380
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1576608244
Short name T739
Test name
Test status
Simulation time 38156613856 ps
CPU time 13.14 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:34:06 PM PDT 24
Peak memory 201320 kb
Host smart-74ee3903-4c3e-466e-be78-aa6ca983f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576608244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1576608244
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.397915420
Short name T6
Test name
Test status
Simulation time 3157721777 ps
CPU time 8.86 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:06 PM PDT 24
Peak memory 201336 kb
Host smart-33467c8d-0ac0-42ae-9843-a1cdc6a1528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397915420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.397915420
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2521940402
Short name T641
Test name
Test status
Simulation time 6021247040 ps
CPU time 16.26 seconds
Started Jul 17 05:33:42 PM PDT 24
Finished Jul 17 05:34:00 PM PDT 24
Peak memory 200968 kb
Host smart-a18bc532-151d-4148-b993-7f640172877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521940402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2521940402
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1963616163
Short name T414
Test name
Test status
Simulation time 51975861529 ps
CPU time 119.67 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:35:57 PM PDT 24
Peak memory 201588 kb
Host smart-bdec44ad-9b82-433b-a952-c3bb104806bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963616163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1963616163
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1568583321
Short name T604
Test name
Test status
Simulation time 416605521 ps
CPU time 0.87 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:33:55 PM PDT 24
Peak memory 201272 kb
Host smart-ccb01d8b-7d19-4d57-a786-cc12bbcd6dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568583321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1568583321
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1322255063
Short name T256
Test name
Test status
Simulation time 165286008208 ps
CPU time 8.15 seconds
Started Jul 17 05:33:56 PM PDT 24
Finished Jul 17 05:34:07 PM PDT 24
Peak memory 201516 kb
Host smart-0c730eee-b951-4135-b4a4-c1ae8298370a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322255063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1322255063
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1066452531
Short name T668
Test name
Test status
Simulation time 492625160294 ps
CPU time 540.73 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:42:56 PM PDT 24
Peak memory 201512 kb
Host smart-7d311ccf-019d-4cf7-9661-a08a17a8ec14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066452531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1066452531
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3755937577
Short name T495
Test name
Test status
Simulation time 165486542181 ps
CPU time 105.77 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:35:54 PM PDT 24
Peak memory 201488 kb
Host smart-487300ed-873f-439f-a040-17fcdc295214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755937577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3755937577
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4018675581
Short name T327
Test name
Test status
Simulation time 336063821230 ps
CPU time 392.29 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:40:30 PM PDT 24
Peak memory 201592 kb
Host smart-2360a39d-1fa3-4b93-b576-08632355af05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018675581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4018675581
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2734426302
Short name T196
Test name
Test status
Simulation time 364895028715 ps
CPU time 238.81 seconds
Started Jul 17 05:33:56 PM PDT 24
Finished Jul 17 05:37:58 PM PDT 24
Peak memory 201532 kb
Host smart-2fd8e17b-293a-41b5-93aa-6191d5eb13fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734426302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2734426302
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2634230411
Short name T551
Test name
Test status
Simulation time 196214663856 ps
CPU time 184.6 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:37:16 PM PDT 24
Peak memory 200908 kb
Host smart-cf22fa91-9d89-4764-a590-d02e9b718028
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634230411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2634230411
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2028105385
Short name T452
Test name
Test status
Simulation time 27432456961 ps
CPU time 64.11 seconds
Started Jul 17 05:33:56 PM PDT 24
Finished Jul 17 05:35:03 PM PDT 24
Peak memory 201324 kb
Host smart-897ed625-4b29-4f71-89af-24aafcfdfd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028105385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2028105385
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4084399322
Short name T355
Test name
Test status
Simulation time 4746691947 ps
CPU time 11.96 seconds
Started Jul 17 05:33:58 PM PDT 24
Finished Jul 17 05:34:11 PM PDT 24
Peak memory 201324 kb
Host smart-4f13a874-1de1-443c-9df8-31f64fdd1da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084399322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4084399322
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2474266830
Short name T694
Test name
Test status
Simulation time 5738773930 ps
CPU time 6.03 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:34:00 PM PDT 24
Peak memory 201316 kb
Host smart-75df971a-eb31-4d47-aaa6-64df775abf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474266830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2474266830
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1913530141
Short name T574
Test name
Test status
Simulation time 227856765867 ps
CPU time 180.98 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:36:57 PM PDT 24
Peak memory 210280 kb
Host smart-941b369e-115c-4889-a523-6c7f9b62d289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913530141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1913530141
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3596324126
Short name T395
Test name
Test status
Simulation time 315467964 ps
CPU time 1.37 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:34:16 PM PDT 24
Peak memory 201216 kb
Host smart-7e7e06d4-a6fa-41bb-9995-28c98887e6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596324126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3596324126
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3650143688
Short name T299
Test name
Test status
Simulation time 385124761261 ps
CPU time 425.86 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:41:04 PM PDT 24
Peak memory 201552 kb
Host smart-2467174d-8a25-43b5-a553-fc60eca58d99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650143688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3650143688
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1094822643
Short name T781
Test name
Test status
Simulation time 334216098244 ps
CPU time 413.65 seconds
Started Jul 17 05:33:56 PM PDT 24
Finished Jul 17 05:40:53 PM PDT 24
Peak memory 201600 kb
Host smart-cdc8c328-adb3-4bce-abbe-ada24eaee96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094822643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1094822643
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2384829461
Short name T182
Test name
Test status
Simulation time 488136462181 ps
CPU time 296.68 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:38:54 PM PDT 24
Peak memory 201592 kb
Host smart-e198c54f-6199-4ef0-a940-29166741f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384829461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2384829461
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2993046653
Short name T364
Test name
Test status
Simulation time 330190635380 ps
CPU time 68.49 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:35:20 PM PDT 24
Peak memory 200932 kb
Host smart-dad5f0f0-9ee5-4ade-a67b-0f04557ede7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993046653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2993046653
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1092543324
Short name T271
Test name
Test status
Simulation time 325830805485 ps
CPU time 196.09 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:37:25 PM PDT 24
Peak memory 201596 kb
Host smart-742a3968-4cdc-40ff-a1f6-29e151cf3866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092543324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1092543324
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.794945230
Short name T189
Test name
Test status
Simulation time 492872979486 ps
CPU time 1220.78 seconds
Started Jul 17 05:33:57 PM PDT 24
Finished Jul 17 05:54:20 PM PDT 24
Peak memory 201520 kb
Host smart-2c419a69-90de-4646-9959-4e532fcb9688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=794945230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.794945230
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2240229504
Short name T321
Test name
Test status
Simulation time 86017968763 ps
CPU time 417.65 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:41:12 PM PDT 24
Peak memory 201832 kb
Host smart-35494c0f-37f3-4f9c-9af6-587774d59a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240229504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2240229504
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3387389114
Short name T670
Test name
Test status
Simulation time 33399694774 ps
CPU time 16.37 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:23 PM PDT 24
Peak memory 201332 kb
Host smart-2b8135ba-0dea-48e0-a45c-451fa96f6062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387389114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3387389114
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1833798994
Short name T563
Test name
Test status
Simulation time 4630293797 ps
CPU time 6.6 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:12 PM PDT 24
Peak memory 201284 kb
Host smart-ac756f7f-f010-4977-9359-83db79b0c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833798994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1833798994
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4247999930
Short name T426
Test name
Test status
Simulation time 5684793685 ps
CPU time 11.96 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:34:07 PM PDT 24
Peak memory 201348 kb
Host smart-6867d506-7d49-423c-8ebf-3d68237e30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247999930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4247999930
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2750966282
Short name T325
Test name
Test status
Simulation time 272756531392 ps
CPU time 814.22 seconds
Started Jul 17 05:34:00 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 212200 kb
Host smart-f7fc1182-623a-4736-b0e1-0dbed292dd0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750966282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2750966282
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.637818132
Short name T263
Test name
Test status
Simulation time 27092981386 ps
CPU time 48.61 seconds
Started Jul 17 05:34:06 PM PDT 24
Finished Jul 17 05:34:55 PM PDT 24
Peak memory 209928 kb
Host smart-28169b1f-ef8b-4886-87b5-2878f7deae5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637818132 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.637818132
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1617821256
Short name T595
Test name
Test status
Simulation time 523424570 ps
CPU time 1.2 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:34:16 PM PDT 24
Peak memory 201224 kb
Host smart-39053d6d-fa8f-415d-b9cb-68bce7b025c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617821256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1617821256
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.180907083
Short name T135
Test name
Test status
Simulation time 478896425833 ps
CPU time 269.02 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:38:34 PM PDT 24
Peak memory 201544 kb
Host smart-4fb04a08-43e0-472d-991f-0f37e5b92b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180907083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.180907083
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3073340578
Short name T90
Test name
Test status
Simulation time 163868006758 ps
CPU time 356.98 seconds
Started Jul 17 05:34:05 PM PDT 24
Finished Jul 17 05:40:03 PM PDT 24
Peak memory 201508 kb
Host smart-3e47a365-45f4-4969-87d6-36cf28e4bb08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073340578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3073340578
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1606454374
Short name T521
Test name
Test status
Simulation time 162297430688 ps
CPU time 180.67 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:37:05 PM PDT 24
Peak memory 201468 kb
Host smart-fdad0870-cdde-453d-8c11-2ec95f8a7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606454374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1606454374
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3517331637
Short name T626
Test name
Test status
Simulation time 161783648059 ps
CPU time 380.28 seconds
Started Jul 17 05:34:05 PM PDT 24
Finished Jul 17 05:40:27 PM PDT 24
Peak memory 201500 kb
Host smart-7e5e430e-9956-4733-803a-93cad64b8a70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517331637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3517331637
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3157190694
Short name T246
Test name
Test status
Simulation time 449621035600 ps
CPU time 489.2 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:42:13 PM PDT 24
Peak memory 201548 kb
Host smart-08021feb-92dd-4807-a2eb-c7b1eb575c1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157190694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3157190694
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2977699601
Short name T475
Test name
Test status
Simulation time 201609975075 ps
CPU time 104.97 seconds
Started Jul 17 05:34:02 PM PDT 24
Finished Jul 17 05:35:49 PM PDT 24
Peak memory 201520 kb
Host smart-ec8db1bc-a1be-4cc4-84d0-a627d881252f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977699601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2977699601
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3607238803
Short name T778
Test name
Test status
Simulation time 129390036564 ps
CPU time 502.75 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:42:38 PM PDT 24
Peak memory 201844 kb
Host smart-0d06a441-8c88-4283-9df5-d5455121a1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607238803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3607238803
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3412171990
Short name T699
Test name
Test status
Simulation time 40942295247 ps
CPU time 96.8 seconds
Started Jul 17 05:34:02 PM PDT 24
Finished Jul 17 05:35:40 PM PDT 24
Peak memory 201340 kb
Host smart-8d35403d-4937-4117-85b3-d396bb082414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412171990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3412171990
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1143644785
Short name T331
Test name
Test status
Simulation time 4377383237 ps
CPU time 5.96 seconds
Started Jul 17 05:34:02 PM PDT 24
Finished Jul 17 05:34:09 PM PDT 24
Peak memory 201324 kb
Host smart-2b2f9b00-9684-432d-8a0a-0e6a06fd8ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143644785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1143644785
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3124789972
Short name T419
Test name
Test status
Simulation time 5490280392 ps
CPU time 3.51 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:09 PM PDT 24
Peak memory 201272 kb
Host smart-61471afc-d541-4c5e-b20c-81a6085469a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124789972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3124789972
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1008897271
Short name T261
Test name
Test status
Simulation time 188004664744 ps
CPU time 83.73 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:35:35 PM PDT 24
Peak memory 201472 kb
Host smart-cdb4e9f3-0fa2-4c96-a11d-e6245f30dc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008897271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1008897271
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2845956217
Short name T108
Test name
Test status
Simulation time 7052141911 ps
CPU time 19.87 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:26 PM PDT 24
Peak memory 201584 kb
Host smart-605e4606-014c-474e-93fd-d3601eb31098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845956217 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2845956217
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2181706805
Short name T635
Test name
Test status
Simulation time 486823142 ps
CPU time 0.82 seconds
Started Jul 17 05:34:21 PM PDT 24
Finished Jul 17 05:34:22 PM PDT 24
Peak memory 201240 kb
Host smart-18b707f8-5680-446c-80db-ca9adcf219a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181706805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2181706805
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3265878650
Short name T173
Test name
Test status
Simulation time 495088859894 ps
CPU time 246.51 seconds
Started Jul 17 05:34:21 PM PDT 24
Finished Jul 17 05:38:28 PM PDT 24
Peak memory 201544 kb
Host smart-d8824f6e-f4d1-4af3-9174-df619fbadc10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265878650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3265878650
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.691689823
Short name T130
Test name
Test status
Simulation time 410621792134 ps
CPU time 947.38 seconds
Started Jul 17 05:34:18 PM PDT 24
Finished Jul 17 05:50:07 PM PDT 24
Peak memory 201620 kb
Host smart-e1d89cdb-5913-4533-9dfc-e4e6510c828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691689823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.691689823
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1101346374
Short name T203
Test name
Test status
Simulation time 160919185603 ps
CPU time 374.71 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:40:20 PM PDT 24
Peak memory 201548 kb
Host smart-6df2afef-2d48-49be-bc55-25dfcc0c74aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101346374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1101346374
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.464312665
Short name T405
Test name
Test status
Simulation time 332650591966 ps
CPU time 773.95 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:47:00 PM PDT 24
Peak memory 201452 kb
Host smart-8f742f41-d1fa-4426-9d33-70e529c72b92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=464312665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.464312665
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3453887282
Short name T649
Test name
Test status
Simulation time 480659878080 ps
CPU time 595.91 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:44:04 PM PDT 24
Peak memory 201508 kb
Host smart-e7817cb4-670f-49ad-9681-c9bf0c3aa370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453887282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3453887282
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.217576101
Short name T486
Test name
Test status
Simulation time 331749029780 ps
CPU time 355.21 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:40:05 PM PDT 24
Peak memory 201588 kb
Host smart-93a72ac8-93c0-494f-a2a4-34c46437190b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217576101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.217576101
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1599961580
Short name T510
Test name
Test status
Simulation time 415697010492 ps
CPU time 191.72 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:37:21 PM PDT 24
Peak memory 201584 kb
Host smart-5bf8f3ae-bf72-4696-963b-86de2d8ae02c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599961580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1599961580
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1803590964
Short name T609
Test name
Test status
Simulation time 25774126467 ps
CPU time 59.37 seconds
Started Jul 17 05:34:16 PM PDT 24
Finished Jul 17 05:35:18 PM PDT 24
Peak memory 201332 kb
Host smart-5ee5c72d-63bc-45b5-9715-e8d5f39945f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803590964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1803590964
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.383659174
Short name T103
Test name
Test status
Simulation time 2935458061 ps
CPU time 5.14 seconds
Started Jul 17 05:34:15 PM PDT 24
Finished Jul 17 05:34:24 PM PDT 24
Peak memory 201292 kb
Host smart-002289c1-f1d9-4023-88ab-228ea5b1290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383659174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.383659174
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.858293535
Short name T494
Test name
Test status
Simulation time 6013943417 ps
CPU time 4.15 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:34:13 PM PDT 24
Peak memory 201324 kb
Host smart-aef3e560-6941-4c8c-91fc-021678657926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858293535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.858293535
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.947428001
Short name T359
Test name
Test status
Simulation time 531838487 ps
CPU time 1.23 seconds
Started Jul 17 05:31:46 PM PDT 24
Finished Jul 17 05:31:48 PM PDT 24
Peak memory 201284 kb
Host smart-6d918230-a1c5-44db-bc50-39276e514346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947428001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.947428001
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3402849369
Short name T275
Test name
Test status
Simulation time 341138454499 ps
CPU time 766.2 seconds
Started Jul 17 05:31:46 PM PDT 24
Finished Jul 17 05:44:33 PM PDT 24
Peak memory 201536 kb
Host smart-3381b14b-abbb-4039-86f9-033e87a7de8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402849369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3402849369
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.525799806
Short name T175
Test name
Test status
Simulation time 520951512279 ps
CPU time 364.93 seconds
Started Jul 17 05:31:44 PM PDT 24
Finished Jul 17 05:37:50 PM PDT 24
Peak memory 201544 kb
Host smart-124a4f88-bb77-48de-9a1c-fc92d11bb11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525799806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.525799806
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2943223412
Short name T95
Test name
Test status
Simulation time 499384161857 ps
CPU time 256.53 seconds
Started Jul 17 05:31:42 PM PDT 24
Finished Jul 17 05:36:00 PM PDT 24
Peak memory 201492 kb
Host smart-bc757b4d-27e8-4fd2-9d21-6ba4bb25d4ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943223412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2943223412
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1936713737
Short name T439
Test name
Test status
Simulation time 488989379957 ps
CPU time 1025.19 seconds
Started Jul 17 05:31:39 PM PDT 24
Finished Jul 17 05:48:45 PM PDT 24
Peak memory 201544 kb
Host smart-e14463d3-fb01-4ec3-8119-1fb6f770b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936713737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1936713737
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2077746118
Short name T339
Test name
Test status
Simulation time 485325996354 ps
CPU time 1141.2 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:50:43 PM PDT 24
Peak memory 201532 kb
Host smart-fd80568d-26f3-48aa-82f2-d99847e58598
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077746118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2077746118
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.352386147
Short name T674
Test name
Test status
Simulation time 554678323014 ps
CPU time 1141.3 seconds
Started Jul 17 05:33:41 PM PDT 24
Finished Jul 17 05:52:44 PM PDT 24
Peak memory 201612 kb
Host smart-5dab357c-a34e-4520-b99f-a05e1d94911a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352386147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.352386147
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1329373922
Short name T214
Test name
Test status
Simulation time 389265322282 ps
CPU time 922.84 seconds
Started Jul 17 05:31:46 PM PDT 24
Finished Jul 17 05:47:10 PM PDT 24
Peak memory 201476 kb
Host smart-8f7df538-d7db-45b8-8a6d-2a35ceb351b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329373922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1329373922
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2664403840
Short name T415
Test name
Test status
Simulation time 38827894856 ps
CPU time 14.43 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:31:57 PM PDT 24
Peak memory 201324 kb
Host smart-df719c0f-52d1-4f03-bf1b-c82d978a0eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664403840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2664403840
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.746493998
Short name T105
Test name
Test status
Simulation time 4054897421 ps
CPU time 10.02 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:31:53 PM PDT 24
Peak memory 201248 kb
Host smart-40ac6d1f-6272-49eb-8358-51145fe3a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746493998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.746493998
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2843371144
Short name T56
Test name
Test status
Simulation time 4131074215 ps
CPU time 10.59 seconds
Started Jul 17 05:31:41 PM PDT 24
Finished Jul 17 05:31:53 PM PDT 24
Peak memory 217068 kb
Host smart-f00d25f5-572e-4053-acea-58450741f3cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843371144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2843371144
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3448409821
Short name T512
Test name
Test status
Simulation time 5774053563 ps
CPU time 7.3 seconds
Started Jul 17 05:31:42 PM PDT 24
Finished Jul 17 05:31:51 PM PDT 24
Peak memory 201256 kb
Host smart-249819f7-8d71-42da-a00b-6015fd92d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448409821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3448409821
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.546000876
Short name T80
Test name
Test status
Simulation time 165695282842 ps
CPU time 188.07 seconds
Started Jul 17 05:31:45 PM PDT 24
Finished Jul 17 05:34:53 PM PDT 24
Peak memory 201580 kb
Host smart-fb9ae42e-3d06-44b2-8b22-9800e5af831d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546000876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.546000876
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2660531115
Short name T86
Test name
Test status
Simulation time 45932358940 ps
CPU time 102.52 seconds
Started Jul 17 05:31:46 PM PDT 24
Finished Jul 17 05:33:30 PM PDT 24
Peak memory 209840 kb
Host smart-297aa59a-6980-4873-bdef-89ba9caed8d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660531115 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2660531115
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2428795148
Short name T530
Test name
Test status
Simulation time 391363380 ps
CPU time 1.54 seconds
Started Jul 17 05:34:28 PM PDT 24
Finished Jul 17 05:34:31 PM PDT 24
Peak memory 201272 kb
Host smart-dc4386c3-189f-4847-9409-e85b2e218f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428795148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2428795148
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3157018392
Short name T7
Test name
Test status
Simulation time 163850825437 ps
CPU time 97.64 seconds
Started Jul 17 05:34:17 PM PDT 24
Finished Jul 17 05:35:57 PM PDT 24
Peak memory 201596 kb
Host smart-861772cb-3449-4d2c-b9e2-a3f03dd622a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157018392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3157018392
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.160007666
Short name T296
Test name
Test status
Simulation time 353570831631 ps
CPU time 767.11 seconds
Started Jul 17 05:34:16 PM PDT 24
Finished Jul 17 05:47:06 PM PDT 24
Peak memory 201544 kb
Host smart-d1ceb965-80e4-4e12-b17c-8616c727ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160007666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.160007666
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4286429400
Short name T679
Test name
Test status
Simulation time 166590872913 ps
CPU time 387.1 seconds
Started Jul 17 05:34:16 PM PDT 24
Finished Jul 17 05:40:46 PM PDT 24
Peak memory 201492 kb
Host smart-4f4e3b70-a34f-4ad4-a11c-c3f47cd9977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286429400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4286429400
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.674858381
Short name T732
Test name
Test status
Simulation time 324708050176 ps
CPU time 386.55 seconds
Started Jul 17 05:34:19 PM PDT 24
Finished Jul 17 05:40:47 PM PDT 24
Peak memory 201460 kb
Host smart-89ba7948-1098-41ad-ad67-41569eeb5eb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=674858381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.674858381
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2015952449
Short name T692
Test name
Test status
Simulation time 330402955412 ps
CPU time 730.93 seconds
Started Jul 17 05:34:18 PM PDT 24
Finished Jul 17 05:46:31 PM PDT 24
Peak memory 201544 kb
Host smart-8c0d280e-f6ca-4785-a69b-b70b7da6bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015952449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2015952449
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3141695347
Short name T599
Test name
Test status
Simulation time 491818268901 ps
CPU time 1100.97 seconds
Started Jul 17 05:34:15 PM PDT 24
Finished Jul 17 05:52:39 PM PDT 24
Peak memory 201452 kb
Host smart-0431f3e2-4511-4571-8b63-063cc0f414f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141695347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3141695347
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2258207052
Short name T640
Test name
Test status
Simulation time 186903127095 ps
CPU time 118.08 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:36:15 PM PDT 24
Peak memory 201552 kb
Host smart-d02246a4-723c-43a0-97f1-8d8034af36bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258207052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2258207052
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.232418468
Short name T76
Test name
Test status
Simulation time 387650171859 ps
CPU time 231.06 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:38:09 PM PDT 24
Peak memory 201484 kb
Host smart-87b85eeb-0f43-4fd8-91d0-9d0c2456efd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232418468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.232418468
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1423812137
Short name T46
Test name
Test status
Simulation time 132943492930 ps
CPU time 681.28 seconds
Started Jul 17 05:34:16 PM PDT 24
Finished Jul 17 05:45:40 PM PDT 24
Peak memory 201952 kb
Host smart-f7c2866a-551d-4d90-85b4-94cd6497e1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423812137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1423812137
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4130735771
Short name T771
Test name
Test status
Simulation time 47703240981 ps
CPU time 21.45 seconds
Started Jul 17 05:34:15 PM PDT 24
Finished Jul 17 05:34:40 PM PDT 24
Peak memory 201304 kb
Host smart-5c076db1-f9b2-499e-a924-5f446c4a1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130735771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4130735771
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1866798805
Short name T634
Test name
Test status
Simulation time 4247241245 ps
CPU time 2.83 seconds
Started Jul 17 05:34:15 PM PDT 24
Finished Jul 17 05:34:21 PM PDT 24
Peak memory 201308 kb
Host smart-459d69b7-39b1-4e30-b6bf-fc497f99c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866798805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1866798805
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1484627652
Short name T397
Test name
Test status
Simulation time 5838304996 ps
CPU time 13.21 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:34:31 PM PDT 24
Peak memory 201340 kb
Host smart-70151bba-5d78-48b5-a776-6a8aad918658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484627652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1484627652
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2058941998
Short name T36
Test name
Test status
Simulation time 32628739099 ps
CPU time 58.3 seconds
Started Jul 17 05:34:26 PM PDT 24
Finished Jul 17 05:35:25 PM PDT 24
Peak memory 201592 kb
Host smart-5ea47b45-0711-4b4f-ab84-8ccedd3929db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058941998 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2058941998
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3356229323
Short name T546
Test name
Test status
Simulation time 324634832 ps
CPU time 0.81 seconds
Started Jul 17 05:34:27 PM PDT 24
Finished Jul 17 05:34:29 PM PDT 24
Peak memory 201272 kb
Host smart-407b366c-1801-4e7a-a987-95af7b3b89ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356229323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3356229323
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2834653225
Short name T656
Test name
Test status
Simulation time 590191409958 ps
CPU time 200.4 seconds
Started Jul 17 05:34:30 PM PDT 24
Finished Jul 17 05:37:51 PM PDT 24
Peak memory 201524 kb
Host smart-0054b374-c895-4c10-91f7-9d157cb5a1f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834653225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2834653225
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3118130022
Short name T547
Test name
Test status
Simulation time 324746166183 ps
CPU time 660.33 seconds
Started Jul 17 05:34:23 PM PDT 24
Finished Jul 17 05:45:24 PM PDT 24
Peak memory 201464 kb
Host smart-ad5c11e3-20a8-4016-9a70-b2663398431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118130022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3118130022
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3682910807
Short name T457
Test name
Test status
Simulation time 164904938899 ps
CPU time 352.74 seconds
Started Jul 17 05:34:24 PM PDT 24
Finished Jul 17 05:40:18 PM PDT 24
Peak memory 201512 kb
Host smart-5dd03b58-18bb-4f2a-9e62-7d3a722849b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682910807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3682910807
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3444417952
Short name T701
Test name
Test status
Simulation time 167335050942 ps
CPU time 96.87 seconds
Started Jul 17 05:34:27 PM PDT 24
Finished Jul 17 05:36:05 PM PDT 24
Peak memory 201592 kb
Host smart-160497d3-4212-4402-8253-20e2aaf1af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444417952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3444417952
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3161612689
Short name T404
Test name
Test status
Simulation time 335775111151 ps
CPU time 777.75 seconds
Started Jul 17 05:34:23 PM PDT 24
Finished Jul 17 05:47:22 PM PDT 24
Peak memory 201584 kb
Host smart-2cd6fc6e-01fc-4cf8-b1f6-2d80e75a229b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161612689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3161612689
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1507609848
Short name T91
Test name
Test status
Simulation time 565888744543 ps
CPU time 670.3 seconds
Started Jul 17 05:34:23 PM PDT 24
Finished Jul 17 05:45:35 PM PDT 24
Peak memory 201556 kb
Host smart-d906bbf2-425c-434a-8c1b-e25c7bfa9b53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507609848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1507609848
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1782264726
Short name T591
Test name
Test status
Simulation time 196665146409 ps
CPU time 106.58 seconds
Started Jul 17 05:34:26 PM PDT 24
Finished Jul 17 05:36:13 PM PDT 24
Peak memory 201508 kb
Host smart-45b2ccb5-df5c-4b2f-8b0e-2dd6ca500bf5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782264726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1782264726
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.999751553
Short name T740
Test name
Test status
Simulation time 109098817624 ps
CPU time 382.92 seconds
Started Jul 17 05:34:25 PM PDT 24
Finished Jul 17 05:40:49 PM PDT 24
Peak memory 202128 kb
Host smart-a7d22d25-677d-4d8f-8229-75ed17bd9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999751553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.999751553
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1608074609
Short name T508
Test name
Test status
Simulation time 21826212336 ps
CPU time 29.15 seconds
Started Jul 17 05:34:23 PM PDT 24
Finished Jul 17 05:34:53 PM PDT 24
Peak memory 201328 kb
Host smart-49b09de7-f197-428a-adae-c94e76b65ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608074609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1608074609
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3237289999
Short name T764
Test name
Test status
Simulation time 4223782746 ps
CPU time 3.24 seconds
Started Jul 17 05:34:27 PM PDT 24
Finished Jul 17 05:34:31 PM PDT 24
Peak memory 201304 kb
Host smart-8b898ed1-87ea-48a3-a04c-2916c20315bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237289999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3237289999
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1602961628
Short name T440
Test name
Test status
Simulation time 5584289640 ps
CPU time 12.99 seconds
Started Jul 17 05:34:25 PM PDT 24
Finished Jul 17 05:34:39 PM PDT 24
Peak memory 201252 kb
Host smart-2155f2cc-6cbe-4575-b5bb-59fe33cbde74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602961628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1602961628
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.474946874
Short name T590
Test name
Test status
Simulation time 108842208634 ps
CPU time 404.8 seconds
Started Jul 17 05:34:26 PM PDT 24
Finished Jul 17 05:41:11 PM PDT 24
Peak memory 217732 kb
Host smart-fea0bd6d-77a5-45d4-b5bc-caf9042d58a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474946874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
474946874
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1614916832
Short name T15
Test name
Test status
Simulation time 98407600174 ps
CPU time 163.39 seconds
Started Jul 17 05:34:28 PM PDT 24
Finished Jul 17 05:37:12 PM PDT 24
Peak memory 210276 kb
Host smart-2a92f920-f83b-4027-925e-06b37a125825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614916832 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1614916832
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.376309030
Short name T585
Test name
Test status
Simulation time 512374942 ps
CPU time 1.59 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:34:48 PM PDT 24
Peak memory 201276 kb
Host smart-a76c867e-6b20-42c4-b912-aaf28601360d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376309030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.376309030
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2917034528
Short name T466
Test name
Test status
Simulation time 505552055697 ps
CPU time 87.5 seconds
Started Jul 17 05:34:26 PM PDT 24
Finished Jul 17 05:35:54 PM PDT 24
Peak memory 201504 kb
Host smart-4ac37dc7-3ae3-48b8-aa75-ec1d09b5ac6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917034528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2917034528
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.121426577
Short name T291
Test name
Test status
Simulation time 542647533768 ps
CPU time 337.16 seconds
Started Jul 17 05:34:24 PM PDT 24
Finished Jul 17 05:40:02 PM PDT 24
Peak memory 201516 kb
Host smart-309d3384-5afe-4184-ac2e-4b01c719fee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121426577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.121426577
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3490979852
Short name T461
Test name
Test status
Simulation time 317023648997 ps
CPU time 679.27 seconds
Started Jul 17 05:34:24 PM PDT 24
Finished Jul 17 05:45:44 PM PDT 24
Peak memory 201588 kb
Host smart-1392fe5b-bcf1-466c-9ef2-ab4746031186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490979852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3490979852
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1856383174
Short name T473
Test name
Test status
Simulation time 320764992334 ps
CPU time 221.62 seconds
Started Jul 17 05:34:29 PM PDT 24
Finished Jul 17 05:38:12 PM PDT 24
Peak memory 201520 kb
Host smart-64439bd4-834b-4103-bd2c-ab86f54f8803
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856383174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1856383174
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3827449632
Short name T558
Test name
Test status
Simulation time 322913130221 ps
CPU time 673.3 seconds
Started Jul 17 05:34:24 PM PDT 24
Finished Jul 17 05:45:38 PM PDT 24
Peak memory 201616 kb
Host smart-2dd4ffec-65b3-4e19-9879-b1bb95c74227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827449632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3827449632
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3445409688
Short name T746
Test name
Test status
Simulation time 333597438681 ps
CPU time 409.11 seconds
Started Jul 17 05:34:28 PM PDT 24
Finished Jul 17 05:41:19 PM PDT 24
Peak memory 201732 kb
Host smart-1f7ad3f0-828b-410c-834f-00aee9144676
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445409688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3445409688
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.331884010
Short name T750
Test name
Test status
Simulation time 525854298707 ps
CPU time 895.63 seconds
Started Jul 17 05:34:26 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 201444 kb
Host smart-c29dda25-0dea-422a-a709-0a94397b2283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331884010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.331884010
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3225237018
Short name T738
Test name
Test status
Simulation time 212834832809 ps
CPU time 239.07 seconds
Started Jul 17 05:34:27 PM PDT 24
Finished Jul 17 05:38:27 PM PDT 24
Peak memory 201448 kb
Host smart-40a061cc-15f2-4477-9955-7375e9e36454
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225237018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3225237018
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.716399395
Short name T398
Test name
Test status
Simulation time 33825243310 ps
CPU time 11.32 seconds
Started Jul 17 05:34:30 PM PDT 24
Finished Jul 17 05:34:42 PM PDT 24
Peak memory 201332 kb
Host smart-cb510541-91d2-48b1-8ad9-fc2b52840982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716399395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.716399395
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3471489849
Short name T23
Test name
Test status
Simulation time 3203430236 ps
CPU time 7.43 seconds
Started Jul 17 05:34:24 PM PDT 24
Finished Jul 17 05:34:33 PM PDT 24
Peak memory 201332 kb
Host smart-0e5ea9e8-5db6-4f02-a13e-79a847e73f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471489849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3471489849
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2334127614
Short name T435
Test name
Test status
Simulation time 6048390500 ps
CPU time 4.54 seconds
Started Jul 17 05:34:26 PM PDT 24
Finished Jul 17 05:34:32 PM PDT 24
Peak memory 201352 kb
Host smart-348a775f-7fbf-42e3-b2ee-c51006ae8377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334127614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2334127614
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2187677231
Short name T793
Test name
Test status
Simulation time 43187581879 ps
CPU time 42.91 seconds
Started Jul 17 05:34:52 PM PDT 24
Finished Jul 17 05:35:36 PM PDT 24
Peak memory 201324 kb
Host smart-a0a360b7-b931-4041-981d-d8af7ca359f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187677231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2187677231
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1731993082
Short name T22
Test name
Test status
Simulation time 356102905510 ps
CPU time 540.06 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:43:46 PM PDT 24
Peak memory 218332 kb
Host smart-a3f0c632-72cb-4a97-beea-37b09293bbcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731993082 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1731993082
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2111715799
Short name T465
Test name
Test status
Simulation time 348684928 ps
CPU time 0.77 seconds
Started Jul 17 05:34:47 PM PDT 24
Finished Jul 17 05:34:49 PM PDT 24
Peak memory 201248 kb
Host smart-3e79a917-7521-43fb-bd6f-09a36215bd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111715799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2111715799
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3593793311
Short name T138
Test name
Test status
Simulation time 514359574139 ps
CPU time 1079.07 seconds
Started Jul 17 05:34:53 PM PDT 24
Finished Jul 17 05:52:53 PM PDT 24
Peak memory 201520 kb
Host smart-bdf07dea-2b0c-4c6b-b258-e417c8206f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593793311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3593793311
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3695474411
Short name T782
Test name
Test status
Simulation time 324953793334 ps
CPU time 697.88 seconds
Started Jul 17 05:34:45 PM PDT 24
Finished Jul 17 05:46:23 PM PDT 24
Peak memory 201528 kb
Host smart-fe169f7d-65ce-4176-8a8a-2531c5a876a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695474411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3695474411
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2354646295
Short name T676
Test name
Test status
Simulation time 175126566835 ps
CPU time 361.66 seconds
Started Jul 17 05:34:47 PM PDT 24
Finished Jul 17 05:40:49 PM PDT 24
Peak memory 201476 kb
Host smart-9e0ff26d-581a-4294-b0a4-3632dd5eb8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354646295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2354646295
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.766513360
Short name T389
Test name
Test status
Simulation time 492271655874 ps
CPU time 1145.21 seconds
Started Jul 17 05:34:47 PM PDT 24
Finished Jul 17 05:53:53 PM PDT 24
Peak memory 201524 kb
Host smart-c289dd9b-2027-40b5-8552-ce45efed87ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=766513360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.766513360
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2026109963
Short name T659
Test name
Test status
Simulation time 489832086656 ps
CPU time 1029.65 seconds
Started Jul 17 05:34:44 PM PDT 24
Finished Jul 17 05:51:54 PM PDT 24
Peak memory 201532 kb
Host smart-7a450856-ceee-498b-8661-245e0b20d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026109963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2026109963
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1626743734
Short name T472
Test name
Test status
Simulation time 496022976837 ps
CPU time 1165.76 seconds
Started Jul 17 05:34:44 PM PDT 24
Finished Jul 17 05:54:11 PM PDT 24
Peak memory 201524 kb
Host smart-4c9a2ead-b8ab-4530-8a6a-c502a274194b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626743734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1626743734
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.339958080
Short name T265
Test name
Test status
Simulation time 625782575402 ps
CPU time 77.64 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:36:05 PM PDT 24
Peak memory 201504 kb
Host smart-ef928aea-36a7-4318-aad6-80a9ad250b68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339958080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.339958080
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3624890698
Short name T188
Test name
Test status
Simulation time 598821424593 ps
CPU time 348.81 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:40:36 PM PDT 24
Peak memory 201444 kb
Host smart-2e0365aa-b0e9-4829-a969-2da085d03444
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624890698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3624890698
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1147471401
Short name T597
Test name
Test status
Simulation time 78010936889 ps
CPU time 466.95 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:42:34 PM PDT 24
Peak memory 201908 kb
Host smart-de082e54-b4b4-4adf-aad3-e07c91b65d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147471401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1147471401
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3468723222
Short name T747
Test name
Test status
Simulation time 36538872518 ps
CPU time 23.54 seconds
Started Jul 17 05:34:47 PM PDT 24
Finished Jul 17 05:35:11 PM PDT 24
Peak memory 201260 kb
Host smart-d2b92da0-f053-4661-bad4-16d567057c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468723222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3468723222
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3742750961
Short name T375
Test name
Test status
Simulation time 3115962410 ps
CPU time 2.5 seconds
Started Jul 17 05:34:46 PM PDT 24
Finished Jul 17 05:34:50 PM PDT 24
Peak memory 201260 kb
Host smart-dd7c5eea-88b4-4cf6-a0ef-5446ced34f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742750961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3742750961
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.569091945
Short name T408
Test name
Test status
Simulation time 5734423302 ps
CPU time 13.92 seconds
Started Jul 17 05:34:47 PM PDT 24
Finished Jul 17 05:35:02 PM PDT 24
Peak memory 201324 kb
Host smart-8e1e242e-637d-479c-8227-48ced473f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569091945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.569091945
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1689382022
Short name T502
Test name
Test status
Simulation time 11760389188 ps
CPU time 15.31 seconds
Started Jul 17 05:34:47 PM PDT 24
Finished Jul 17 05:35:03 PM PDT 24
Peak memory 201520 kb
Host smart-c10b7a28-db94-4120-8e9c-1cc02f1b52e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689382022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1689382022
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1968693325
Short name T242
Test name
Test status
Simulation time 488050520821 ps
CPU time 330.84 seconds
Started Jul 17 05:34:52 PM PDT 24
Finished Jul 17 05:40:24 PM PDT 24
Peak memory 210228 kb
Host smart-4d2a52fb-d3f8-4af9-b9ba-4af124c99b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968693325 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1968693325
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4068577953
Short name T350
Test name
Test status
Simulation time 511814300 ps
CPU time 1.24 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:35:14 PM PDT 24
Peak memory 201256 kb
Host smart-de9a6d96-7b70-43f5-b2f0-9852fe94c628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068577953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4068577953
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3419586132
Short name T10
Test name
Test status
Simulation time 172215956043 ps
CPU time 90.22 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:36:41 PM PDT 24
Peak memory 201616 kb
Host smart-d5ea286a-9421-41b9-ad42-6fdba31f47b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419586132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3419586132
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3433186966
Short name T245
Test name
Test status
Simulation time 539317118954 ps
CPU time 98.55 seconds
Started Jul 17 05:35:07 PM PDT 24
Finished Jul 17 05:36:47 PM PDT 24
Peak memory 201536 kb
Host smart-1db6d3cb-8ecd-4382-827d-f380692962e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433186966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3433186966
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4153431192
Short name T482
Test name
Test status
Simulation time 496360366949 ps
CPU time 1153.35 seconds
Started Jul 17 05:34:49 PM PDT 24
Finished Jul 17 05:54:03 PM PDT 24
Peak memory 201472 kb
Host smart-01a0b4fa-9511-46ac-b056-36904529a554
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153431192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4153431192
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.387007100
Short name T753
Test name
Test status
Simulation time 170942013660 ps
CPU time 402.09 seconds
Started Jul 17 05:34:53 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 201500 kb
Host smart-275c6f05-cb8d-465a-97ac-479282f6e98e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=387007100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.387007100
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3886308785
Short name T210
Test name
Test status
Simulation time 386717408844 ps
CPU time 841.3 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:49:15 PM PDT 24
Peak memory 201612 kb
Host smart-4d039b75-624f-4e06-80e6-0bed42746226
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886308785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3886308785
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2301943692
Short name T230
Test name
Test status
Simulation time 596482021122 ps
CPU time 1375.83 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:58:07 PM PDT 24
Peak memory 201592 kb
Host smart-850e4087-f79d-459f-b940-aa140d6245d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301943692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2301943692
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1169401060
Short name T307
Test name
Test status
Simulation time 70140959692 ps
CPU time 270.28 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:39:42 PM PDT 24
Peak memory 201964 kb
Host smart-a451783e-9582-488e-8f24-28f425136395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169401060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1169401060
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1669156878
Short name T454
Test name
Test status
Simulation time 40709852971 ps
CPU time 24.2 seconds
Started Jul 17 05:35:07 PM PDT 24
Finished Jul 17 05:35:33 PM PDT 24
Peak memory 201280 kb
Host smart-f03868e3-bb92-4bb8-a308-5f8e019b496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669156878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1669156878
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3913934620
Short name T352
Test name
Test status
Simulation time 5124689082 ps
CPU time 13.41 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:35:27 PM PDT 24
Peak memory 201336 kb
Host smart-9674ed48-0219-436f-afc8-e73cf846545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913934620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3913934620
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.929754504
Short name T460
Test name
Test status
Simulation time 5919282074 ps
CPU time 5.57 seconds
Started Jul 17 05:34:45 PM PDT 24
Finished Jul 17 05:34:51 PM PDT 24
Peak memory 201268 kb
Host smart-8cc650ae-90a4-4360-a62d-ac8a93e1fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929754504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.929754504
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1164437699
Short name T292
Test name
Test status
Simulation time 574833234831 ps
CPU time 286.54 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:40:03 PM PDT 24
Peak memory 201416 kb
Host smart-6676ea47-6b30-4014-aa06-65e2cd32ae87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164437699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1164437699
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1284553588
Short name T735
Test name
Test status
Simulation time 398549606 ps
CPU time 1.48 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:35:11 PM PDT 24
Peak memory 201268 kb
Host smart-b3e87ee6-8c38-4394-9270-91e6831fd011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284553588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1284553588
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2169197992
Short name T205
Test name
Test status
Simulation time 200156758891 ps
CPU time 19.59 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:35:35 PM PDT 24
Peak memory 201544 kb
Host smart-19256834-43ec-4216-a578-2d27731fdf9f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169197992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2169197992
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3482182611
Short name T303
Test name
Test status
Simulation time 179273795303 ps
CPU time 111.73 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:37:05 PM PDT 24
Peak memory 201520 kb
Host smart-500a715d-9442-461e-aeec-822bec8f54d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482182611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3482182611
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.69157539
Short name T497
Test name
Test status
Simulation time 495590277985 ps
CPU time 1234.8 seconds
Started Jul 17 05:35:13 PM PDT 24
Finished Jul 17 05:55:49 PM PDT 24
Peak memory 201500 kb
Host smart-2ca733e8-93d1-4198-9ebe-781435f6eb0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=69157539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt
_fixed.69157539
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1229036712
Short name T154
Test name
Test status
Simulation time 332756884945 ps
CPU time 824.53 seconds
Started Jul 17 05:35:13 PM PDT 24
Finished Jul 17 05:48:59 PM PDT 24
Peak memory 201540 kb
Host smart-32b9beaa-6ded-4493-8ee9-40af2d24d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229036712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1229036712
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1927809504
Short name T329
Test name
Test status
Simulation time 331027195158 ps
CPU time 813.31 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 201328 kb
Host smart-048f3450-46c6-4a89-a149-37f6bdd5d785
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927809504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1927809504
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.878237995
Short name T373
Test name
Test status
Simulation time 190441720463 ps
CPU time 120.07 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:37:13 PM PDT 24
Peak memory 201536 kb
Host smart-2c8157cc-62a3-4a23-9d13-cdb735bf6707
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878237995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.878237995
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3949529925
Short name T79
Test name
Test status
Simulation time 94309395983 ps
CPU time 492.9 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:43:23 PM PDT 24
Peak memory 201896 kb
Host smart-4081706e-9684-4077-a5f7-c1e2adea01d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949529925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3949529925
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.118164240
Short name T683
Test name
Test status
Simulation time 46184609211 ps
CPU time 112.28 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:37:05 PM PDT 24
Peak memory 201328 kb
Host smart-8e7cc912-72bc-4e2d-af32-116961980490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118164240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.118164240
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.922580584
Short name T337
Test name
Test status
Simulation time 4805566628 ps
CPU time 3.67 seconds
Started Jul 17 05:35:08 PM PDT 24
Finished Jul 17 05:35:13 PM PDT 24
Peak memory 201328 kb
Host smart-72d08500-31fe-4cfd-a298-afbe452fe842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922580584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.922580584
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3859172186
Short name T579
Test name
Test status
Simulation time 5707291623 ps
CPU time 12.77 seconds
Started Jul 17 05:35:08 PM PDT 24
Finished Jul 17 05:35:22 PM PDT 24
Peak memory 201272 kb
Host smart-540c87e6-8b44-4fc0-b6cb-f2a287c933eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859172186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3859172186
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1482778360
Short name T424
Test name
Test status
Simulation time 269576666567 ps
CPU time 1278.2 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:56:29 PM PDT 24
Peak memory 210100 kb
Host smart-d94ec612-5c11-4cd0-8143-a81f6ad41237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482778360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1482778360
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.451234729
Short name T59
Test name
Test status
Simulation time 330178103471 ps
CPU time 194.7 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:38:29 PM PDT 24
Peak memory 210232 kb
Host smart-3c88dde9-2e8f-45f2-b3b9-fcd726546ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451234729 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.451234729
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4272955695
Short name T763
Test name
Test status
Simulation time 531849960 ps
CPU time 0.89 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:35:12 PM PDT 24
Peak memory 201240 kb
Host smart-f7fe3c9d-5660-450a-ab19-f724f847be15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272955695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4272955695
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4261591240
Short name T504
Test name
Test status
Simulation time 261747739383 ps
CPU time 162.33 seconds
Started Jul 17 05:35:07 PM PDT 24
Finished Jul 17 05:37:50 PM PDT 24
Peak memory 201464 kb
Host smart-c541e57b-8e62-4af1-aa52-50b90145a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261591240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4261591240
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2272460298
Short name T164
Test name
Test status
Simulation time 489824592214 ps
CPU time 78.14 seconds
Started Jul 17 05:35:13 PM PDT 24
Finished Jul 17 05:36:32 PM PDT 24
Peak memory 201564 kb
Host smart-44dc586f-5df8-42d3-ad9a-2dfb85f6f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272460298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2272460298
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3217188429
Short name T561
Test name
Test status
Simulation time 167738219007 ps
CPU time 31.87 seconds
Started Jul 17 05:35:07 PM PDT 24
Finished Jul 17 05:35:40 PM PDT 24
Peak memory 201480 kb
Host smart-3560d127-8c56-47ea-831b-70775c9d9fd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217188429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3217188429
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1615954911
Short name T544
Test name
Test status
Simulation time 169213783535 ps
CPU time 357.46 seconds
Started Jul 17 05:35:10 PM PDT 24
Finished Jul 17 05:41:09 PM PDT 24
Peak memory 201504 kb
Host smart-ed1b77c7-355a-4a2a-a52a-3486cf3b54a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615954911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1615954911
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3753762719
Short name T417
Test name
Test status
Simulation time 491750706300 ps
CPU time 312.6 seconds
Started Jul 17 05:35:10 PM PDT 24
Finished Jul 17 05:40:24 PM PDT 24
Peak memory 201572 kb
Host smart-a0fbac86-5fc8-4ed8-b6a3-e7a5073ead4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753762719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3753762719
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2838309394
Short name T262
Test name
Test status
Simulation time 366263484380 ps
CPU time 81.74 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:36:37 PM PDT 24
Peak memory 201552 kb
Host smart-aca27f9e-a3aa-4e14-8b3a-056466619d3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838309394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2838309394
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3783191884
Short name T382
Test name
Test status
Simulation time 196237024525 ps
CPU time 188.53 seconds
Started Jul 17 05:35:10 PM PDT 24
Finished Jul 17 05:38:20 PM PDT 24
Peak memory 201576 kb
Host smart-0499d569-962b-4f1e-8b78-4c56ab4467bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783191884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3783191884
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3625224050
Short name T678
Test name
Test status
Simulation time 98478320452 ps
CPU time 508.5 seconds
Started Jul 17 05:35:09 PM PDT 24
Finished Jul 17 05:43:39 PM PDT 24
Peak memory 201848 kb
Host smart-5de76192-9bff-4c04-9246-210cbf666e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625224050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3625224050
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.336638031
Short name T356
Test name
Test status
Simulation time 20875953112 ps
CPU time 23.31 seconds
Started Jul 17 05:35:16 PM PDT 24
Finished Jul 17 05:35:40 PM PDT 24
Peak memory 201256 kb
Host smart-bf1bf487-fe25-4693-88c7-52b52ce70654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336638031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.336638031
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1043791487
Short name T779
Test name
Test status
Simulation time 4162905465 ps
CPU time 10.7 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:35:26 PM PDT 24
Peak memory 201288 kb
Host smart-22604ff2-c6f1-48e3-ae38-cde9da0e07a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043791487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1043791487
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4016058027
Short name T791
Test name
Test status
Simulation time 5755997274 ps
CPU time 14.56 seconds
Started Jul 17 05:35:08 PM PDT 24
Finished Jul 17 05:35:23 PM PDT 24
Peak memory 201244 kb
Host smart-98b43b85-f71f-414e-815d-92dab04d112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016058027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4016058027
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.604039455
Short name T43
Test name
Test status
Simulation time 205532624908 ps
CPU time 440.66 seconds
Started Jul 17 05:35:10 PM PDT 24
Finished Jul 17 05:42:32 PM PDT 24
Peak memory 201512 kb
Host smart-f4777a92-1757-4048-8364-8ca1d93e80b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604039455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
604039455
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.634466538
Short name T20
Test name
Test status
Simulation time 20737375618 ps
CPU time 47.37 seconds
Started Jul 17 05:35:07 PM PDT 24
Finished Jul 17 05:35:56 PM PDT 24
Peak memory 201640 kb
Host smart-ace8fd19-a77d-4456-bc69-4ecea17fe5b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634466538 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.634466538
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3738243511
Short name T553
Test name
Test status
Simulation time 471819583 ps
CPU time 1.64 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:35:17 PM PDT 24
Peak memory 201224 kb
Host smart-f5d57987-de12-4299-a058-93bb42643afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738243511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3738243511
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3904543162
Short name T270
Test name
Test status
Simulation time 174088695216 ps
CPU time 429.63 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:42:22 PM PDT 24
Peak memory 201512 kb
Host smart-f65a7fe9-a11a-4f00-bb52-1205e0815cb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904543162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3904543162
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3824981163
Short name T12
Test name
Test status
Simulation time 162448770880 ps
CPU time 340.42 seconds
Started Jul 17 05:35:13 PM PDT 24
Finished Jul 17 05:40:54 PM PDT 24
Peak memory 201492 kb
Host smart-82fe98b0-304e-4768-a22e-ceb490bde3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824981163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3824981163
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2750580962
Short name T353
Test name
Test status
Simulation time 501364753771 ps
CPU time 237.35 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:39:09 PM PDT 24
Peak memory 201508 kb
Host smart-3a990cf2-f9a4-4ace-8be4-334938cffd61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750580962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2750580962
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.976826781
Short name T581
Test name
Test status
Simulation time 331635702220 ps
CPU time 729.6 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:47:22 PM PDT 24
Peak memory 201536 kb
Host smart-6db210f1-98a3-4218-a97e-c0c444663b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976826781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.976826781
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3426246854
Short name T416
Test name
Test status
Simulation time 325401390813 ps
CPU time 774.71 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:48:08 PM PDT 24
Peak memory 201544 kb
Host smart-062a7c67-305c-47fa-bd6e-1ec1b4a7c0f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426246854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3426246854
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2193940007
Short name T582
Test name
Test status
Simulation time 611873133985 ps
CPU time 259.77 seconds
Started Jul 17 05:35:13 PM PDT 24
Finished Jul 17 05:39:34 PM PDT 24
Peak memory 201536 kb
Host smart-47577e69-26be-48dd-a50a-09efea10ec14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193940007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2193940007
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2216234768
Short name T707
Test name
Test status
Simulation time 120309334334 ps
CPU time 517.85 seconds
Started Jul 17 05:35:12 PM PDT 24
Finished Jul 17 05:43:51 PM PDT 24
Peak memory 201912 kb
Host smart-e3caa588-2ba3-40fc-8202-b83f011913f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216234768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2216234768
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2077906342
Short name T342
Test name
Test status
Simulation time 25505860107 ps
CPU time 30.93 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:35:47 PM PDT 24
Peak memory 201280 kb
Host smart-d186e2ce-9585-47ac-bd9d-87e336c1710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077906342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2077906342
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2914078145
Short name T462
Test name
Test status
Simulation time 4223543560 ps
CPU time 9.67 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:35:26 PM PDT 24
Peak memory 201276 kb
Host smart-74490bb1-697f-4c73-83af-7856c5d0630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914078145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2914078145
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3328807024
Short name T723
Test name
Test status
Simulation time 5728522653 ps
CPU time 2.46 seconds
Started Jul 17 05:35:16 PM PDT 24
Finished Jul 17 05:35:19 PM PDT 24
Peak memory 201272 kb
Host smart-b0a00a92-c804-43f9-88f4-2b535c778015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328807024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3328807024
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3357773806
Short name T145
Test name
Test status
Simulation time 325514065507 ps
CPU time 68.61 seconds
Started Jul 17 05:35:16 PM PDT 24
Finished Jul 17 05:36:25 PM PDT 24
Peak memory 201536 kb
Host smart-ec161510-485f-4a55-b486-ede8e9e58df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357773806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3357773806
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.142142107
Short name T672
Test name
Test status
Simulation time 58619576516 ps
CPU time 103.58 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:36:59 PM PDT 24
Peak memory 210280 kb
Host smart-e7f8328e-4bb0-4c48-a854-8baeff375329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142142107 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.142142107
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3506052715
Short name T386
Test name
Test status
Simulation time 308873362 ps
CPU time 0.77 seconds
Started Jul 17 05:35:17 PM PDT 24
Finished Jul 17 05:35:19 PM PDT 24
Peak memory 201284 kb
Host smart-30da1be9-a1c5-4fd7-ad34-7702f4ad27b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506052715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3506052715
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1807451570
Short name T301
Test name
Test status
Simulation time 196788149444 ps
CPU time 102.15 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:37:01 PM PDT 24
Peak memory 201532 kb
Host smart-f909c204-b09a-4bfb-bb2c-2ac715f1b29f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807451570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1807451570
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4239085915
Short name T300
Test name
Test status
Simulation time 169758794400 ps
CPU time 380.95 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:41:38 PM PDT 24
Peak memory 201536 kb
Host smart-90c86a77-df0f-40ca-b961-f989c9a42751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239085915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4239085915
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.923601025
Short name T226
Test name
Test status
Simulation time 330261383576 ps
CPU time 767.98 seconds
Started Jul 17 05:35:20 PM PDT 24
Finished Jul 17 05:48:09 PM PDT 24
Peak memory 201524 kb
Host smart-007d56dd-b5fe-4f99-8598-fb2e46ade3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923601025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.923601025
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2032082556
Short name T152
Test name
Test status
Simulation time 494817485914 ps
CPU time 1075.05 seconds
Started Jul 17 05:35:17 PM PDT 24
Finished Jul 17 05:53:13 PM PDT 24
Peak memory 201512 kb
Host smart-20a7fb6d-9307-4920-9638-d82d8947d0fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032082556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2032082556
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.4205001374
Short name T169
Test name
Test status
Simulation time 494586200839 ps
CPU time 203.5 seconds
Started Jul 17 05:35:15 PM PDT 24
Finished Jul 17 05:38:39 PM PDT 24
Peak memory 201532 kb
Host smart-03be9e46-27a6-4fcb-a659-c54246b28adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205001374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4205001374
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3517261951
Short name T421
Test name
Test status
Simulation time 326717215652 ps
CPU time 677.23 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:46:32 PM PDT 24
Peak memory 201504 kb
Host smart-b54cf1f9-67cf-4eb7-be40-cfcd049d95c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517261951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3517261951
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.239338286
Short name T184
Test name
Test status
Simulation time 567708591767 ps
CPU time 338.84 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:40:51 PM PDT 24
Peak memory 201540 kb
Host smart-4d9d92eb-1d0e-4e6f-9566-d1e19d20338b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239338286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.239338286
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.257755948
Short name T430
Test name
Test status
Simulation time 205099760106 ps
CPU time 149.33 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:37:42 PM PDT 24
Peak memory 201592 kb
Host smart-91615673-35f8-4a9c-b546-df5e21b6b34d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257755948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.257755948
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2349141758
Short name T772
Test name
Test status
Simulation time 93479382082 ps
CPU time 510.4 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:43:50 PM PDT 24
Peak memory 201892 kb
Host smart-7abbee1f-e67b-4081-81f7-bcfcc9c24d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349141758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2349141758
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.178001090
Short name T463
Test name
Test status
Simulation time 46438617927 ps
CPU time 48.82 seconds
Started Jul 17 05:35:16 PM PDT 24
Finished Jul 17 05:36:06 PM PDT 24
Peak memory 201328 kb
Host smart-39791f15-21a9-4012-a353-bf3be2abbfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178001090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.178001090
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.609657671
Short name T489
Test name
Test status
Simulation time 4389940642 ps
CPU time 10.35 seconds
Started Jul 17 05:35:17 PM PDT 24
Finished Jul 17 05:35:28 PM PDT 24
Peak memory 201324 kb
Host smart-27662b3e-1927-4aff-81de-25469b0e9ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609657671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.609657671
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1447902448
Short name T625
Test name
Test status
Simulation time 6058634838 ps
CPU time 4.54 seconds
Started Jul 17 05:35:11 PM PDT 24
Finished Jul 17 05:35:17 PM PDT 24
Peak memory 201328 kb
Host smart-2a0abe5e-fa27-4a32-a6c1-ce33a9dc5547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447902448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1447902448
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.391875398
Short name T293
Test name
Test status
Simulation time 167863171489 ps
CPU time 139.28 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:37:38 PM PDT 24
Peak memory 201516 kb
Host smart-da1edb09-02d6-436d-83e7-b68922c39f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391875398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
391875398
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2400839863
Short name T410
Test name
Test status
Simulation time 21609691964 ps
CPU time 55.95 seconds
Started Jul 17 05:35:17 PM PDT 24
Finished Jul 17 05:36:14 PM PDT 24
Peak memory 210252 kb
Host smart-d1022133-4b34-4aff-a091-3a764822ec9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400839863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2400839863
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3663871954
Short name T378
Test name
Test status
Simulation time 342275692 ps
CPU time 1.04 seconds
Started Jul 17 05:35:21 PM PDT 24
Finished Jul 17 05:35:24 PM PDT 24
Peak memory 201220 kb
Host smart-2293a3af-95e4-425a-b6c6-d7464dba138a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663871954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3663871954
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3378509782
Short name T170
Test name
Test status
Simulation time 348169104337 ps
CPU time 84.38 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:36:39 PM PDT 24
Peak memory 201524 kb
Host smart-e7d51512-c105-44cf-a2c2-860d90b3b790
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378509782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3378509782
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2815922273
Short name T253
Test name
Test status
Simulation time 330265228140 ps
CPU time 120.86 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:37:20 PM PDT 24
Peak memory 201616 kb
Host smart-003a682d-46e4-4a6a-8b77-d89dd060cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815922273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2815922273
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1107102886
Short name T333
Test name
Test status
Simulation time 488205696932 ps
CPU time 1065.92 seconds
Started Jul 17 05:35:13 PM PDT 24
Finished Jul 17 05:53:01 PM PDT 24
Peak memory 201444 kb
Host smart-783df39b-7ad4-4ba5-9671-9e4f9bc87740
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107102886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1107102886
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1885984722
Short name T774
Test name
Test status
Simulation time 330233100380 ps
CPU time 762.2 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:48:02 PM PDT 24
Peak memory 201548 kb
Host smart-46860aca-638c-42e4-9184-1c8b19b0ce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885984722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1885984722
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3624705068
Short name T326
Test name
Test status
Simulation time 167770047257 ps
CPU time 96.86 seconds
Started Jul 17 05:35:17 PM PDT 24
Finished Jul 17 05:36:55 PM PDT 24
Peak memory 201528 kb
Host smart-c9036f71-1e28-4680-96b2-8d8769759da7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624705068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3624705068
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4101937348
Short name T216
Test name
Test status
Simulation time 166994671040 ps
CPU time 379.79 seconds
Started Jul 17 05:35:18 PM PDT 24
Finished Jul 17 05:41:39 PM PDT 24
Peak memory 201544 kb
Host smart-365e0704-dafc-4f23-ab12-df9491afef46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101937348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4101937348
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3672004981
Short name T335
Test name
Test status
Simulation time 205642751287 ps
CPU time 252.68 seconds
Started Jul 17 05:35:17 PM PDT 24
Finished Jul 17 05:39:31 PM PDT 24
Peak memory 201524 kb
Host smart-76b7f668-1a3b-4d39-b72e-700662ada88f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672004981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3672004981
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2885546648
Short name T784
Test name
Test status
Simulation time 97693433472 ps
CPU time 330.86 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:41:03 PM PDT 24
Peak memory 201824 kb
Host smart-fd37a9c6-4c70-4bdd-b139-607432118fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885546648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2885546648
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2728615113
Short name T377
Test name
Test status
Simulation time 29421206099 ps
CPU time 18.28 seconds
Started Jul 17 05:35:31 PM PDT 24
Finished Jul 17 05:35:51 PM PDT 24
Peak memory 200844 kb
Host smart-583b9d63-929c-4bb7-938a-d11376c8eefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728615113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2728615113
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4197824851
Short name T789
Test name
Test status
Simulation time 4311094459 ps
CPU time 11.46 seconds
Started Jul 17 05:35:25 PM PDT 24
Finished Jul 17 05:35:38 PM PDT 24
Peak memory 201328 kb
Host smart-83317c87-a634-4f80-acb7-22d840d77b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197824851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4197824851
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3711647968
Short name T516
Test name
Test status
Simulation time 5935087535 ps
CPU time 2.45 seconds
Started Jul 17 05:35:14 PM PDT 24
Finished Jul 17 05:35:17 PM PDT 24
Peak memory 201344 kb
Host smart-16c99d6b-ab7f-4fc3-acdb-b2e4ebfa1642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711647968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3711647968
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.719071029
Short name T283
Test name
Test status
Simulation time 190246687733 ps
CPU time 104.22 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:37:16 PM PDT 24
Peak memory 201520 kb
Host smart-758efc5c-3015-4d75-b200-29fa86c62744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719071029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
719071029
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2256850396
Short name T493
Test name
Test status
Simulation time 116821747339 ps
CPU time 148.18 seconds
Started Jul 17 05:35:25 PM PDT 24
Finished Jul 17 05:37:55 PM PDT 24
Peak memory 202020 kb
Host smart-da01160d-80bb-41b9-99f7-7fb4f6ba0f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256850396 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2256850396
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1609984900
Short name T762
Test name
Test status
Simulation time 501859172 ps
CPU time 1.23 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:33:55 PM PDT 24
Peak memory 201280 kb
Host smart-db57e350-c7b1-42d5-9b43-ac22e67c1987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609984900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1609984900
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2144411200
Short name T209
Test name
Test status
Simulation time 498424011004 ps
CPU time 1004.48 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:48:40 PM PDT 24
Peak memory 201532 kb
Host smart-f639e9ff-b7bb-4d41-ab69-48bfd2e86864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144411200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2144411200
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.867697883
Short name T607
Test name
Test status
Simulation time 551534137656 ps
CPU time 665.66 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:43:01 PM PDT 24
Peak memory 201528 kb
Host smart-29e40138-9cf1-4a2e-b05a-6383a74eb5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867697883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.867697883
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.285338691
Short name T644
Test name
Test status
Simulation time 166411200724 ps
CPU time 102.72 seconds
Started Jul 17 05:31:53 PM PDT 24
Finished Jul 17 05:33:37 PM PDT 24
Peak memory 201524 kb
Host smart-82cd2c53-288a-4919-bdb1-4cf788a63d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285338691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.285338691
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2832177710
Short name T187
Test name
Test status
Simulation time 496017883847 ps
CPU time 106.74 seconds
Started Jul 17 05:31:52 PM PDT 24
Finished Jul 17 05:33:39 PM PDT 24
Peak memory 201440 kb
Host smart-4fe3e11d-ffed-4e20-b7b8-f281ed7c98b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832177710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2832177710
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.108630385
Short name T155
Test name
Test status
Simulation time 168266387178 ps
CPU time 177.77 seconds
Started Jul 17 05:31:44 PM PDT 24
Finished Jul 17 05:34:43 PM PDT 24
Peak memory 201548 kb
Host smart-ea2b7e0e-0a51-430f-8b5a-552276b8b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108630385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.108630385
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3918978797
Short name T413
Test name
Test status
Simulation time 335018055105 ps
CPU time 684.82 seconds
Started Jul 17 05:31:46 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 201528 kb
Host smart-d24623af-9eef-4c2d-9679-f78749c04630
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918978797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3918978797
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1075450693
Short name T241
Test name
Test status
Simulation time 278508993636 ps
CPU time 669.88 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:45:04 PM PDT 24
Peak memory 201552 kb
Host smart-543dc5fc-6574-4adc-ae31-f6cde4a84d9f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075450693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1075450693
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1784772326
Short name T594
Test name
Test status
Simulation time 382463508980 ps
CPU time 450.45 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:39:25 PM PDT 24
Peak memory 201520 kb
Host smart-36c495b7-fc73-48c7-a2e8-8b54dc3f8a6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784772326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1784772326
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.678262455
Short name T647
Test name
Test status
Simulation time 33666801356 ps
CPU time 69.19 seconds
Started Jul 17 05:31:52 PM PDT 24
Finished Jul 17 05:33:02 PM PDT 24
Peak memory 201332 kb
Host smart-38b4eb37-2613-411d-9e5e-cd8c6bbff441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678262455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.678262455
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.818238731
Short name T628
Test name
Test status
Simulation time 4910981364 ps
CPU time 10.89 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:16 PM PDT 24
Peak memory 201348 kb
Host smart-6cf20ded-183f-4a44-988f-a2e5f7993193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818238731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.818238731
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3011974169
Short name T58
Test name
Test status
Simulation time 4275894633 ps
CPU time 3.58 seconds
Started Jul 17 05:31:56 PM PDT 24
Finished Jul 17 05:32:00 PM PDT 24
Peak memory 217068 kb
Host smart-3df61608-eb4c-4f69-b74b-70b98f10dc5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011974169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3011974169
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.916989207
Short name T731
Test name
Test status
Simulation time 5526219674 ps
CPU time 4.4 seconds
Started Jul 17 05:31:44 PM PDT 24
Finished Jul 17 05:31:49 PM PDT 24
Peak memory 201344 kb
Host smart-715c51f4-c2ab-4fc5-ae15-fb975d1e087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916989207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.916989207
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3017308943
Short name T587
Test name
Test status
Simulation time 366142268259 ps
CPU time 881.38 seconds
Started Jul 17 05:31:55 PM PDT 24
Finished Jul 17 05:46:37 PM PDT 24
Peak memory 201520 kb
Host smart-1c1a87fd-5cf1-4552-88ee-90ca7486c24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017308943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3017308943
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2407689485
Short name T66
Test name
Test status
Simulation time 429433944 ps
CPU time 0.88 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:35:32 PM PDT 24
Peak memory 201280 kb
Host smart-35583faa-af6c-4526-a1ef-982f98b6b804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407689485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2407689485
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1999323407
Short name T162
Test name
Test status
Simulation time 163078395608 ps
CPU time 385.99 seconds
Started Jul 17 05:35:28 PM PDT 24
Finished Jul 17 05:41:55 PM PDT 24
Peak memory 201560 kb
Host smart-1f7a14d4-bc49-460c-bc6f-d8350c4517cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999323407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1999323407
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.145992470
Short name T191
Test name
Test status
Simulation time 164373845915 ps
CPU time 103.93 seconds
Started Jul 17 05:35:22 PM PDT 24
Finished Jul 17 05:37:07 PM PDT 24
Peak memory 201548 kb
Host smart-dd903a2a-fef2-4176-9d54-01c0998c2268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145992470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.145992470
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2720893365
Short name T633
Test name
Test status
Simulation time 161800666737 ps
CPU time 99.56 seconds
Started Jul 17 05:35:26 PM PDT 24
Finished Jul 17 05:37:07 PM PDT 24
Peak memory 200312 kb
Host smart-202fdb55-1aa0-4cae-97f7-995ac4fac499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720893365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2720893365
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2245473545
Short name T688
Test name
Test status
Simulation time 499609273880 ps
CPU time 1180.26 seconds
Started Jul 17 05:35:32 PM PDT 24
Finished Jul 17 05:55:14 PM PDT 24
Peak memory 201468 kb
Host smart-9c56d4e0-e495-4a7b-94f1-39eb2330e29d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245473545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2245473545
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2336649297
Short name T177
Test name
Test status
Simulation time 493533307507 ps
CPU time 299.01 seconds
Started Jul 17 05:35:23 PM PDT 24
Finished Jul 17 05:40:23 PM PDT 24
Peak memory 201532 kb
Host smart-7451c574-c142-4418-b9ce-acd1f28b99ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336649297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2336649297
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.85109449
Short name T328
Test name
Test status
Simulation time 501246243580 ps
CPU time 267.89 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:39:58 PM PDT 24
Peak memory 201528 kb
Host smart-01ef4f4d-9745-4810-b2f4-5fc53727cbe3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=85109449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed
.85109449
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1971354794
Short name T94
Test name
Test status
Simulation time 383002772673 ps
CPU time 810.73 seconds
Started Jul 17 05:35:26 PM PDT 24
Finished Jul 17 05:48:58 PM PDT 24
Peak memory 201536 kb
Host smart-323411b2-ed7b-4378-8233-a1edef355337
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971354794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1971354794
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.47468660
Short name T438
Test name
Test status
Simulation time 593045449274 ps
CPU time 194.2 seconds
Started Jul 17 05:35:21 PM PDT 24
Finished Jul 17 05:38:37 PM PDT 24
Peak memory 201516 kb
Host smart-4f9c18eb-7019-415b-bdfc-0411ca581b78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47468660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.a
dc_ctrl_filters_wakeup_fixed.47468660
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2467537270
Short name T657
Test name
Test status
Simulation time 83856325686 ps
CPU time 297.24 seconds
Started Jul 17 05:35:22 PM PDT 24
Finished Jul 17 05:40:20 PM PDT 24
Peak memory 201920 kb
Host smart-eadb01de-6c64-4857-96a1-abfba7aec46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467537270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2467537270
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2315752575
Short name T589
Test name
Test status
Simulation time 44116220401 ps
CPU time 16.65 seconds
Started Jul 17 05:35:27 PM PDT 24
Finished Jul 17 05:35:45 PM PDT 24
Peak memory 201252 kb
Host smart-0e061e8b-1b8e-4c4f-98c5-7fd1c37dd0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315752575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2315752575
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.113510820
Short name T783
Test name
Test status
Simulation time 4777314894 ps
CPU time 11.04 seconds
Started Jul 17 05:35:31 PM PDT 24
Finished Jul 17 05:35:43 PM PDT 24
Peak memory 201208 kb
Host smart-a3e83981-3f0a-4d07-afa7-e30cf0e3ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113510820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.113510820
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2918321696
Short name T354
Test name
Test status
Simulation time 5940616109 ps
CPU time 13.49 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:35:45 PM PDT 24
Peak memory 201224 kb
Host smart-3e5a10e9-e3e4-42ad-8151-e5506c8e3a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918321696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2918321696
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3521766647
Short name T19
Test name
Test status
Simulation time 296567765785 ps
CPU time 171.95 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:38:22 PM PDT 24
Peak memory 201596 kb
Host smart-9a553927-bada-4305-880a-b727c9f67579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521766647 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3521766647
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2712404932
Short name T718
Test name
Test status
Simulation time 345382434 ps
CPU time 0.8 seconds
Started Jul 17 05:35:28 PM PDT 24
Finished Jul 17 05:35:30 PM PDT 24
Peak memory 201232 kb
Host smart-0152821f-c5b7-49e7-8f16-3fd9cb27804a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712404932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2712404932
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1946604102
Short name T715
Test name
Test status
Simulation time 163051266988 ps
CPU time 75.06 seconds
Started Jul 17 05:35:27 PM PDT 24
Finished Jul 17 05:36:43 PM PDT 24
Peak memory 201540 kb
Host smart-1d1c00ae-a073-49d7-8d81-f9153e244549
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946604102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1946604102
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1099469791
Short name T133
Test name
Test status
Simulation time 558288575504 ps
CPU time 1318.05 seconds
Started Jul 17 05:35:20 PM PDT 24
Finished Jul 17 05:57:20 PM PDT 24
Peak memory 201528 kb
Host smart-05ada1bd-99dd-4210-a4da-d39f249783ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099469791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1099469791
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.514945266
Short name T229
Test name
Test status
Simulation time 328038577827 ps
CPU time 225.47 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:39:16 PM PDT 24
Peak memory 201536 kb
Host smart-163a5978-1917-4ae6-b22c-7901c38ea191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514945266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.514945266
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.36717889
Short name T332
Test name
Test status
Simulation time 331650316371 ps
CPU time 299.63 seconds
Started Jul 17 05:35:21 PM PDT 24
Finished Jul 17 05:40:22 PM PDT 24
Peak memory 201464 kb
Host smart-f6deb941-7fda-4ab1-85b0-d49e765c5f24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt
_fixed.36717889
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1996392205
Short name T550
Test name
Test status
Simulation time 335889851260 ps
CPU time 76.19 seconds
Started Jul 17 05:35:20 PM PDT 24
Finished Jul 17 05:36:38 PM PDT 24
Peak memory 201476 kb
Host smart-4a591fbd-490b-4a7a-8175-c93204477e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996392205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1996392205
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2196263690
Short name T776
Test name
Test status
Simulation time 165905133648 ps
CPU time 198.69 seconds
Started Jul 17 05:35:26 PM PDT 24
Finished Jul 17 05:38:46 PM PDT 24
Peak memory 201520 kb
Host smart-105143e2-8ca3-4050-828d-fc410e8f0ed4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196263690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2196263690
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3606823094
Short name T523
Test name
Test status
Simulation time 193693113087 ps
CPU time 111.27 seconds
Started Jul 17 05:35:20 PM PDT 24
Finished Jul 17 05:37:12 PM PDT 24
Peak memory 201736 kb
Host smart-ab75a573-28de-4cb7-8705-1a7070a23c3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606823094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3606823094
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1344970739
Short name T400
Test name
Test status
Simulation time 399371350554 ps
CPU time 248.45 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:39:39 PM PDT 24
Peak memory 201448 kb
Host smart-39241a07-f779-4a7e-9a73-5bb809a5fbd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344970739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1344970739
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1154191371
Short name T505
Test name
Test status
Simulation time 135471166908 ps
CPU time 524.39 seconds
Started Jul 17 05:35:21 PM PDT 24
Finished Jul 17 05:44:07 PM PDT 24
Peak memory 201892 kb
Host smart-1dcb75ee-0c2f-46d8-9d78-156c8c030b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154191371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1154191371
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1924411122
Short name T618
Test name
Test status
Simulation time 27287648410 ps
CPU time 5.39 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:35:37 PM PDT 24
Peak memory 201212 kb
Host smart-c8648b0d-28de-42a0-a348-938732eec5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924411122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1924411122
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.501816403
Short name T380
Test name
Test status
Simulation time 2720630363 ps
CPU time 2.19 seconds
Started Jul 17 05:35:28 PM PDT 24
Finished Jul 17 05:35:32 PM PDT 24
Peak memory 201268 kb
Host smart-02a37fe7-7e33-4922-8263-e8533dbf6acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501816403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.501816403
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1101536153
Short name T534
Test name
Test status
Simulation time 5807768658 ps
CPU time 7.89 seconds
Started Jul 17 05:35:20 PM PDT 24
Finished Jul 17 05:35:29 PM PDT 24
Peak memory 201328 kb
Host smart-fd8bc778-a264-47b9-8376-545961f4e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101536153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1101536153
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.827160323
Short name T540
Test name
Test status
Simulation time 743316898819 ps
CPU time 284.96 seconds
Started Jul 17 05:35:21 PM PDT 24
Finished Jul 17 05:40:07 PM PDT 24
Peak memory 201520 kb
Host smart-89b5db8a-bfd4-4c77-a956-bb3fd0b2b5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827160323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
827160323
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1059695711
Short name T202
Test name
Test status
Simulation time 1108851854282 ps
CPU time 442.02 seconds
Started Jul 17 05:35:31 PM PDT 24
Finished Jul 17 05:42:55 PM PDT 24
Peak memory 217108 kb
Host smart-5bfc136c-91cb-4189-9de9-880b0a25ffe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059695711 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1059695711
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3293650584
Short name T490
Test name
Test status
Simulation time 496222186 ps
CPU time 0.96 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:35:33 PM PDT 24
Peak memory 201208 kb
Host smart-90fbdfc6-24d4-42ee-bec6-c740d4f71c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293650584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3293650584
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.462381476
Short name T266
Test name
Test status
Simulation time 361049897170 ps
CPU time 832.5 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:49:25 PM PDT 24
Peak memory 201412 kb
Host smart-ca33a170-2ada-4513-a134-e08aa67e3af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462381476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.462381476
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.618783741
Short name T160
Test name
Test status
Simulation time 328237937580 ps
CPU time 179.75 seconds
Started Jul 17 05:35:28 PM PDT 24
Finished Jul 17 05:38:29 PM PDT 24
Peak memory 201488 kb
Host smart-407d58d2-cacd-4410-b876-1a26e0008dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618783741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.618783741
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2474380302
Short name T367
Test name
Test status
Simulation time 325900545170 ps
CPU time 348.85 seconds
Started Jul 17 05:35:27 PM PDT 24
Finished Jul 17 05:41:17 PM PDT 24
Peak memory 201512 kb
Host smart-2eadc0b8-d40f-49e4-ab55-8c33271c3a7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474380302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2474380302
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3053142287
Short name T760
Test name
Test status
Simulation time 166579518253 ps
CPU time 94.32 seconds
Started Jul 17 05:35:22 PM PDT 24
Finished Jul 17 05:36:57 PM PDT 24
Peak memory 201564 kb
Host smart-5f68ca82-2efa-4a0d-8a4e-c30702013146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053142287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3053142287
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.673641683
Short name T576
Test name
Test status
Simulation time 320874975655 ps
CPU time 747.31 seconds
Started Jul 17 05:35:22 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 201468 kb
Host smart-8fa0a63e-1a56-46cb-8725-2b211cfef194
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=673641683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.673641683
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.268475869
Short name T409
Test name
Test status
Simulation time 182419946408 ps
CPU time 102.26 seconds
Started Jul 17 05:35:25 PM PDT 24
Finished Jul 17 05:37:08 PM PDT 24
Peak memory 201528 kb
Host smart-443fde21-8cd7-4173-93eb-8dbefa1559f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268475869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.268475869
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.857324546
Short name T446
Test name
Test status
Simulation time 600820034990 ps
CPU time 1324.32 seconds
Started Jul 17 05:35:30 PM PDT 24
Finished Jul 17 05:57:36 PM PDT 24
Peak memory 201408 kb
Host smart-0305a986-885a-42b0-8a4f-14a81141cdad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857324546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.857324546
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4229360237
Short name T506
Test name
Test status
Simulation time 118663714598 ps
CPU time 356.02 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:41:27 PM PDT 24
Peak memory 201912 kb
Host smart-eaf4a3ec-d7d0-45cb-9dc7-2c9f10ce7161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229360237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4229360237
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.121652980
Short name T614
Test name
Test status
Simulation time 31709299460 ps
CPU time 37.72 seconds
Started Jul 17 05:35:28 PM PDT 24
Finished Jul 17 05:36:07 PM PDT 24
Peak memory 201336 kb
Host smart-f2082bc6-433c-4496-8c59-acf484a9fdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121652980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.121652980
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.520961063
Short name T9
Test name
Test status
Simulation time 4691112045 ps
CPU time 10.71 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:35:41 PM PDT 24
Peak memory 201288 kb
Host smart-0a7aa80c-0cc3-4489-b1e5-5eac954d4a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520961063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.520961063
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.285851076
Short name T491
Test name
Test status
Simulation time 6163592730 ps
CPU time 4.62 seconds
Started Jul 17 05:35:29 PM PDT 24
Finished Jul 17 05:35:35 PM PDT 24
Peak memory 201332 kb
Host smart-72128384-8d8d-4db2-a53d-c82e1b59ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285851076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.285851076
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2047630281
Short name T675
Test name
Test status
Simulation time 118290382166 ps
CPU time 267.45 seconds
Started Jul 17 05:35:26 PM PDT 24
Finished Jul 17 05:39:55 PM PDT 24
Peak memory 208836 kb
Host smart-79c6a823-12f5-43e1-82ce-1ca2fef9db0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047630281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2047630281
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.501619868
Short name T665
Test name
Test status
Simulation time 352848482 ps
CPU time 0.83 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:35:41 PM PDT 24
Peak memory 201276 kb
Host smart-969dfc4e-e7a5-4719-98a4-0293bb9e513d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501619868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.501619868
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2732276295
Short name T757
Test name
Test status
Simulation time 182351348941 ps
CPU time 93.6 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:37:11 PM PDT 24
Peak memory 201512 kb
Host smart-6fcba1ee-50d0-413c-ac34-9c940f7d0984
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732276295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2732276295
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4116343348
Short name T520
Test name
Test status
Simulation time 540259463480 ps
CPU time 1184.13 seconds
Started Jul 17 05:35:35 PM PDT 24
Finished Jul 17 05:55:20 PM PDT 24
Peak memory 201516 kb
Host smart-0ef3d14b-6908-4103-97f2-818f33c7ec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116343348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4116343348
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3971816543
Short name T148
Test name
Test status
Simulation time 332221299227 ps
CPU time 196.49 seconds
Started Jul 17 05:35:37 PM PDT 24
Finished Jul 17 05:38:54 PM PDT 24
Peak memory 201524 kb
Host smart-d4d564c0-9ec9-4498-b51c-8a3bb130ba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971816543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3971816543
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1525527536
Short name T492
Test name
Test status
Simulation time 322256298095 ps
CPU time 208.63 seconds
Started Jul 17 05:35:41 PM PDT 24
Finished Jul 17 05:39:11 PM PDT 24
Peak memory 201456 kb
Host smart-ba9ea424-646a-42fe-b2de-f51e1faed675
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525527536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1525527536
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2914031990
Short name T488
Test name
Test status
Simulation time 159994667991 ps
CPU time 186.14 seconds
Started Jul 17 05:35:40 PM PDT 24
Finished Jul 17 05:38:47 PM PDT 24
Peak memory 201592 kb
Host smart-defa4dfa-0059-416e-9e53-ee91d5b9bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914031990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2914031990
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1560023043
Short name T376
Test name
Test status
Simulation time 495417112540 ps
CPU time 326.35 seconds
Started Jul 17 05:35:42 PM PDT 24
Finished Jul 17 05:41:09 PM PDT 24
Peak memory 201516 kb
Host smart-a1ce9f8e-85d0-48e8-8595-ef8b266e3cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560023043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1560023043
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2291241821
Short name T231
Test name
Test status
Simulation time 367170987909 ps
CPU time 395.78 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:42:14 PM PDT 24
Peak memory 201552 kb
Host smart-aee4c035-917c-4ed3-8df5-e1afc98c0151
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291241821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2291241821
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.24685364
Short name T471
Test name
Test status
Simulation time 208203967559 ps
CPU time 460.7 seconds
Started Jul 17 05:35:35 PM PDT 24
Finished Jul 17 05:43:16 PM PDT 24
Peak memory 201512 kb
Host smart-078cde76-e6bd-4500-b4c9-c13db3960b04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24685364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
dc_ctrl_filters_wakeup_fixed.24685364
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3290317406
Short name T442
Test name
Test status
Simulation time 127215648975 ps
CPU time 437.48 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:42:57 PM PDT 24
Peak memory 201908 kb
Host smart-bebc10fd-2fd4-4447-93da-01d5342b42d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290317406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3290317406
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2015537761
Short name T357
Test name
Test status
Simulation time 32031508103 ps
CPU time 74.8 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:36:54 PM PDT 24
Peak memory 201328 kb
Host smart-736fb681-3c76-4da0-bf74-a5dd0e760ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015537761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2015537761
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3229489939
Short name T101
Test name
Test status
Simulation time 4217843752 ps
CPU time 8.97 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:35:48 PM PDT 24
Peak memory 201264 kb
Host smart-325c7380-2044-4b97-b343-4f8dbd7a83f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229489939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3229489939
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.626668614
Short name T347
Test name
Test status
Simulation time 5616497140 ps
CPU time 4.31 seconds
Started Jul 17 05:35:27 PM PDT 24
Finished Jul 17 05:35:32 PM PDT 24
Peak memory 201332 kb
Host smart-094bf20b-a48c-47f4-a750-3c0faad3f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626668614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.626668614
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4260554059
Short name T159
Test name
Test status
Simulation time 503368813628 ps
CPU time 300.76 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:40:38 PM PDT 24
Peak memory 201540 kb
Host smart-61c6725d-25fd-46e0-bee5-d1b5d88fcc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260554059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4260554059
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2375081073
Short name T65
Test name
Test status
Simulation time 378299326 ps
CPU time 0.72 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:36:06 PM PDT 24
Peak memory 201188 kb
Host smart-fe600c09-1df7-464f-b668-ca070722cda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375081073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2375081073
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1249216685
Short name T207
Test name
Test status
Simulation time 547306988554 ps
CPU time 1289.82 seconds
Started Jul 17 05:35:37 PM PDT 24
Finished Jul 17 05:57:08 PM PDT 24
Peak memory 201532 kb
Host smart-cda34ceb-07ad-49ea-9b2b-b64adac4e85b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249216685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1249216685
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1487840652
Short name T106
Test name
Test status
Simulation time 519943088598 ps
CPU time 854.59 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:49:52 PM PDT 24
Peak memory 201548 kb
Host smart-c9199ddc-c0ef-455c-be85-0bd458fc3b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487840652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1487840652
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2311636996
Short name T476
Test name
Test status
Simulation time 494634027777 ps
CPU time 304.26 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:40:43 PM PDT 24
Peak memory 201508 kb
Host smart-9703a6cb-3e42-4572-8e60-312345678ed9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311636996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2311636996
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.173087706
Short name T745
Test name
Test status
Simulation time 163133403915 ps
CPU time 98.56 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:37:16 PM PDT 24
Peak memory 201768 kb
Host smart-cd858bca-b71d-4756-9289-bd40abaef24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173087706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.173087706
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3937480269
Short name T711
Test name
Test status
Simulation time 166156066951 ps
CPU time 59.26 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:36:36 PM PDT 24
Peak memory 201480 kb
Host smart-a5a14979-3386-4124-bd9b-fd3a4e812a64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937480269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3937480269
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1842320551
Short name T136
Test name
Test status
Simulation time 456376207982 ps
CPU time 1115.06 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:54:13 PM PDT 24
Peak memory 201556 kb
Host smart-5d1aef7d-0fb3-4be9-816f-1eb761bb9683
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842320551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1842320551
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3996464962
Short name T775
Test name
Test status
Simulation time 619532800267 ps
CPU time 373.49 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:41:51 PM PDT 24
Peak memory 201532 kb
Host smart-a1748bbb-764e-473b-889d-b644a5db2337
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996464962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3996464962
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3892307356
Short name T185
Test name
Test status
Simulation time 89860671649 ps
CPU time 368.06 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:41:47 PM PDT 24
Peak memory 201848 kb
Host smart-f52b51fd-fdde-4320-9c63-af1ce9359df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892307356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3892307356
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1181789955
Short name T700
Test name
Test status
Simulation time 22407690088 ps
CPU time 12.68 seconds
Started Jul 17 05:35:39 PM PDT 24
Finished Jul 17 05:35:53 PM PDT 24
Peak memory 201324 kb
Host smart-3815f369-9cb3-4921-8192-be99c10c75bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181789955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1181789955
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2857045552
Short name T458
Test name
Test status
Simulation time 5360711842 ps
CPU time 1.95 seconds
Started Jul 17 05:35:39 PM PDT 24
Finished Jul 17 05:35:42 PM PDT 24
Peak memory 201260 kb
Host smart-c04c9e59-e4aa-458a-b853-1f2d5e62db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857045552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2857045552
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4133840003
Short name T507
Test name
Test status
Simulation time 5677215193 ps
CPU time 2.7 seconds
Started Jul 17 05:35:38 PM PDT 24
Finished Jul 17 05:35:41 PM PDT 24
Peak memory 201328 kb
Host smart-442fbedd-91af-491f-a9e5-fe42498ccbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133840003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4133840003
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3799677832
Short name T531
Test name
Test status
Simulation time 217612683943 ps
CPU time 728.78 seconds
Started Jul 17 05:35:36 PM PDT 24
Finished Jul 17 05:47:45 PM PDT 24
Peak memory 210024 kb
Host smart-dbb03d14-2838-40cb-910b-54ceb300df56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799677832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3799677832
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.441027240
Short name T98
Test name
Test status
Simulation time 272452918293 ps
CPU time 468.85 seconds
Started Jul 17 05:35:37 PM PDT 24
Finished Jul 17 05:43:27 PM PDT 24
Peak memory 210628 kb
Host smart-8e9ee78b-91ff-4262-ad4b-deabf80b8315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441027240 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.441027240
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.346576675
Short name T651
Test name
Test status
Simulation time 443059046 ps
CPU time 1.74 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:36:09 PM PDT 24
Peak memory 201504 kb
Host smart-122bb612-2fca-4ca1-a51d-152de7864f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346576675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.346576675
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1533704502
Short name T144
Test name
Test status
Simulation time 538568444373 ps
CPU time 491.33 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:44:19 PM PDT 24
Peak memory 201452 kb
Host smart-7e801264-4c61-43f1-8eea-8a596c816a99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533704502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1533704502
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3192642184
Short name T100
Test name
Test status
Simulation time 162719544371 ps
CPU time 84.4 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:37:30 PM PDT 24
Peak memory 201532 kb
Host smart-c823e763-30b7-4c17-9992-73c732acf1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192642184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3192642184
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3583296630
Short name T478
Test name
Test status
Simulation time 167317009990 ps
CPU time 396.15 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:42:42 PM PDT 24
Peak memory 201532 kb
Host smart-9900b5a2-8896-41d7-8366-87488c56edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583296630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3583296630
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1846587121
Short name T84
Test name
Test status
Simulation time 330108824587 ps
CPU time 58.75 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:37:06 PM PDT 24
Peak memory 201480 kb
Host smart-ec8e2680-e945-40a6-99c0-4dfa06117b98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846587121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1846587121
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3831272904
Short name T557
Test name
Test status
Simulation time 169540320766 ps
CPU time 397.3 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:42:44 PM PDT 24
Peak memory 201528 kb
Host smart-46237c56-12d0-4162-b41d-02347a74eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831272904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3831272904
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.753436716
Short name T636
Test name
Test status
Simulation time 493747396608 ps
CPU time 1136.96 seconds
Started Jul 17 05:36:03 PM PDT 24
Finished Jul 17 05:55:00 PM PDT 24
Peak memory 201524 kb
Host smart-856fced0-67ae-45a2-b714-4a6a5c5812b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=753436716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.753436716
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1758485337
Short name T217
Test name
Test status
Simulation time 179227242798 ps
CPU time 101.33 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:37:49 PM PDT 24
Peak memory 201544 kb
Host smart-2fba12ff-04e7-4489-b905-18a01183473f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758485337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1758485337
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.380703462
Short name T37
Test name
Test status
Simulation time 208128666572 ps
CPU time 503.29 seconds
Started Jul 17 05:36:07 PM PDT 24
Finished Jul 17 05:44:32 PM PDT 24
Peak memory 201500 kb
Host smart-a882275b-49ae-4a70-9b92-d52f00f0abe4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380703462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.380703462
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1254366685
Short name T687
Test name
Test status
Simulation time 131584161548 ps
CPU time 419.94 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:43:05 PM PDT 24
Peak memory 201864 kb
Host smart-2bf714ec-bf66-4e62-ae73-2b6f5640651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254366685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1254366685
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2508460489
Short name T758
Test name
Test status
Simulation time 36421416053 ps
CPU time 22.12 seconds
Started Jul 17 05:36:07 PM PDT 24
Finished Jul 17 05:36:30 PM PDT 24
Peak memory 201332 kb
Host smart-2869204b-852b-495c-a67c-a119955f9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508460489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2508460489
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.557037193
Short name T689
Test name
Test status
Simulation time 4618114037 ps
CPU time 3.69 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:36:09 PM PDT 24
Peak memory 201324 kb
Host smart-e18e16ec-b0db-4be4-9269-e6ab3d3c4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557037193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.557037193
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1428665781
Short name T411
Test name
Test status
Simulation time 6006670609 ps
CPU time 4.49 seconds
Started Jul 17 05:36:07 PM PDT 24
Finished Jul 17 05:36:13 PM PDT 24
Peak memory 201324 kb
Host smart-2dd5461f-c772-4a4b-ab16-4b94629ce69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428665781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1428665781
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3639297727
Short name T765
Test name
Test status
Simulation time 148002982046 ps
CPU time 666.46 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:47:13 PM PDT 24
Peak memory 211124 kb
Host smart-3d13c149-5fc1-4638-9502-4e787722ea8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639297727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3639297727
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3098195986
Short name T362
Test name
Test status
Simulation time 346015003 ps
CPU time 1.4 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:36:24 PM PDT 24
Peak memory 201256 kb
Host smart-5d86610e-a377-4e45-840b-33b6da390bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098195986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3098195986
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.141909273
Short name T78
Test name
Test status
Simulation time 513930313513 ps
CPU time 114.72 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:38:00 PM PDT 24
Peak memory 201508 kb
Host smart-58b0a042-6497-42bd-b598-4ee74b03c3af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141909273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.141909273
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3925771427
Short name T610
Test name
Test status
Simulation time 558426260670 ps
CPU time 713.97 seconds
Started Jul 17 05:36:07 PM PDT 24
Finished Jul 17 05:48:02 PM PDT 24
Peak memory 201612 kb
Host smart-0b7fdad3-0ea9-42e6-8c46-77aed44fcad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925771427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3925771427
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.389803013
Short name T598
Test name
Test status
Simulation time 171662740333 ps
CPU time 94.38 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:37:42 PM PDT 24
Peak memory 201484 kb
Host smart-f42b4119-3f8e-4e35-a65b-fc4270b52c8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=389803013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.389803013
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3610076998
Short name T627
Test name
Test status
Simulation time 500320810636 ps
CPU time 589.12 seconds
Started Jul 17 05:36:02 PM PDT 24
Finished Jul 17 05:45:52 PM PDT 24
Peak memory 201592 kb
Host smart-546748e1-3d25-4f36-b0fb-bebf022cc289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610076998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3610076998
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2066612175
Short name T777
Test name
Test status
Simulation time 322291224258 ps
CPU time 719.28 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 201732 kb
Host smart-4916c507-35b9-447c-8d4b-69a07bf7817b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066612175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2066612175
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.97622952
Short name T539
Test name
Test status
Simulation time 185567315986 ps
CPU time 86.53 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:37:33 PM PDT 24
Peak memory 201528 kb
Host smart-c1e7e979-8d7d-410e-be64-54f2aac904b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97622952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_w
akeup.97622952
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4065975816
Short name T434
Test name
Test status
Simulation time 616796210576 ps
CPU time 132.13 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:38:20 PM PDT 24
Peak memory 201516 kb
Host smart-d424c914-4ec6-413e-9600-1961f2a1addc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065975816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4065975816
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3775873256
Short name T469
Test name
Test status
Simulation time 113115969515 ps
CPU time 474.32 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:44:00 PM PDT 24
Peak memory 201900 kb
Host smart-ed250b28-5e50-432f-8c97-139075535f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775873256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3775873256
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.256517221
Short name T384
Test name
Test status
Simulation time 36325094599 ps
CPU time 19.74 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:36:27 PM PDT 24
Peak memory 201344 kb
Host smart-2442477d-9520-456a-a425-e8489ac850d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256517221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.256517221
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1483251872
Short name T698
Test name
Test status
Simulation time 3803791862 ps
CPU time 3.02 seconds
Started Jul 17 05:36:04 PM PDT 24
Finished Jul 17 05:36:09 PM PDT 24
Peak memory 201324 kb
Host smart-b86dd4e5-283f-4fce-b121-3fbce4cd52e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483251872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1483251872
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1993958656
Short name T429
Test name
Test status
Simulation time 5804824309 ps
CPU time 4.61 seconds
Started Jul 17 05:36:05 PM PDT 24
Finished Jul 17 05:36:12 PM PDT 24
Peak memory 201256 kb
Host smart-57124c82-f396-47b9-ab3b-1d6a30cb736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993958656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1993958656
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.459861391
Short name T244
Test name
Test status
Simulation time 50108597333 ps
CPU time 97.24 seconds
Started Jul 17 05:36:06 PM PDT 24
Finished Jul 17 05:37:45 PM PDT 24
Peak memory 209848 kb
Host smart-dd979633-5420-4484-92c5-448ad8b06223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459861391 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.459861391
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3178933953
Short name T580
Test name
Test status
Simulation time 347981405 ps
CPU time 1.13 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:36:21 PM PDT 24
Peak memory 201224 kb
Host smart-179d7cd4-b50d-4caf-9fb9-3c2c02da3493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178933953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3178933953
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3367622168
Short name T555
Test name
Test status
Simulation time 167821641323 ps
CPU time 102.47 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:38:05 PM PDT 24
Peak memory 201520 kb
Host smart-006e57ab-3d81-4fd5-9b45-62c9680f8fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367622168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3367622168
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4190525488
Short name T399
Test name
Test status
Simulation time 164868456438 ps
CPU time 364.28 seconds
Started Jul 17 05:36:22 PM PDT 24
Finished Jul 17 05:42:28 PM PDT 24
Peak memory 201484 kb
Host smart-bc94eada-7dd9-46ac-9b14-7100fe7f99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190525488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4190525488
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2420212120
Short name T365
Test name
Test status
Simulation time 318584410528 ps
CPU time 747.58 seconds
Started Jul 17 05:36:24 PM PDT 24
Finished Jul 17 05:48:53 PM PDT 24
Peak memory 201508 kb
Host smart-21ebca15-6084-4a6f-bc75-6816a6ac6bb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420212120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2420212120
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.344505667
Short name T759
Test name
Test status
Simulation time 164761354357 ps
CPU time 406.88 seconds
Started Jul 17 05:36:22 PM PDT 24
Finished Jul 17 05:43:10 PM PDT 24
Peak memory 201564 kb
Host smart-067532e1-6892-4a57-9dea-784ebdb30cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344505667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.344505667
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3285094913
Short name T402
Test name
Test status
Simulation time 500329573218 ps
CPU time 148.63 seconds
Started Jul 17 05:36:24 PM PDT 24
Finished Jul 17 05:38:54 PM PDT 24
Peak memory 201508 kb
Host smart-781638ba-4df3-45ad-8ef6-4d6b3107e86d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285094913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3285094913
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.224955495
Short name T543
Test name
Test status
Simulation time 620428740683 ps
CPU time 368.21 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:42:30 PM PDT 24
Peak memory 201496 kb
Host smart-2e055933-c54d-40d8-8f0c-1425c9403876
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224955495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.224955495
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3213923674
Short name T318
Test name
Test status
Simulation time 128913873847 ps
CPU time 471.58 seconds
Started Jul 17 05:36:18 PM PDT 24
Finished Jul 17 05:44:10 PM PDT 24
Peak memory 201896 kb
Host smart-bfe50c23-8c3a-4f01-a049-c5ae4be61fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213923674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3213923674
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.4145737722
Short name T102
Test name
Test status
Simulation time 40458851968 ps
CPU time 21.81 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:36:44 PM PDT 24
Peak memory 201280 kb
Host smart-210d1d66-8dac-4110-8ad8-80f91a0d93d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145737722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.4145737722
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3889408536
Short name T696
Test name
Test status
Simulation time 4231383899 ps
CPU time 5.65 seconds
Started Jul 17 05:36:17 PM PDT 24
Finished Jul 17 05:36:23 PM PDT 24
Peak memory 201300 kb
Host smart-63b8a9bb-8cb0-4ec2-b31e-2cba7f0bde5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889408536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3889408536
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3352105389
Short name T346
Test name
Test status
Simulation time 5908548428 ps
CPU time 7.18 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:36:29 PM PDT 24
Peak memory 201320 kb
Host smart-24bf317f-fbcf-4ff3-a381-5643eb7d1704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352105389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3352105389
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.369496176
Short name T183
Test name
Test status
Simulation time 514473311689 ps
CPU time 1230.93 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:56:53 PM PDT 24
Peak memory 201520 kb
Host smart-2068ec31-0c95-4017-90aa-012fc4318761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369496176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
369496176
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2740734189
Short name T267
Test name
Test status
Simulation time 937624675657 ps
CPU time 144.55 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:38:46 PM PDT 24
Peak memory 202024 kb
Host smart-4b94aa7e-a902-493b-ad8a-6c114af2007d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740734189 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2740734189
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.4293154732
Short name T554
Test name
Test status
Simulation time 449567615 ps
CPU time 1.58 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:36:24 PM PDT 24
Peak memory 201160 kb
Host smart-bb8c51c4-d1b9-449a-b3c6-2ba590011ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293154732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4293154732
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1260756737
Short name T284
Test name
Test status
Simulation time 177011958558 ps
CPU time 97.73 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:37:59 PM PDT 24
Peak memory 201524 kb
Host smart-1937ef54-831f-4544-bd4f-8d8dc020bc00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260756737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1260756737
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4082792432
Short name T302
Test name
Test status
Simulation time 512520118279 ps
CPU time 1244.32 seconds
Started Jul 17 05:36:24 PM PDT 24
Finished Jul 17 05:57:10 PM PDT 24
Peak memory 201548 kb
Host smart-47eeb2d3-920f-4c91-9c07-a5bc1ad4c574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082792432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4082792432
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1030117612
Short name T11
Test name
Test status
Simulation time 483101875962 ps
CPU time 571.89 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:45:54 PM PDT 24
Peak memory 201556 kb
Host smart-c8ad31c8-19f5-44f1-804e-cffeb53759ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030117612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1030117612
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3113895665
Short name T449
Test name
Test status
Simulation time 163143911019 ps
CPU time 394.27 seconds
Started Jul 17 05:36:23 PM PDT 24
Finished Jul 17 05:42:59 PM PDT 24
Peak memory 201524 kb
Host smart-5b6860c8-addf-4469-b7bf-79243f76f044
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113895665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3113895665
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2516278206
Short name T524
Test name
Test status
Simulation time 167013943748 ps
CPU time 368.13 seconds
Started Jul 17 05:36:23 PM PDT 24
Finished Jul 17 05:42:33 PM PDT 24
Peak memory 201536 kb
Host smart-b5314a93-69ba-4aa7-bb7f-bcf35ff87a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516278206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2516278206
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3359910000
Short name T566
Test name
Test status
Simulation time 329057927465 ps
CPU time 228.62 seconds
Started Jul 17 05:36:18 PM PDT 24
Finished Jul 17 05:40:07 PM PDT 24
Peak memory 201536 kb
Host smart-fba22097-8481-480d-af1d-e093e3a54e5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359910000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3359910000
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2068189134
Short name T596
Test name
Test status
Simulation time 198492449564 ps
CPU time 425.7 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:43:27 PM PDT 24
Peak memory 201460 kb
Host smart-cd433a89-a60b-4bc1-b095-837a73a1f812
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068189134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2068189134
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2893834994
Short name T572
Test name
Test status
Simulation time 97421226074 ps
CPU time 367.32 seconds
Started Jul 17 05:36:22 PM PDT 24
Finished Jul 17 05:42:31 PM PDT 24
Peak memory 201812 kb
Host smart-3aa958aa-05bf-4f15-97db-88dd3df6a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893834994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2893834994
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2033315880
Short name T396
Test name
Test status
Simulation time 43071706839 ps
CPU time 89.98 seconds
Started Jul 17 05:36:23 PM PDT 24
Finished Jul 17 05:37:54 PM PDT 24
Peak memory 201240 kb
Host smart-2599818c-9b93-4e1f-a91e-ae8c3df2e2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033315880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2033315880
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1613692871
Short name T532
Test name
Test status
Simulation time 3238648482 ps
CPU time 2.59 seconds
Started Jul 17 05:36:22 PM PDT 24
Finished Jul 17 05:36:26 PM PDT 24
Peak memory 201292 kb
Host smart-7c28b780-36f1-4f3b-90eb-cf34a970009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613692871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1613692871
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2305853024
Short name T450
Test name
Test status
Simulation time 5795244322 ps
CPU time 9.36 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:36:29 PM PDT 24
Peak memory 201328 kb
Host smart-d6dc1981-14df-4b29-b7a6-4f12eb6b69d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305853024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2305853024
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3889099388
Short name T77
Test name
Test status
Simulation time 175449481452 ps
CPU time 94.84 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:37:57 PM PDT 24
Peak memory 201452 kb
Host smart-4c070d34-7937-412f-ad44-0319cea57e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889099388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3889099388
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3731527252
Short name T128
Test name
Test status
Simulation time 140781710791 ps
CPU time 172.87 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:39:16 PM PDT 24
Peak memory 210152 kb
Host smart-a0cead55-6517-496d-b7fd-ca39e8ff44cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731527252 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3731527252
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.499506044
Short name T655
Test name
Test status
Simulation time 414387098 ps
CPU time 1.65 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:36:22 PM PDT 24
Peak memory 201284 kb
Host smart-a6946f19-7445-4fef-8fa6-e876d335cb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499506044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.499506044
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4248727454
Short name T232
Test name
Test status
Simulation time 174874056842 ps
CPU time 386.56 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:42:47 PM PDT 24
Peak memory 201492 kb
Host smart-2c7eab35-ba1d-433e-8fc1-5a019388db30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248727454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4248727454
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.762924810
Short name T264
Test name
Test status
Simulation time 335211010916 ps
CPU time 191.99 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:39:34 PM PDT 24
Peak memory 201548 kb
Host smart-de7e9018-a76a-4c2e-895a-b969aa9aa4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762924810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.762924810
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.452446193
Short name T195
Test name
Test status
Simulation time 495241588161 ps
CPU time 392.98 seconds
Started Jul 17 05:36:23 PM PDT 24
Finished Jul 17 05:42:57 PM PDT 24
Peak memory 201540 kb
Host smart-0c193de6-dab5-4281-8eb0-c5923a6df42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452446193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.452446193
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.76930708
Short name T533
Test name
Test status
Simulation time 492830345316 ps
CPU time 1120.7 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:55:01 PM PDT 24
Peak memory 201524 kb
Host smart-5c1368f4-3c5d-4f1d-a950-c67806f9aee9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=76930708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt
_fixed.76930708
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.906109392
Short name T172
Test name
Test status
Simulation time 479339270132 ps
CPU time 313.89 seconds
Started Jul 17 05:36:22 PM PDT 24
Finished Jul 17 05:41:37 PM PDT 24
Peak memory 201548 kb
Host smart-0f3a83f9-cea3-4103-82df-9604b03a8338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906109392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.906109392
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.4178417345
Short name T720
Test name
Test status
Simulation time 328437397950 ps
CPU time 195.1 seconds
Started Jul 17 05:36:24 PM PDT 24
Finished Jul 17 05:39:40 PM PDT 24
Peak memory 201508 kb
Host smart-4c5b7983-176a-40de-a79d-d31ffa45bf9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178417345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.4178417345
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.949128484
Short name T428
Test name
Test status
Simulation time 355297049717 ps
CPU time 496.09 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:44:37 PM PDT 24
Peak memory 201604 kb
Host smart-65e944d1-fa55-41e5-aebc-1aa047b22d4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949128484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.949128484
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.515967299
Short name T501
Test name
Test status
Simulation time 402249564898 ps
CPU time 434.45 seconds
Started Jul 17 05:36:23 PM PDT 24
Finished Jul 17 05:43:39 PM PDT 24
Peak memory 201476 kb
Host smart-32e9d939-aaed-4688-a6bd-6995e3bd795e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515967299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.515967299
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2134488281
Short name T499
Test name
Test status
Simulation time 89506849000 ps
CPU time 477.9 seconds
Started Jul 17 05:36:24 PM PDT 24
Finished Jul 17 05:44:23 PM PDT 24
Peak memory 201908 kb
Host smart-d6fe7976-0bdf-40b6-86f5-140e212505f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134488281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2134488281
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1452867505
Short name T484
Test name
Test status
Simulation time 38886652321 ps
CPU time 84.36 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:37:46 PM PDT 24
Peak memory 201268 kb
Host smart-fb72e9df-f2dc-4d1a-98ce-15dc73a044a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452867505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1452867505
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.714834680
Short name T565
Test name
Test status
Simulation time 3640696562 ps
CPU time 2.74 seconds
Started Jul 17 05:36:20 PM PDT 24
Finished Jul 17 05:36:24 PM PDT 24
Peak memory 201328 kb
Host smart-681d64fa-67d3-438c-b6ee-6a5ddbe64be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714834680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.714834680
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3749876287
Short name T383
Test name
Test status
Simulation time 5667896706 ps
CPU time 13.34 seconds
Started Jul 17 05:36:18 PM PDT 24
Finished Jul 17 05:36:31 PM PDT 24
Peak memory 201340 kb
Host smart-c8a5ba04-88f1-42ff-ac2a-9d780129bc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749876287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3749876287
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.893783432
Short name T257
Test name
Test status
Simulation time 211756930353 ps
CPU time 130.34 seconds
Started Jul 17 05:36:36 PM PDT 24
Finished Jul 17 05:38:47 PM PDT 24
Peak memory 201536 kb
Host smart-86cac6c2-256e-4083-8aff-797c3d24e418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893783432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
893783432
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4021002585
Short name T54
Test name
Test status
Simulation time 112873175258 ps
CPU time 209.39 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:39:49 PM PDT 24
Peak memory 209848 kb
Host smart-1459008a-66c7-4ca3-981e-f35a2a423abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021002585 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4021002585
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.908723964
Short name T673
Test name
Test status
Simulation time 357688306 ps
CPU time 1.42 seconds
Started Jul 17 05:32:03 PM PDT 24
Finished Jul 17 05:32:05 PM PDT 24
Peak memory 201208 kb
Host smart-2c48ea67-3ba9-4ed5-b9c8-e762a71f8cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908723964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.908723964
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3787093532
Short name T134
Test name
Test status
Simulation time 167969340495 ps
CPU time 190.32 seconds
Started Jul 17 05:31:53 PM PDT 24
Finished Jul 17 05:35:04 PM PDT 24
Peak memory 201596 kb
Host smart-19822ad1-9054-4a80-b014-7f4ce042af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787093532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3787093532
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.141919494
Short name T664
Test name
Test status
Simulation time 165882954241 ps
CPU time 93.2 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:35:27 PM PDT 24
Peak memory 201536 kb
Host smart-dc1614bc-9859-47b2-ad9b-8c21a4efa120
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=141919494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.141919494
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1108819400
Short name T756
Test name
Test status
Simulation time 336334623866 ps
CPU time 734.62 seconds
Started Jul 17 05:31:52 PM PDT 24
Finished Jul 17 05:44:07 PM PDT 24
Peak memory 201540 kb
Host smart-96b9978e-0c28-44b5-a189-0134a27addf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108819400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1108819400
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1589326901
Short name T420
Test name
Test status
Simulation time 331446998760 ps
CPU time 293.81 seconds
Started Jul 17 05:31:52 PM PDT 24
Finished Jul 17 05:36:47 PM PDT 24
Peak memory 201572 kb
Host smart-7aa65f19-2c92-4507-b7ba-6433e0ebf77f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589326901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1589326901
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3245327926
Short name T556
Test name
Test status
Simulation time 242588366187 ps
CPU time 551.6 seconds
Started Jul 17 05:31:53 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 201536 kb
Host smart-47550854-94dc-4111-ad3a-44fadd0be7c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245327926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3245327926
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1766940204
Short name T387
Test name
Test status
Simulation time 621826255083 ps
CPU time 1350.27 seconds
Started Jul 17 05:31:53 PM PDT 24
Finished Jul 17 05:54:25 PM PDT 24
Peak memory 201476 kb
Host smart-5c429bd3-7c25-4770-94e2-673fb381fd78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766940204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1766940204
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1029085091
Short name T5
Test name
Test status
Simulation time 23835680899 ps
CPU time 14.8 seconds
Started Jul 17 05:31:54 PM PDT 24
Finished Jul 17 05:32:10 PM PDT 24
Peak memory 201244 kb
Host smart-51a1e908-6be8-4c15-a7fe-3bea185db625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029085091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1029085091
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3806172956
Short name T443
Test name
Test status
Simulation time 4684232350 ps
CPU time 6.29 seconds
Started Jul 17 05:31:55 PM PDT 24
Finished Jul 17 05:32:02 PM PDT 24
Peak memory 201268 kb
Host smart-47bc1311-1a8f-4b0f-b0dc-90bfa53a8660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806172956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3806172956
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2449056196
Short name T57
Test name
Test status
Simulation time 4510069965 ps
CPU time 7.72 seconds
Started Jul 17 05:32:07 PM PDT 24
Finished Jul 17 05:32:16 PM PDT 24
Peak memory 217196 kb
Host smart-ae96fd77-33d5-4504-a430-3b54c08f8de8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449056196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2449056196
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3158902466
Short name T394
Test name
Test status
Simulation time 5717141185 ps
CPU time 4.17 seconds
Started Jul 17 05:31:53 PM PDT 24
Finished Jul 17 05:31:59 PM PDT 24
Peak memory 201276 kb
Host smart-a69449d9-a8d2-4db8-b5ce-e5f8b8079d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158902466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3158902466
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.255211661
Short name T312
Test name
Test status
Simulation time 254598225762 ps
CPU time 479.51 seconds
Started Jul 17 05:32:08 PM PDT 24
Finished Jul 17 05:40:09 PM PDT 24
Peak memory 201892 kb
Host smart-2cdc7abb-3e42-4888-bbdd-7985b846bc2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255211661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.255211661
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1889447309
Short name T691
Test name
Test status
Simulation time 75758555823 ps
CPU time 47.49 seconds
Started Jul 17 05:32:11 PM PDT 24
Finished Jul 17 05:32:59 PM PDT 24
Peak memory 209768 kb
Host smart-8598fb98-ed5e-4f29-b2c6-c17a35130373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889447309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1889447309
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.418911950
Short name T401
Test name
Test status
Simulation time 424789387 ps
CPU time 0.83 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:36:58 PM PDT 24
Peak memory 201192 kb
Host smart-85855c5e-b2ab-4769-a3a9-144f0f47d738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418911950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.418911950
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2414385609
Short name T168
Test name
Test status
Simulation time 509971870536 ps
CPU time 301.69 seconds
Started Jul 17 05:36:35 PM PDT 24
Finished Jul 17 05:41:37 PM PDT 24
Peak memory 201524 kb
Host smart-f6f5dd28-91ef-4691-bfe9-9f8638eeecbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414385609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2414385609
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1227241617
Short name T250
Test name
Test status
Simulation time 491242439825 ps
CPU time 1047.06 seconds
Started Jul 17 05:36:21 PM PDT 24
Finished Jul 17 05:53:50 PM PDT 24
Peak memory 201476 kb
Host smart-64fb39d9-c1bc-4bc2-95af-7e4bf0c971d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227241617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1227241617
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2886791886
Short name T468
Test name
Test status
Simulation time 490941312021 ps
CPU time 1078.88 seconds
Started Jul 17 05:36:22 PM PDT 24
Finished Jul 17 05:54:22 PM PDT 24
Peak memory 201528 kb
Host smart-3719aa42-a8c4-4994-b2c1-410cf0dabb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886791886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2886791886
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2176337975
Short name T190
Test name
Test status
Simulation time 491717261175 ps
CPU time 585.31 seconds
Started Jul 17 05:36:25 PM PDT 24
Finished Jul 17 05:46:11 PM PDT 24
Peak memory 201512 kb
Host smart-bedf8f88-ef02-4898-af99-4ae50d40849d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176337975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2176337975
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.326495214
Short name T537
Test name
Test status
Simulation time 169441478905 ps
CPU time 188.25 seconds
Started Jul 17 05:36:32 PM PDT 24
Finished Jul 17 05:39:41 PM PDT 24
Peak memory 201516 kb
Host smart-3c2f40fb-b1a4-45de-928a-dd01d34d5916
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326495214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.326495214
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3997040897
Short name T592
Test name
Test status
Simulation time 199038595203 ps
CPU time 138.69 seconds
Started Jul 17 05:36:32 PM PDT 24
Finished Jul 17 05:38:52 PM PDT 24
Peak memory 201500 kb
Host smart-f594cc40-59a8-441f-8bd5-07a63caa0771
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997040897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3997040897
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.369485051
Short name T314
Test name
Test status
Simulation time 126285889027 ps
CPU time 657.38 seconds
Started Jul 17 05:36:38 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 201844 kb
Host smart-df6343e6-ed13-450d-8cb0-42c22a841e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369485051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.369485051
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1186875704
Short name T571
Test name
Test status
Simulation time 46947328911 ps
CPU time 32.53 seconds
Started Jul 17 05:36:38 PM PDT 24
Finished Jul 17 05:37:11 PM PDT 24
Peak memory 201244 kb
Host smart-31ba2e6c-3039-4ae3-97ca-3e3f2a310c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186875704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1186875704
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1926915363
Short name T617
Test name
Test status
Simulation time 2784106998 ps
CPU time 3.39 seconds
Started Jul 17 05:36:32 PM PDT 24
Finished Jul 17 05:36:36 PM PDT 24
Peak memory 201348 kb
Host smart-02547ee9-76c9-4066-99d0-36592f540d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926915363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1926915363
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3260816236
Short name T548
Test name
Test status
Simulation time 5915185410 ps
CPU time 7.95 seconds
Started Jul 17 05:36:19 PM PDT 24
Finished Jul 17 05:36:29 PM PDT 24
Peak memory 201300 kb
Host smart-7c6859d9-8a51-426d-b9b0-55bf6f802b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260816236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3260816236
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2315076089
Short name T608
Test name
Test status
Simulation time 185446241857 ps
CPU time 163.67 seconds
Started Jul 17 05:36:32 PM PDT 24
Finished Jul 17 05:39:16 PM PDT 24
Peak memory 201592 kb
Host smart-bc968f11-5ee6-4e9a-a8ec-0d57087cfae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315076089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2315076089
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3976440263
Short name T407
Test name
Test status
Simulation time 363555398 ps
CPU time 0.78 seconds
Started Jul 17 05:36:35 PM PDT 24
Finished Jul 17 05:36:36 PM PDT 24
Peak memory 201156 kb
Host smart-b88de1ec-b8f8-4b7f-9fb2-e8270c750501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976440263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3976440263
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.771780883
Short name T129
Test name
Test status
Simulation time 537561166985 ps
CPU time 626.06 seconds
Started Jul 17 05:36:37 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 201480 kb
Host smart-e0aa769a-1d9a-4854-a5dd-64e81a6543e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771780883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.771780883
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3359390543
Short name T406
Test name
Test status
Simulation time 165105636029 ps
CPU time 99.61 seconds
Started Jul 17 05:36:35 PM PDT 24
Finished Jul 17 05:38:15 PM PDT 24
Peak memory 201532 kb
Host smart-5e434331-b518-4350-89bf-de2d3521a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359390543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3359390543
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2844692406
Short name T26
Test name
Test status
Simulation time 327889633187 ps
CPU time 171.91 seconds
Started Jul 17 05:36:35 PM PDT 24
Finished Jul 17 05:39:27 PM PDT 24
Peak memory 201408 kb
Host smart-d5f1da87-7a0a-470e-a96b-8ffc1b0b90a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844692406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2844692406
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3673191151
Short name T705
Test name
Test status
Simulation time 486709364018 ps
CPU time 263.16 seconds
Started Jul 17 05:36:34 PM PDT 24
Finished Jul 17 05:40:58 PM PDT 24
Peak memory 201456 kb
Host smart-1e843f87-cccc-4a42-a2ee-caa4fc5359e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673191151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3673191151
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3885870299
Short name T770
Test name
Test status
Simulation time 260017305400 ps
CPU time 629.12 seconds
Started Jul 17 05:36:34 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 201536 kb
Host smart-be2d5c0b-83a1-4015-90e1-9e68151f8d49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885870299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3885870299
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2271631790
Short name T445
Test name
Test status
Simulation time 601382646005 ps
CPU time 726.46 seconds
Started Jul 17 05:36:34 PM PDT 24
Finished Jul 17 05:48:42 PM PDT 24
Peak memory 201452 kb
Host smart-8f3cd03f-66d9-4584-ad21-636a10fdcfde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271631790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2271631790
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3915537084
Short name T192
Test name
Test status
Simulation time 131752747303 ps
CPU time 409.54 seconds
Started Jul 17 05:36:31 PM PDT 24
Finished Jul 17 05:43:21 PM PDT 24
Peak memory 201916 kb
Host smart-a17ec8d6-0cd7-4ae7-b7c1-f0f4dcefaa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915537084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3915537084
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3220015763
Short name T564
Test name
Test status
Simulation time 36140946334 ps
CPU time 79.07 seconds
Started Jul 17 05:36:33 PM PDT 24
Finished Jul 17 05:37:53 PM PDT 24
Peak memory 201276 kb
Host smart-fd1319db-eb97-425c-90f9-261d907ef9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220015763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3220015763
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3511859533
Short name T528
Test name
Test status
Simulation time 3849969481 ps
CPU time 2.44 seconds
Started Jul 17 05:36:32 PM PDT 24
Finished Jul 17 05:36:35 PM PDT 24
Peak memory 201236 kb
Host smart-7135ba37-1a43-4695-96c8-617f69a6d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511859533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3511859533
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4228381527
Short name T480
Test name
Test status
Simulation time 5937619888 ps
CPU time 13.86 seconds
Started Jul 17 05:36:31 PM PDT 24
Finished Jul 17 05:36:46 PM PDT 24
Peak memory 201340 kb
Host smart-1983216b-fa09-42af-8691-fb42e3f3b794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228381527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4228381527
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2055873680
Short name T602
Test name
Test status
Simulation time 326130533911 ps
CPU time 195.95 seconds
Started Jul 17 05:36:33 PM PDT 24
Finished Jul 17 05:39:49 PM PDT 24
Peak memory 201484 kb
Host smart-ba76a167-d439-401c-841f-699dec4e395f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055873680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2055873680
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3051043783
Short name T21
Test name
Test status
Simulation time 107157424712 ps
CPU time 169.09 seconds
Started Jul 17 05:36:31 PM PDT 24
Finished Jul 17 05:39:21 PM PDT 24
Peak memory 217980 kb
Host smart-de244be5-b2cc-4d3f-95e4-f4cfab1e39b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051043783 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3051043783
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.721876626
Short name T643
Test name
Test status
Simulation time 294736443 ps
CPU time 0.78 seconds
Started Jul 17 05:36:42 PM PDT 24
Finished Jul 17 05:36:43 PM PDT 24
Peak memory 201240 kb
Host smart-aae6e86c-96f8-4105-aa50-b667afda80fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721876626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.721876626
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.782846249
Short name T741
Test name
Test status
Simulation time 330217793287 ps
CPU time 115.91 seconds
Started Jul 17 05:36:38 PM PDT 24
Finished Jul 17 05:38:34 PM PDT 24
Peak memory 201472 kb
Host smart-8c07529f-96cc-4fe8-a95a-9069ecb99b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782846249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.782846249
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1545071929
Short name T334
Test name
Test status
Simulation time 489674780095 ps
CPU time 293.63 seconds
Started Jul 17 05:36:46 PM PDT 24
Finished Jul 17 05:41:40 PM PDT 24
Peak memory 201440 kb
Host smart-d6daa2b1-7a7a-45a8-ae58-656d86801d62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545071929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1545071929
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3765993155
Short name T288
Test name
Test status
Simulation time 485002090732 ps
CPU time 265.37 seconds
Started Jul 17 05:36:31 PM PDT 24
Finished Jul 17 05:40:58 PM PDT 24
Peak memory 201520 kb
Host smart-177747c0-1375-4142-86fa-4245e31a977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765993155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3765993155
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2782130706
Short name T646
Test name
Test status
Simulation time 493510668157 ps
CPU time 1196.63 seconds
Started Jul 17 05:36:32 PM PDT 24
Finished Jul 17 05:56:29 PM PDT 24
Peak memory 201528 kb
Host smart-78d52d1a-1ba9-4cea-954a-13ebaab8f6b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782130706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2782130706
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.848930458
Short name T773
Test name
Test status
Simulation time 376755839465 ps
CPU time 800.32 seconds
Started Jul 17 05:36:43 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 201572 kb
Host smart-a56a7040-b1cf-4f8e-bbc1-e7eda79deef5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848930458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.848930458
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3074529125
Short name T786
Test name
Test status
Simulation time 588778766851 ps
CPU time 1317.19 seconds
Started Jul 17 05:36:43 PM PDT 24
Finished Jul 17 05:58:41 PM PDT 24
Peak memory 201512 kb
Host smart-2d13e9dc-6448-4ca4-bad9-6fe67d8b5327
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074529125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3074529125
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1157617963
Short name T712
Test name
Test status
Simulation time 124880893837 ps
CPU time 487.49 seconds
Started Jul 17 05:36:46 PM PDT 24
Finished Jul 17 05:44:54 PM PDT 24
Peak memory 201948 kb
Host smart-65d3108e-07e2-4837-9fb0-a9271e01bc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157617963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1157617963
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3249755102
Short name T89
Test name
Test status
Simulation time 32932537202 ps
CPU time 76.9 seconds
Started Jul 17 05:36:42 PM PDT 24
Finished Jul 17 05:37:59 PM PDT 24
Peak memory 201328 kb
Host smart-0d816540-876d-40e0-85e2-a540bf181366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249755102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3249755102
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.343099229
Short name T366
Test name
Test status
Simulation time 4321727463 ps
CPU time 5.43 seconds
Started Jul 17 05:36:43 PM PDT 24
Finished Jul 17 05:36:49 PM PDT 24
Peak memory 201260 kb
Host smart-3b2bc631-56c7-467c-a9ac-21c19c00fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343099229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.343099229
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2208706875
Short name T391
Test name
Test status
Simulation time 5870944925 ps
CPU time 3.92 seconds
Started Jul 17 05:36:33 PM PDT 24
Finished Jul 17 05:36:38 PM PDT 24
Peak memory 201292 kb
Host smart-49d76b2f-852f-4f2a-a8df-9294b64a700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208706875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2208706875
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2142457527
Short name T671
Test name
Test status
Simulation time 321301388480 ps
CPU time 1071.66 seconds
Started Jul 17 05:36:44 PM PDT 24
Finished Jul 17 05:54:36 PM PDT 24
Peak memory 212640 kb
Host smart-6e2f0b55-b69f-4ff7-8857-d508d72f4a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142457527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2142457527
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.900754604
Short name T18
Test name
Test status
Simulation time 200874648377 ps
CPU time 150.97 seconds
Started Jul 17 05:36:43 PM PDT 24
Finished Jul 17 05:39:14 PM PDT 24
Peak memory 210228 kb
Host smart-163c41a5-d723-453c-9520-e36d91b9d5ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900754604 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.900754604
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4055409145
Short name T418
Test name
Test status
Simulation time 312485652 ps
CPU time 0.79 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:36:57 PM PDT 24
Peak memory 201288 kb
Host smart-3cf85779-a2fa-4777-adf9-7b6e8e73f97b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055409145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4055409145
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2553820241
Short name T218
Test name
Test status
Simulation time 380840464775 ps
CPU time 304.41 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:42:01 PM PDT 24
Peak memory 201532 kb
Host smart-f4d35fce-ed17-466b-b65e-dbbdd895f0da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553820241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2553820241
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4154944364
Short name T616
Test name
Test status
Simulation time 162373859460 ps
CPU time 177.55 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:39:54 PM PDT 24
Peak memory 201540 kb
Host smart-ddc0c890-7ff5-4d55-be6d-c8f327c9c5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154944364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4154944364
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1423035933
Short name T714
Test name
Test status
Simulation time 489839677464 ps
CPU time 346.53 seconds
Started Jul 17 05:36:43 PM PDT 24
Finished Jul 17 05:42:30 PM PDT 24
Peak memory 201392 kb
Host smart-d931b531-79cb-4f72-88c7-e62a566ffb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423035933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1423035933
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2130840995
Short name T392
Test name
Test status
Simulation time 489759898270 ps
CPU time 1212.79 seconds
Started Jul 17 05:36:54 PM PDT 24
Finished Jul 17 05:57:08 PM PDT 24
Peak memory 201504 kb
Host smart-31ffe76d-ac75-409d-b076-cabc1317fc6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130840995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2130840995
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3192144113
Short name T713
Test name
Test status
Simulation time 329430906606 ps
CPU time 195.84 seconds
Started Jul 17 05:36:47 PM PDT 24
Finished Jul 17 05:40:03 PM PDT 24
Peak memory 201564 kb
Host smart-1b05f172-3412-4920-82a4-93b6857f0752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192144113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3192144113
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2193171860
Short name T451
Test name
Test status
Simulation time 493031941561 ps
CPU time 1079.27 seconds
Started Jul 17 05:36:42 PM PDT 24
Finished Jul 17 05:54:42 PM PDT 24
Peak memory 201592 kb
Host smart-55edd474-7c39-489c-bd8f-40967362e89a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193171860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2193171860
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.17467353
Short name T165
Test name
Test status
Simulation time 189976509356 ps
CPU time 111.32 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:38:48 PM PDT 24
Peak memory 201596 kb
Host smart-d2fb6cd5-43b4-49f4-9e46-755dffd333b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17467353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_w
akeup.17467353
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2237050747
Short name T780
Test name
Test status
Simulation time 614650121076 ps
CPU time 798.47 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:50:15 PM PDT 24
Peak memory 201436 kb
Host smart-79e5b4bd-7494-4dd5-bf2f-1d012262f2b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237050747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2237050747
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4109377756
Short name T82
Test name
Test status
Simulation time 89647878924 ps
CPU time 284.35 seconds
Started Jul 17 05:36:57 PM PDT 24
Finished Jul 17 05:41:42 PM PDT 24
Peak memory 201852 kb
Host smart-7b3528cb-9397-4772-9587-0e8abb017200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109377756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4109377756
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3192597662
Short name T345
Test name
Test status
Simulation time 29084905432 ps
CPU time 21.16 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:37:18 PM PDT 24
Peak memory 201336 kb
Host smart-bd0566fd-b76b-4cac-8774-53077dde022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192597662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3192597662
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2621282369
Short name T422
Test name
Test status
Simulation time 4337955057 ps
CPU time 5.66 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:37:01 PM PDT 24
Peak memory 201336 kb
Host smart-7f2e8f0f-d34d-4e77-a7aa-c7cbe2c5bb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621282369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2621282369
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1517573760
Short name T381
Test name
Test status
Simulation time 5641830628 ps
CPU time 5.12 seconds
Started Jul 17 05:36:43 PM PDT 24
Finished Jul 17 05:36:49 PM PDT 24
Peak memory 201292 kb
Host smart-91aeaad4-278b-43f7-b27f-bd150c3e125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517573760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1517573760
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2987072940
Short name T272
Test name
Test status
Simulation time 256728102911 ps
CPU time 384.69 seconds
Started Jul 17 05:36:54 PM PDT 24
Finished Jul 17 05:43:20 PM PDT 24
Peak memory 201824 kb
Host smart-3f58f04b-d4ee-44d4-8837-45e9adcafac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987072940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2987072940
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1107401502
Short name T685
Test name
Test status
Simulation time 532534079 ps
CPU time 1.26 seconds
Started Jul 17 05:37:08 PM PDT 24
Finished Jul 17 05:37:11 PM PDT 24
Peak memory 201276 kb
Host smart-6c958d6f-0185-4dbc-8b7f-2655286bb2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107401502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1107401502
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2837251915
Short name T706
Test name
Test status
Simulation time 378411535053 ps
CPU time 816.14 seconds
Started Jul 17 05:36:55 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 201456 kb
Host smart-93e2efb0-c9aa-48a1-b166-d55495a61d0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837251915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2837251915
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.4110799636
Short name T734
Test name
Test status
Simulation time 516971188206 ps
CPU time 656.06 seconds
Started Jul 17 05:37:07 PM PDT 24
Finished Jul 17 05:48:04 PM PDT 24
Peak memory 201540 kb
Host smart-36abc306-c1d9-4d5c-bb42-b57a65f749e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110799636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.4110799636
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3055554964
Short name T153
Test name
Test status
Simulation time 493148280434 ps
CPU time 279.25 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 201472 kb
Host smart-c4ffd487-db36-49c1-83c8-a0c58fe627fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055554964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3055554964
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1612389137
Short name T141
Test name
Test status
Simulation time 494487367571 ps
CPU time 546.84 seconds
Started Jul 17 05:36:53 PM PDT 24
Finished Jul 17 05:46:01 PM PDT 24
Peak memory 201752 kb
Host smart-f1f5cb57-e904-4e78-b601-7c20f168c564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612389137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1612389137
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1987930934
Short name T437
Test name
Test status
Simulation time 330184918692 ps
CPU time 750.53 seconds
Started Jul 17 05:36:54 PM PDT 24
Finished Jul 17 05:49:26 PM PDT 24
Peak memory 201524 kb
Host smart-491b5018-a9aa-480a-893d-fd86929b0162
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987930934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1987930934
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.943700836
Short name T107
Test name
Test status
Simulation time 174329560692 ps
CPU time 110.74 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:38:48 PM PDT 24
Peak memory 201484 kb
Host smart-47e8530d-b9a4-4cf0-b6e8-258ca2404f90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943700836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.943700836
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2972234749
Short name T567
Test name
Test status
Simulation time 203054825992 ps
CPU time 463.01 seconds
Started Jul 17 05:36:56 PM PDT 24
Finished Jul 17 05:44:40 PM PDT 24
Peak memory 201516 kb
Host smart-f4abefe3-fa61-407d-899a-ce682932f9ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972234749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2972234749
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3384849396
Short name T500
Test name
Test status
Simulation time 126474580368 ps
CPU time 669.92 seconds
Started Jul 17 05:37:08 PM PDT 24
Finished Jul 17 05:48:19 PM PDT 24
Peak memory 201832 kb
Host smart-5d5b7fa8-0dd5-4bdb-bff6-4340c472b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384849396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3384849396
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2546087670
Short name T754
Test name
Test status
Simulation time 31064837152 ps
CPU time 22.99 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:37:33 PM PDT 24
Peak memory 201296 kb
Host smart-a2f13c84-bcba-4b7e-918f-f32bd86ec241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546087670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2546087670
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3214606069
Short name T358
Test name
Test status
Simulation time 3988489278 ps
CPU time 2.65 seconds
Started Jul 17 05:37:10 PM PDT 24
Finished Jul 17 05:37:14 PM PDT 24
Peak memory 201324 kb
Host smart-451919b7-77ad-4dec-adf1-8235a887e41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214606069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3214606069
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4022927464
Short name T570
Test name
Test status
Simulation time 5766185128 ps
CPU time 7.33 seconds
Started Jul 17 05:36:54 PM PDT 24
Finished Jul 17 05:37:03 PM PDT 24
Peak memory 201340 kb
Host smart-17cb2391-3431-4161-ad49-9078eba49412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022927464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4022927464
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.121604489
Short name T593
Test name
Test status
Simulation time 239736510721 ps
CPU time 554.8 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:46:26 PM PDT 24
Peak memory 201540 kb
Host smart-a2f8eaa6-8e71-41e8-8031-0622096d5588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121604489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
121604489
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2783824448
Short name T30
Test name
Test status
Simulation time 170499977118 ps
CPU time 52.94 seconds
Started Jul 17 05:37:10 PM PDT 24
Finished Jul 17 05:38:05 PM PDT 24
Peak memory 201640 kb
Host smart-aa31c881-8871-4920-9066-e82fab0d2fea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783824448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2783824448
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2864116825
Short name T453
Test name
Test status
Simulation time 404302687 ps
CPU time 0.85 seconds
Started Jul 17 05:37:19 PM PDT 24
Finished Jul 17 05:37:21 PM PDT 24
Peak memory 201156 kb
Host smart-973fbd74-1618-4111-b7f4-a2d89f977276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864116825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2864116825
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.958005781
Short name T751
Test name
Test status
Simulation time 512388882724 ps
CPU time 180.07 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:40:10 PM PDT 24
Peak memory 201460 kb
Host smart-aeee2e4d-62ab-4afd-8373-4310ca96dc13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958005781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.958005781
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2731561380
Short name T279
Test name
Test status
Simulation time 493496425302 ps
CPU time 1104.5 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:55:36 PM PDT 24
Peak memory 201532 kb
Host smart-fc3a2eca-ff99-4e7a-92be-87122d7d2eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731561380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2731561380
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3870862109
Short name T137
Test name
Test status
Simulation time 164246579528 ps
CPU time 101.07 seconds
Started Jul 17 05:37:10 PM PDT 24
Finished Jul 17 05:38:52 PM PDT 24
Peak memory 201496 kb
Host smart-096c2f60-577d-4924-b1bb-dbc2be9d6546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870862109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3870862109
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2011376460
Short name T163
Test name
Test status
Simulation time 160821237429 ps
CPU time 92.88 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:38:43 PM PDT 24
Peak memory 201616 kb
Host smart-7098b642-b7a1-4f7a-b774-faeacd3a451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011376460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2011376460
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2169364279
Short name T600
Test name
Test status
Simulation time 498924781125 ps
CPU time 525.71 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:45:56 PM PDT 24
Peak memory 201500 kb
Host smart-628f7f8a-92b4-4885-be2c-ab5fd9f1d239
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169364279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2169364279
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1107920646
Short name T276
Test name
Test status
Simulation time 572346148574 ps
CPU time 620.13 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:47:31 PM PDT 24
Peak memory 201496 kb
Host smart-55ef1a27-0304-49a8-bcfd-222f962d1771
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107920646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1107920646
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2303074900
Short name T624
Test name
Test status
Simulation time 583564056097 ps
CPU time 363.77 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:43:14 PM PDT 24
Peak memory 201500 kb
Host smart-be3217c4-656b-4edc-b24f-2c873eefa69b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303074900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2303074900
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1466989354
Short name T40
Test name
Test status
Simulation time 98167625365 ps
CPU time 319.3 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:42:41 PM PDT 24
Peak memory 201840 kb
Host smart-16258d02-f593-4e81-93e6-822246a9f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466989354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1466989354
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3332366454
Short name T637
Test name
Test status
Simulation time 40819430326 ps
CPU time 23.14 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:37:44 PM PDT 24
Peak memory 201328 kb
Host smart-98698b2a-342c-411c-80d3-8725af111d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332366454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3332366454
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2465220150
Short name T371
Test name
Test status
Simulation time 5413315896 ps
CPU time 2.53 seconds
Started Jul 17 05:37:21 PM PDT 24
Finished Jul 17 05:37:25 PM PDT 24
Peak memory 201336 kb
Host smart-bc190b26-64d0-4d91-90e8-ab86fa292ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465220150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2465220150
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.65752959
Short name T684
Test name
Test status
Simulation time 5645142533 ps
CPU time 3.44 seconds
Started Jul 17 05:37:09 PM PDT 24
Finished Jul 17 05:37:14 PM PDT 24
Peak memory 201344 kb
Host smart-11409f9a-0e7d-44df-8d63-99932053c8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65752959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.65752959
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2489767398
Short name T96
Test name
Test status
Simulation time 478551768486 ps
CPU time 871.01 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:51:52 PM PDT 24
Peak memory 211984 kb
Host smart-fe77f0a6-2ed5-4357-86d2-4920fa031102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489767398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2489767398
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1881525345
Short name T560
Test name
Test status
Simulation time 418241151 ps
CPU time 1.48 seconds
Started Jul 17 05:37:33 PM PDT 24
Finished Jul 17 05:37:37 PM PDT 24
Peak memory 201276 kb
Host smart-5e9df928-f6fc-4e58-b834-dc392de5df65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881525345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1881525345
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1106652125
Short name T268
Test name
Test status
Simulation time 356419746118 ps
CPU time 414.8 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:44:16 PM PDT 24
Peak memory 201532 kb
Host smart-b248ff3e-277a-40dd-b5a8-12a09e9aa3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106652125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1106652125
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3718816007
Short name T769
Test name
Test status
Simulation time 487083500965 ps
CPU time 781.74 seconds
Started Jul 17 05:37:22 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 201532 kb
Host smart-0d7d43cc-ce49-4166-81fd-8b3f68962453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718816007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3718816007
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2249803651
Short name T549
Test name
Test status
Simulation time 493099161849 ps
CPU time 772.13 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:50:13 PM PDT 24
Peak memory 201444 kb
Host smart-a607f7cf-08ab-4219-856c-fd73211d8abb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249803651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2249803651
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1399986806
Short name T761
Test name
Test status
Simulation time 168590744211 ps
CPU time 364.8 seconds
Started Jul 17 05:37:21 PM PDT 24
Finished Jul 17 05:43:27 PM PDT 24
Peak memory 201560 kb
Host smart-af3805b5-434e-4c66-a995-53457e4a37bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399986806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1399986806
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2448380711
Short name T749
Test name
Test status
Simulation time 481473024195 ps
CPU time 171.56 seconds
Started Jul 17 05:37:21 PM PDT 24
Finished Jul 17 05:40:13 PM PDT 24
Peak memory 201476 kb
Host smart-2abf989f-e798-4328-9703-8d66a9a2c3ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448380711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2448380711
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.725041157
Short name T151
Test name
Test status
Simulation time 346327588290 ps
CPU time 784.56 seconds
Started Jul 17 05:37:23 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 201580 kb
Host smart-350baf1c-5609-4e11-9ce1-1bc8aa6376e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725041157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.725041157
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2768535821
Short name T379
Test name
Test status
Simulation time 601957092250 ps
CPU time 1286.54 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:58:48 PM PDT 24
Peak memory 201524 kb
Host smart-740f1369-7baf-4c63-ab4c-a79915002c37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768535821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2768535821
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.323823770
Short name T535
Test name
Test status
Simulation time 85332009107 ps
CPU time 425.52 seconds
Started Jul 17 05:37:32 PM PDT 24
Finished Jul 17 05:44:39 PM PDT 24
Peak memory 201840 kb
Host smart-2379553c-997a-4070-a67f-0bdc42ff26aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323823770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.323823770
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2132203616
Short name T729
Test name
Test status
Simulation time 24026109792 ps
CPU time 15.47 seconds
Started Jul 17 05:37:32 PM PDT 24
Finished Jul 17 05:37:50 PM PDT 24
Peak memory 201328 kb
Host smart-f1cdd201-de00-4db8-a4fa-61dc0ab3207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132203616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2132203616
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1628273032
Short name T340
Test name
Test status
Simulation time 3878896144 ps
CPU time 1.15 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:37:22 PM PDT 24
Peak memory 201336 kb
Host smart-81f64964-b1e9-4eb9-b5ed-a1c2af29f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628273032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1628273032
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3246434157
Short name T615
Test name
Test status
Simulation time 5678866703 ps
CPU time 13.79 seconds
Started Jul 17 05:37:20 PM PDT 24
Finished Jul 17 05:37:34 PM PDT 24
Peak memory 201248 kb
Host smart-74452360-a552-4842-a85a-3384b8bfe24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246434157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3246434157
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3585694178
Short name T33
Test name
Test status
Simulation time 126061815591 ps
CPU time 163.21 seconds
Started Jul 17 05:37:33 PM PDT 24
Finished Jul 17 05:40:18 PM PDT 24
Peak memory 211352 kb
Host smart-21dc08a8-b315-44f8-8d4f-6ad321583b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585694178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3585694178
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1897324619
Short name T441
Test name
Test status
Simulation time 346270809 ps
CPU time 1.02 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:37:46 PM PDT 24
Peak memory 201284 kb
Host smart-a5b53e02-bded-4175-963b-0fde59d8e164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897324619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1897324619
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2997384231
Short name T181
Test name
Test status
Simulation time 331853519881 ps
CPU time 104.72 seconds
Started Jul 17 05:37:37 PM PDT 24
Finished Jul 17 05:39:23 PM PDT 24
Peak memory 201380 kb
Host smart-0c51fe52-adb8-4ac1-834b-1853699d17c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997384231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2997384231
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3328937194
Short name T193
Test name
Test status
Simulation time 159306848454 ps
CPU time 374.49 seconds
Started Jul 17 05:37:32 PM PDT 24
Finished Jul 17 05:43:49 PM PDT 24
Peak memory 201540 kb
Host smart-d9175669-df6a-45c7-a7b6-41f0cc833d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328937194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3328937194
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.192618768
Short name T260
Test name
Test status
Simulation time 162261957808 ps
CPU time 192.37 seconds
Started Jul 17 05:37:33 PM PDT 24
Finished Jul 17 05:40:48 PM PDT 24
Peak memory 201520 kb
Host smart-5fb76360-1686-4c26-a39d-a1b59266bfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192618768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.192618768
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1476422190
Short name T606
Test name
Test status
Simulation time 163579092053 ps
CPU time 95.24 seconds
Started Jul 17 05:37:33 PM PDT 24
Finished Jul 17 05:39:10 PM PDT 24
Peak memory 201444 kb
Host smart-7ef4b4dd-41d7-4276-9c0d-d0bc83946017
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476422190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1476422190
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2300023247
Short name T498
Test name
Test status
Simulation time 326179552461 ps
CPU time 394.3 seconds
Started Jul 17 05:37:33 PM PDT 24
Finished Jul 17 05:44:10 PM PDT 24
Peak memory 201572 kb
Host smart-adabf42c-a77a-4d00-bc4c-bf2d073feb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300023247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2300023247
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4117195892
Short name T545
Test name
Test status
Simulation time 493382143326 ps
CPU time 1126.94 seconds
Started Jul 17 05:37:32 PM PDT 24
Finished Jul 17 05:56:20 PM PDT 24
Peak memory 201600 kb
Host smart-3872731d-72a4-4c88-82ff-fbeae66fbbd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117195892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4117195892
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3826423251
Short name T143
Test name
Test status
Simulation time 529500375638 ps
CPU time 228.67 seconds
Started Jul 17 05:37:37 PM PDT 24
Finished Jul 17 05:41:27 PM PDT 24
Peak memory 201460 kb
Host smart-32dc3f1f-645f-40b6-86ad-4fa7e8a5006a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826423251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3826423251
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2298276593
Short name T619
Test name
Test status
Simulation time 602685607177 ps
CPU time 1396.45 seconds
Started Jul 17 05:37:38 PM PDT 24
Finished Jul 17 06:00:55 PM PDT 24
Peak memory 201376 kb
Host smart-ada337f0-13e1-4d16-b16e-122d37a35014
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298276593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2298276593
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3253245535
Short name T319
Test name
Test status
Simulation time 96374083591 ps
CPU time 366.78 seconds
Started Jul 17 05:37:38 PM PDT 24
Finished Jul 17 05:43:46 PM PDT 24
Peak memory 201772 kb
Host smart-c9ed953f-4685-4d4c-b6be-e2ed124fc068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253245535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3253245535
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3766794810
Short name T526
Test name
Test status
Simulation time 22780383244 ps
CPU time 48.72 seconds
Started Jul 17 05:37:32 PM PDT 24
Finished Jul 17 05:38:23 PM PDT 24
Peak memory 201324 kb
Host smart-d6ac22d8-de70-42a5-8942-20c1da3398ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766794810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3766794810
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2877843425
Short name T724
Test name
Test status
Simulation time 5028329506 ps
CPU time 6.6 seconds
Started Jul 17 05:37:33 PM PDT 24
Finished Jul 17 05:37:42 PM PDT 24
Peak memory 201320 kb
Host smart-b904f58f-c7ee-41fb-97dc-668fb91dad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877843425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2877843425
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1221600919
Short name T737
Test name
Test status
Simulation time 5659520742 ps
CPU time 3.83 seconds
Started Jul 17 05:37:38 PM PDT 24
Finished Jul 17 05:37:42 PM PDT 24
Peak memory 201192 kb
Host smart-a9767150-3777-4a1a-bd58-fca0e645aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221600919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1221600919
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2363299576
Short name T186
Test name
Test status
Simulation time 97530289075 ps
CPU time 257.67 seconds
Started Jul 17 05:37:46 PM PDT 24
Finished Jul 17 05:42:05 PM PDT 24
Peak memory 217948 kb
Host smart-d5b4daee-29d6-4ec9-8214-2af416363573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363299576 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2363299576
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1257737323
Short name T485
Test name
Test status
Simulation time 358957082 ps
CPU time 1.4 seconds
Started Jul 17 05:37:57 PM PDT 24
Finished Jul 17 05:37:59 PM PDT 24
Peak memory 201276 kb
Host smart-c75f6d2c-ef36-4cc7-bfad-c7cfbb77a177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257737323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1257737323
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.697404066
Short name T167
Test name
Test status
Simulation time 348723267373 ps
CPU time 203.67 seconds
Started Jul 17 05:37:43 PM PDT 24
Finished Jul 17 05:41:08 PM PDT 24
Peak memory 201476 kb
Host smart-7e302a4a-c4df-44fd-a7b0-497b99b30ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697404066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.697404066
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2064561026
Short name T290
Test name
Test status
Simulation time 337219127700 ps
CPU time 775.2 seconds
Started Jul 17 05:37:45 PM PDT 24
Finished Jul 17 05:50:42 PM PDT 24
Peak memory 201532 kb
Host smart-fb74db25-10d8-407d-a171-b096227ddca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064561026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2064561026
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.236075849
Short name T552
Test name
Test status
Simulation time 164743539299 ps
CPU time 92.75 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:39:18 PM PDT 24
Peak memory 201512 kb
Host smart-7c5c44ee-ef26-4b54-aef5-fc96d42908c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=236075849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.236075849
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2729074926
Short name T273
Test name
Test status
Simulation time 330819380161 ps
CPU time 824.67 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:51:30 PM PDT 24
Peak memory 201580 kb
Host smart-30284583-c16e-4dad-9f0b-0650b82b2e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729074926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2729074926
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3538161259
Short name T726
Test name
Test status
Simulation time 161023384731 ps
CPU time 128.19 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:39:54 PM PDT 24
Peak memory 201592 kb
Host smart-e160b49e-dcff-41a4-86e1-40b25dd731f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538161259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3538161259
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2869115537
Short name T663
Test name
Test status
Simulation time 204248290784 ps
CPU time 67.2 seconds
Started Jul 17 05:37:43 PM PDT 24
Finished Jul 17 05:38:52 PM PDT 24
Peak memory 201572 kb
Host smart-ea9da898-c029-4c2a-b562-037cff18e835
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869115537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2869115537
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1886565072
Short name T324
Test name
Test status
Simulation time 102586082995 ps
CPU time 558.56 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:47:15 PM PDT 24
Peak memory 201888 kb
Host smart-2bedef65-f409-4aab-ac73-2c21560d3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886565072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1886565072
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3591906712
Short name T349
Test name
Test status
Simulation time 28371284538 ps
CPU time 64.59 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:39:02 PM PDT 24
Peak memory 201336 kb
Host smart-7c678e3d-f87f-414a-865d-5d1369beb2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591906712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3591906712
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.621234592
Short name T667
Test name
Test status
Simulation time 4641270977 ps
CPU time 10.05 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:37:56 PM PDT 24
Peak memory 201328 kb
Host smart-7d3a8edd-9c13-4291-b0a5-f689fce5b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621234592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.621234592
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2061420459
Short name T511
Test name
Test status
Simulation time 5760469498 ps
CPU time 3.82 seconds
Started Jul 17 05:37:44 PM PDT 24
Finished Jul 17 05:37:50 PM PDT 24
Peak memory 201260 kb
Host smart-09aa3180-a495-4c42-80c7-ef3691537ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061420459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2061420459
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3646982986
Short name T677
Test name
Test status
Simulation time 275566966894 ps
CPU time 472.4 seconds
Started Jul 17 05:37:57 PM PDT 24
Finished Jul 17 05:45:50 PM PDT 24
Peak memory 210140 kb
Host smart-a11899c4-93c3-4e28-9225-24a41300773c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646982986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3646982986
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2191518214
Short name T680
Test name
Test status
Simulation time 52582381472 ps
CPU time 100.91 seconds
Started Jul 17 05:37:57 PM PDT 24
Finished Jul 17 05:39:39 PM PDT 24
Peak memory 210276 kb
Host smart-3775f050-7a41-4cef-9dae-fca76cf9f799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191518214 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2191518214
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2667406803
Short name T790
Test name
Test status
Simulation time 336923504 ps
CPU time 0.98 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:37:58 PM PDT 24
Peak memory 201240 kb
Host smart-c246d721-8aed-4990-aa15-0545673cce65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667406803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2667406803
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.945334560
Short name T298
Test name
Test status
Simulation time 360999295909 ps
CPU time 827.44 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:51:44 PM PDT 24
Peak memory 201536 kb
Host smart-71713865-2a06-489f-aebf-d5b917fd45ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945334560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.945334560
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4258701747
Short name T690
Test name
Test status
Simulation time 163803750212 ps
CPU time 386.31 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:44:23 PM PDT 24
Peak memory 201476 kb
Host smart-20f485b0-d239-4111-8adf-cd9ff52f24c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258701747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4258701747
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1400622953
Short name T744
Test name
Test status
Simulation time 507783837917 ps
CPU time 322.94 seconds
Started Jul 17 05:37:58 PM PDT 24
Finished Jul 17 05:43:22 PM PDT 24
Peak memory 201700 kb
Host smart-1a27bd5c-a865-479c-b569-22cdacb94218
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400622953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1400622953
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.286146943
Short name T682
Test name
Test status
Simulation time 492899914339 ps
CPU time 541.62 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:46:59 PM PDT 24
Peak memory 201548 kb
Host smart-6dc238a6-c45d-41c6-bb1e-e514f7791486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286146943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.286146943
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4214385699
Short name T577
Test name
Test status
Simulation time 331319203817 ps
CPU time 765.44 seconds
Started Jul 17 05:37:57 PM PDT 24
Finished Jul 17 05:50:43 PM PDT 24
Peak memory 201692 kb
Host smart-392fe31e-2cb2-4f04-9c2b-dd0fa1a1e801
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214385699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4214385699
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2910510718
Short name T277
Test name
Test status
Simulation time 638289928358 ps
CPU time 1440.83 seconds
Started Jul 17 05:37:54 PM PDT 24
Finished Jul 17 06:01:56 PM PDT 24
Peak memory 201792 kb
Host smart-439cb9a7-fe3a-4e90-ad55-0ece6d43570f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910510718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2910510718
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3186259751
Short name T517
Test name
Test status
Simulation time 205573787042 ps
CPU time 217.94 seconds
Started Jul 17 05:37:57 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 201372 kb
Host smart-a89cad20-e6e0-407a-aa1c-5f58355f647a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186259751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3186259751
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3393698803
Short name T605
Test name
Test status
Simulation time 95476440540 ps
CPU time 316.06 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:43:13 PM PDT 24
Peak memory 201828 kb
Host smart-56f6541b-9c17-491c-bf8f-94638798ef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393698803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3393698803
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2965403198
Short name T370
Test name
Test status
Simulation time 23647462013 ps
CPU time 13.35 seconds
Started Jul 17 05:37:59 PM PDT 24
Finished Jul 17 05:38:13 PM PDT 24
Peak memory 201328 kb
Host smart-8bfa4422-fcf4-4405-86cb-0f8d05ee7473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965403198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2965403198
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1750095012
Short name T338
Test name
Test status
Simulation time 4404947121 ps
CPU time 3.17 seconds
Started Jul 17 05:37:59 PM PDT 24
Finished Jul 17 05:38:02 PM PDT 24
Peak memory 201324 kb
Host smart-536e020f-dcc5-4f5f-bb08-6045164a8a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750095012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1750095012
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3944757041
Short name T348
Test name
Test status
Simulation time 5894617669 ps
CPU time 2.11 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:37:59 PM PDT 24
Peak memory 201248 kb
Host smart-2fc9479a-10a3-4d82-8280-798b0df2bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944757041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3944757041
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3537468068
Short name T766
Test name
Test status
Simulation time 194829011793 ps
CPU time 225.74 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:41:43 PM PDT 24
Peak memory 201404 kb
Host smart-a3a4504f-ece2-40eb-8e9d-f875bbe56c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537468068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3537468068
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2986876949
Short name T721
Test name
Test status
Simulation time 115985378223 ps
CPU time 367.29 seconds
Started Jul 17 05:37:56 PM PDT 24
Finished Jul 17 05:44:04 PM PDT 24
Peak memory 217888 kb
Host smart-d3f5cd47-a5d6-482c-9f86-ed983faaa406
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986876949 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2986876949
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2328440414
Short name T390
Test name
Test status
Simulation time 306881924 ps
CPU time 1.32 seconds
Started Jul 17 05:32:05 PM PDT 24
Finished Jul 17 05:32:07 PM PDT 24
Peak memory 201200 kb
Host smart-51c36f19-2d97-4065-804b-655aa5341e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328440414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2328440414
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2754501002
Short name T704
Test name
Test status
Simulation time 164613230256 ps
CPU time 321.03 seconds
Started Jul 17 05:32:04 PM PDT 24
Finished Jul 17 05:37:26 PM PDT 24
Peak memory 201764 kb
Host smart-27857001-e1cc-44f5-91eb-74f6a47a4b30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754501002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2754501002
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1577195938
Short name T518
Test name
Test status
Simulation time 532360561268 ps
CPU time 1257.38 seconds
Started Jul 17 05:32:08 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 201548 kb
Host smart-6b7d21d0-8c0e-4d0f-b237-993e8bc22c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577195938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1577195938
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1402562949
Short name T717
Test name
Test status
Simulation time 161947671272 ps
CPU time 86.25 seconds
Started Jul 17 05:32:05 PM PDT 24
Finished Jul 17 05:33:32 PM PDT 24
Peak memory 201492 kb
Host smart-f35a45e6-0948-4ec1-8bac-410531bc6c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402562949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1402562949
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2279639829
Short name T180
Test name
Test status
Simulation time 167658959659 ps
CPU time 105.57 seconds
Started Jul 17 05:32:12 PM PDT 24
Finished Jul 17 05:33:58 PM PDT 24
Peak memory 201464 kb
Host smart-48756219-07f4-40fb-b637-322b480188e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279639829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2279639829
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.138717482
Short name T24
Test name
Test status
Simulation time 486240654916 ps
CPU time 189.29 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:37:17 PM PDT 24
Peak memory 201580 kb
Host smart-8699021e-784f-4de7-a3b4-c83253038653
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=138717482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.138717482
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2568756463
Short name T693
Test name
Test status
Simulation time 601912480779 ps
CPU time 647.98 seconds
Started Jul 17 05:32:05 PM PDT 24
Finished Jul 17 05:42:54 PM PDT 24
Peak memory 201476 kb
Host smart-0ea800f9-33be-43dc-855d-a3d8305969cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568756463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2568756463
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1778136121
Short name T621
Test name
Test status
Simulation time 129694159674 ps
CPU time 681.68 seconds
Started Jul 17 05:32:06 PM PDT 24
Finished Jul 17 05:43:29 PM PDT 24
Peak memory 201888 kb
Host smart-4df36e0b-4733-4c54-a7d8-f958f088b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778136121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1778136121
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3974810465
Short name T733
Test name
Test status
Simulation time 45066064779 ps
CPU time 52.57 seconds
Started Jul 17 05:32:15 PM PDT 24
Finished Jul 17 05:33:08 PM PDT 24
Peak memory 201332 kb
Host smart-97f92dfc-bb8e-4902-8909-6b4ea3d071ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974810465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3974810465
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3502372636
Short name T573
Test name
Test status
Simulation time 5358669316 ps
CPU time 4.05 seconds
Started Jul 17 05:33:07 PM PDT 24
Finished Jul 17 05:33:11 PM PDT 24
Peak memory 201324 kb
Host smart-bdc98098-5723-4c56-8c14-6d692a25f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502372636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3502372636
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.778527822
Short name T344
Test name
Test status
Simulation time 5822558052 ps
CPU time 14.43 seconds
Started Jul 17 05:32:10 PM PDT 24
Finished Jul 17 05:32:25 PM PDT 24
Peak memory 201328 kb
Host smart-7bad9a94-10d5-4728-8daa-4af0ff849d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778527822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.778527822
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.55662806
Short name T752
Test name
Test status
Simulation time 197427561110 ps
CPU time 272.8 seconds
Started Jul 17 05:32:06 PM PDT 24
Finished Jul 17 05:36:40 PM PDT 24
Peak memory 201592 kb
Host smart-fa8a1b80-5c45-4d0c-a3b3-cc11d36656ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55662806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.55662806
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3391506158
Short name T16
Test name
Test status
Simulation time 415950597968 ps
CPU time 178.6 seconds
Started Jul 17 05:32:03 PM PDT 24
Finished Jul 17 05:35:03 PM PDT 24
Peak memory 212248 kb
Host smart-d1b76514-09fd-4c9e-94d4-cb35340a3add
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391506158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3391506158
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2665260734
Short name T661
Test name
Test status
Simulation time 433136790 ps
CPU time 0.88 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:34:09 PM PDT 24
Peak memory 201288 kb
Host smart-820bf9fe-a5c7-4613-891e-240210a5265c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665260734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2665260734
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.666685253
Short name T515
Test name
Test status
Simulation time 328019727309 ps
CPU time 367.87 seconds
Started Jul 17 05:32:15 PM PDT 24
Finished Jul 17 05:38:23 PM PDT 24
Peak memory 201584 kb
Host smart-a8c3e1d9-9bb8-46ca-ade0-d91180fd5473
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666685253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.666685253
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1988350617
Short name T157
Test name
Test status
Simulation time 164968521596 ps
CPU time 102.1 seconds
Started Jul 17 05:33:43 PM PDT 24
Finished Jul 17 05:35:26 PM PDT 24
Peak memory 201512 kb
Host smart-eea07f83-3771-4500-bb6d-eef085d6f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988350617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1988350617
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.12445985
Short name T584
Test name
Test status
Simulation time 161058453011 ps
CPU time 366.32 seconds
Started Jul 17 05:32:09 PM PDT 24
Finished Jul 17 05:38:16 PM PDT 24
Peak memory 201532 kb
Host smart-6d2b6036-10c2-4b50-bb48-c062c98b8e6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_
fixed.12445985
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3720552839
Short name T459
Test name
Test status
Simulation time 322806577680 ps
CPU time 697.57 seconds
Started Jul 17 05:32:06 PM PDT 24
Finished Jul 17 05:43:45 PM PDT 24
Peak memory 201468 kb
Host smart-f4050cc6-23c0-4d18-92b6-2b2bbf2f1fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720552839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3720552839
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1813726121
Short name T588
Test name
Test status
Simulation time 495099866280 ps
CPU time 554.28 seconds
Started Jul 17 05:32:06 PM PDT 24
Finished Jul 17 05:41:21 PM PDT 24
Peak memory 201580 kb
Host smart-b246f521-0ff6-4c75-a4a8-a24aeac70179
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813726121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1813726121
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.838153679
Short name T233
Test name
Test status
Simulation time 428942812065 ps
CPU time 226.62 seconds
Started Jul 17 05:32:13 PM PDT 24
Finished Jul 17 05:36:00 PM PDT 24
Peak memory 201612 kb
Host smart-9c3932a2-6e75-471a-995d-cc4187350731
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838153679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.838153679
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2756333285
Short name T432
Test name
Test status
Simulation time 603413167833 ps
CPU time 1307.57 seconds
Started Jul 17 05:32:06 PM PDT 24
Finished Jul 17 05:53:54 PM PDT 24
Peak memory 201568 kb
Host smart-05b4114c-c231-42d0-8dfe-1743a94d58d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756333285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2756333285
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2151070444
Short name T44
Test name
Test status
Simulation time 126045345073 ps
CPU time 730.43 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:46:00 PM PDT 24
Peak memory 201888 kb
Host smart-b6b60292-a482-4907-a7b6-40d5eaaae8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151070444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2151070444
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1153353416
Short name T81
Test name
Test status
Simulation time 44048881236 ps
CPU time 28.92 seconds
Started Jul 17 05:32:07 PM PDT 24
Finished Jul 17 05:32:37 PM PDT 24
Peak memory 201324 kb
Host smart-d70f6747-dfce-4123-81ae-8d0a10f5c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153353416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1153353416
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.521180486
Short name T496
Test name
Test status
Simulation time 3944713230 ps
CPU time 9.95 seconds
Started Jul 17 05:32:07 PM PDT 24
Finished Jul 17 05:32:17 PM PDT 24
Peak memory 201300 kb
Host smart-c168c70f-f933-4816-9455-543fb83d1cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521180486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.521180486
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.993330480
Short name T727
Test name
Test status
Simulation time 5727036279 ps
CPU time 7.23 seconds
Started Jul 17 05:32:08 PM PDT 24
Finished Jul 17 05:32:16 PM PDT 24
Peak memory 201332 kb
Host smart-be9ac81d-1c6d-4809-868a-4ea1f4bcf4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993330480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.993330480
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3389754727
Short name T28
Test name
Test status
Simulation time 170570341057 ps
CPU time 375.36 seconds
Started Jul 17 05:33:09 PM PDT 24
Finished Jul 17 05:39:26 PM PDT 24
Peak memory 201476 kb
Host smart-ca590518-a3b0-46d6-80ba-2ff9d408c656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389754727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3389754727
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3084027190
Short name T4
Test name
Test status
Simulation time 32874409433 ps
CPU time 45.67 seconds
Started Jul 17 05:32:05 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 209924 kb
Host smart-f4ba8dca-5add-4149-ae25-4740903de382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084027190 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3084027190
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1088329777
Short name T361
Test name
Test status
Simulation time 430001966 ps
CPU time 1.08 seconds
Started Jul 17 05:33:00 PM PDT 24
Finished Jul 17 05:33:02 PM PDT 24
Peak memory 201204 kb
Host smart-95079b35-05c8-4c50-a1c9-e6dcc540b12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088329777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1088329777
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.741142719
Short name T431
Test name
Test status
Simulation time 502676736375 ps
CPU time 1107.64 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 201480 kb
Host smart-6b62991d-5473-45b9-ade2-37ab0e64d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741142719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.741142719
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4189198361
Short name T201
Test name
Test status
Simulation time 494953802645 ps
CPU time 1212.48 seconds
Started Jul 17 05:32:59 PM PDT 24
Finished Jul 17 05:53:13 PM PDT 24
Peak memory 201464 kb
Host smart-bf0545a9-dba2-4f80-9a21-554274a1dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189198361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4189198361
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2324159460
Short name T343
Test name
Test status
Simulation time 165127505493 ps
CPU time 386.85 seconds
Started Jul 17 05:32:54 PM PDT 24
Finished Jul 17 05:39:22 PM PDT 24
Peak memory 201440 kb
Host smart-cc0a5f68-beb9-473a-bb95-9178417d3a4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324159460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2324159460
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3749638999
Short name T297
Test name
Test status
Simulation time 492009901593 ps
CPU time 540.65 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:41:59 PM PDT 24
Peak memory 201544 kb
Host smart-0be358de-e10e-4a52-9cfe-c921d0b2b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749638999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3749638999
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3864834297
Short name T479
Test name
Test status
Simulation time 334871300061 ps
CPU time 408.18 seconds
Started Jul 17 05:32:58 PM PDT 24
Finished Jul 17 05:39:48 PM PDT 24
Peak memory 201520 kb
Host smart-9bb1e2cc-a10f-4e26-b0ad-4903004fc27c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864834297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3864834297
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2129900498
Short name T222
Test name
Test status
Simulation time 374916389295 ps
CPU time 442.79 seconds
Started Jul 17 05:34:00 PM PDT 24
Finished Jul 17 05:41:24 PM PDT 24
Peak memory 201616 kb
Host smart-b380fb8b-6e24-4533-a98e-d797d36f1060
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129900498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2129900498
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.144147805
Short name T710
Test name
Test status
Simulation time 604080962707 ps
CPU time 678.5 seconds
Started Jul 17 05:35:41 PM PDT 24
Finished Jul 17 05:47:00 PM PDT 24
Peak memory 201524 kb
Host smart-15f18042-29ba-498b-8134-38bc246fcadb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144147805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.144147805
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4104467946
Short name T320
Test name
Test status
Simulation time 94016226989 ps
CPU time 457.64 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:40:36 PM PDT 24
Peak memory 201960 kb
Host smart-8c6ad3be-28d4-431e-b0ea-c53bcf995bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104467946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4104467946
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.128161028
Short name T639
Test name
Test status
Simulation time 29770718881 ps
CPU time 16.42 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:22 PM PDT 24
Peak memory 201264 kb
Host smart-1047aa61-d99b-41e4-a2d5-df66e4c09cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128161028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.128161028
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2934610090
Short name T374
Test name
Test status
Simulation time 3573905958 ps
CPU time 5.6 seconds
Started Jul 17 05:33:01 PM PDT 24
Finished Jul 17 05:33:08 PM PDT 24
Peak memory 201256 kb
Host smart-3e753f52-e0a2-4c4f-88a7-e6fcf1a3f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934610090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2934610090
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4098677042
Short name T768
Test name
Test status
Simulation time 5531246754 ps
CPU time 14.19 seconds
Started Jul 17 05:32:59 PM PDT 24
Finished Jul 17 05:33:15 PM PDT 24
Peak memory 201264 kb
Host smart-78882d7c-2613-4c86-8ece-1b8549dcb2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098677042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4098677042
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.897593286
Short name T285
Test name
Test status
Simulation time 517212352945 ps
CPU time 1146.45 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:52:05 PM PDT 24
Peak memory 201544 kb
Host smart-117700d1-22fd-49dd-b987-a95cb77ff663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897593286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.897593286
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2614277363
Short name T743
Test name
Test status
Simulation time 22976285279 ps
CPU time 54.67 seconds
Started Jul 17 05:33:59 PM PDT 24
Finished Jul 17 05:34:55 PM PDT 24
Peak memory 210308 kb
Host smart-9d61322e-f3e9-4f61-85c9-490ece833d45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614277363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2614277363
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3060833799
Short name T456
Test name
Test status
Simulation time 347454850 ps
CPU time 1.09 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:34:18 PM PDT 24
Peak memory 201228 kb
Host smart-2f37708b-cccd-4dd5-b7e5-250017ceb393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060833799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3060833799
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.372598705
Short name T503
Test name
Test status
Simulation time 334361002186 ps
CPU time 377.1 seconds
Started Jul 17 05:34:01 PM PDT 24
Finished Jul 17 05:40:19 PM PDT 24
Peak memory 201508 kb
Host smart-da73c17f-ea9c-4ebf-826f-8c248e666c8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372598705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.372598705
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3692746081
Short name T212
Test name
Test status
Simulation time 352983346990 ps
CPU time 841.3 seconds
Started Jul 17 05:34:06 PM PDT 24
Finished Jul 17 05:48:09 PM PDT 24
Peak memory 201512 kb
Host smart-66ca5da7-7535-463d-a299-f9688aa7f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692746081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3692746081
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1843676436
Short name T455
Test name
Test status
Simulation time 491195734637 ps
CPU time 591.98 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:43:40 PM PDT 24
Peak memory 201536 kb
Host smart-ef122157-f3ed-48a1-800d-d591dca4033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843676436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1843676436
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.543506249
Short name T104
Test name
Test status
Simulation time 168408931969 ps
CPU time 31.35 seconds
Started Jul 17 05:39:45 PM PDT 24
Finished Jul 17 05:40:17 PM PDT 24
Peak memory 201568 kb
Host smart-39493b55-556a-4a7d-b1a2-c31232d58a7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=543506249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.543506249
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2845293417
Short name T97
Test name
Test status
Simulation time 160234395610 ps
CPU time 391.56 seconds
Started Jul 17 05:34:06 PM PDT 24
Finished Jul 17 05:40:39 PM PDT 24
Peak memory 201604 kb
Host smart-d2a6c8c2-1df3-4afb-968d-2280641aefa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845293417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2845293417
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.835508785
Short name T730
Test name
Test status
Simulation time 155801242215 ps
CPU time 79.59 seconds
Started Jul 17 05:32:59 PM PDT 24
Finished Jul 17 05:34:20 PM PDT 24
Peak memory 201504 kb
Host smart-dbc3470d-5bf8-41c9-a857-01a9fa21ab7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=835508785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.835508785
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.20113995
Short name T525
Test name
Test status
Simulation time 185806186233 ps
CPU time 221.63 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:36:40 PM PDT 24
Peak memory 201516 kb
Host smart-08ac9ce8-c3e3-406c-a3fa-2f5489c71f0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20113995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wa
keup.20113995
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2729538283
Short name T393
Test name
Test status
Simulation time 412495918156 ps
CPU time 251.25 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:38:22 PM PDT 24
Peak memory 201376 kb
Host smart-2911753e-c15c-4d98-9050-06817a773198
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729538283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2729538283
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1521127489
Short name T311
Test name
Test status
Simulation time 90254320282 ps
CPU time 460.22 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:41:21 PM PDT 24
Peak memory 201936 kb
Host smart-05d6c9f0-0728-4a88-ade1-af4a364d54f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521127489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1521127489
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.4082732
Short name T652
Test name
Test status
Simulation time 25693790328 ps
CPU time 61.58 seconds
Started Jul 17 05:32:57 PM PDT 24
Finished Jul 17 05:34:01 PM PDT 24
Peak memory 201252 kb
Host smart-f733797f-c801-4484-98cf-f4b51b502dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.4082732
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.570493889
Short name T722
Test name
Test status
Simulation time 3701173831 ps
CPU time 4.66 seconds
Started Jul 17 05:32:57 PM PDT 24
Finished Jul 17 05:33:04 PM PDT 24
Peak memory 201316 kb
Host smart-0e7f720e-5bb8-4064-8a99-81eb4b01ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570493889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.570493889
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.530102173
Short name T385
Test name
Test status
Simulation time 5730288025 ps
CPU time 13.52 seconds
Started Jul 17 05:33:02 PM PDT 24
Finished Jul 17 05:33:16 PM PDT 24
Peak memory 201268 kb
Host smart-387f661c-8182-4d5e-a378-9f9df469b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530102173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.530102173
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1903797838
Short name T650
Test name
Test status
Simulation time 55134183701 ps
CPU time 114.15 seconds
Started Jul 17 05:33:01 PM PDT 24
Finished Jul 17 05:34:57 PM PDT 24
Peak memory 201448 kb
Host smart-258b2f17-2380-45ee-998a-0d96499518f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903797838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1903797838
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2190773284
Short name T427
Test name
Test status
Simulation time 470633144 ps
CPU time 0.84 seconds
Started Jul 17 05:33:41 PM PDT 24
Finished Jul 17 05:33:43 PM PDT 24
Peak memory 201288 kb
Host smart-1a6ee857-cba8-4fc7-b95a-39b9af5d1d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190773284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2190773284
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3721027130
Short name T50
Test name
Test status
Simulation time 329339472571 ps
CPU time 41.15 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:33:39 PM PDT 24
Peak memory 201520 kb
Host smart-5d3d3867-60c1-46ba-a7e8-9b717a3afc9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721027130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3721027130
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3412691441
Short name T282
Test name
Test status
Simulation time 498532366375 ps
CPU time 230.21 seconds
Started Jul 17 05:32:58 PM PDT 24
Finished Jul 17 05:36:50 PM PDT 24
Peak memory 201492 kb
Host smart-eb5823f2-690e-4fce-bb8e-dfadbc92d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412691441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3412691441
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2922718179
Short name T529
Test name
Test status
Simulation time 487703754560 ps
CPU time 163.59 seconds
Started Jul 17 05:32:58 PM PDT 24
Finished Jul 17 05:35:43 PM PDT 24
Peak memory 201560 kb
Host smart-219dada4-78ba-4e82-b95e-9c5627fbbbe7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922718179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2922718179
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1265772592
Short name T487
Test name
Test status
Simulation time 489363531309 ps
CPU time 957.29 seconds
Started Jul 17 05:32:59 PM PDT 24
Finished Jul 17 05:48:57 PM PDT 24
Peak memory 201580 kb
Host smart-104d45e9-e557-4c15-9d27-06c2aae636c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265772592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1265772592
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.798440983
Short name T787
Test name
Test status
Simulation time 490505810990 ps
CPU time 1063.95 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:51:37 PM PDT 24
Peak memory 201536 kb
Host smart-2f9417fc-d32b-4695-a542-b40b4182c949
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=798440983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.798440983
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.312897566
Short name T709
Test name
Test status
Simulation time 179888525603 ps
CPU time 87.43 seconds
Started Jul 17 05:32:58 PM PDT 24
Finished Jul 17 05:34:27 PM PDT 24
Peak memory 201516 kb
Host smart-50a30635-151c-4450-afbf-e55e44396df6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312897566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.312897566
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2566359233
Short name T447
Test name
Test status
Simulation time 206099815811 ps
CPU time 254.77 seconds
Started Jul 17 05:34:01 PM PDT 24
Finished Jul 17 05:38:17 PM PDT 24
Peak memory 201436 kb
Host smart-6b2c25b2-a885-44d2-8b43-31108ef03e9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566359233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2566359233
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1976566829
Short name T620
Test name
Test status
Simulation time 92487037854 ps
CPU time 374.99 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:40:23 PM PDT 24
Peak memory 201896 kb
Host smart-076d515d-7aa7-4751-abc1-f75d8f763e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976566829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1976566829
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.783062763
Short name T658
Test name
Test status
Simulation time 40070722497 ps
CPU time 21.61 seconds
Started Jul 17 05:33:01 PM PDT 24
Finished Jul 17 05:33:24 PM PDT 24
Peak memory 201236 kb
Host smart-fffc2aaf-d73e-4654-92d3-8a6ed0d5ff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783062763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.783062763
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3948336231
Short name T474
Test name
Test status
Simulation time 5202635358 ps
CPU time 4.01 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:33:01 PM PDT 24
Peak memory 201336 kb
Host smart-356124a9-7503-48f8-8a09-56c7e20917ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948336231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3948336231
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2137986333
Short name T575
Test name
Test status
Simulation time 6207606533 ps
CPU time 15.89 seconds
Started Jul 17 05:32:56 PM PDT 24
Finished Jul 17 05:33:14 PM PDT 24
Peak memory 201320 kb
Host smart-cfb0a03e-b5f7-456c-953f-fcfae8e704bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137986333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2137986333
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3299143923
Short name T767
Test name
Test status
Simulation time 232382752134 ps
CPU time 68.8 seconds
Started Jul 17 05:34:01 PM PDT 24
Finished Jul 17 05:35:11 PM PDT 24
Peak memory 201452 kb
Host smart-4f940a99-f0d9-45d9-bc53-eb8713cb547d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299143923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3299143923
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4114442856
Short name T611
Test name
Test status
Simulation time 42692297271 ps
CPU time 120.73 seconds
Started Jul 17 05:32:57 PM PDT 24
Finished Jul 17 05:35:00 PM PDT 24
Peak memory 210192 kb
Host smart-47eb07fc-af3f-4949-acdc-f79156ed6c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114442856 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4114442856
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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