Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7251	1			T5	73		T9	40		T10	58
testmodes[AdcCtrlTestmodeNormal]	5818	1			T1	1		T4	1		T5	26
testmodes[AdcCtrlTestmodeLowpower]	5888	1			T2	1		T3	12		T5	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3871	1			T5	55		T9	9		T10	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1848	1			T5	11		T9	16		T10	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1424	1			T5	7		T9	15		T10	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1831	1			T5	14		T9	14		T10	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2139	1			T5	8		T9	21		T10	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1493	1			T5	3		T9	16		T10	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1446	1			T5	4		T9	17		T10	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1481	1			T5	6		T9	14		T10	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2725	1			T3	11		T5	5		T8	1