Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23764

1

T1

1

T2

26

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3379

1

T5

2

T6

13

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T3

12

T5

115

T7

2

auto[1]

5875

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	107	1			T58	3		T41	7		T205	28
values[1]	588	1			T5	2		T7	11		T43	19
values[2]	912	1			T119	6		T141	1		T206	13
values[3]	755	1			T118	1		T46	3		T27	16
values[4]	625	1			T6	13		T46	23		T38	5
values[5]	654	1			T35	26		T43	8		T119	25
values[6]	759	1			T37	29		T141	1		T22	17
values[7]	592	1			T2	26		T5	1		T119	25
values[8]	602	1			T37	6		T23	9		T162	13
values[9]	3499	1			T1	1		T4	8		T8	17
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	889	1			T5	2		T7	11		T43	19
values[1]	951	1			T141	1		T27	21		T128	18
values[2]	667	1			T118	1		T46	3		T27	16
values[3]	598	1			T46	23		T38	5		T22	13
values[4]	744	1			T6	13		T35	26		T43	8
values[5]	628	1			T2	26		T5	1		T37	29
values[6]	3115	1			T1	1		T4	8		T8	17
values[7]	545	1			T9	1		T23	9		T162	13
values[8]	773	1			T9	1		T35	23		T37	23
values[9]	183	1			T46	34		T57	14		T58	10
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	1		T43	4		T119	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T192	12		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T141	1		T27	10		T95	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T128	1		T13	16		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T27	14		T30	12		T95	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T118	1		T46	3		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	13		T38	2		T22	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T149	1		T172	1		T31	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T43	8		T23	7		T161	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	8		T35	13		T119	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	13		T5	1		T37	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T119	13		T23	7		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1659	1			T1	1		T4	1		T8	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T37	1		T38	5		T22	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	5		T162	7		T58	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	1		T89	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T35	11		T24	7		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	1		T37	15		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T46	17		T58	5		T208	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T57	7		T209	2		T210	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	10		T43	15		T12	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T192	9		T89	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	11		T129	11		T130	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T128	17		T13	12		T123	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T27	2		T30	13		T123	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T88	1		T50	14		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	10		T38	3		T57	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T31	8		T212	11		T213	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T23	13		T31	8		T214	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	5		T35	13		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	13		T37	17		T57	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T119	12		T23	4		T215	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T4	7		T127	25		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T37	5		T38	4		T27	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T23	4		T162	6		T58	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T89	8		T123	1		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	12		T206	5		T162	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T37	8		T191	1		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T46	17		T58	5		T216	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T57	7		T209	9		T210	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T41	4		T205	13		T217	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T58	3		T218	10		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	1		T43	4		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T192	12		T88	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T119	6		T141	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T40	5		T48	1		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T27	14		T57	13		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T118	1		T46	3		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	13		T38	2		T22	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	8		T172	1		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T43	8		T23	7		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	13		T119	13		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T37	12		T141	1		T57	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T22	17		T23	7		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	13		T5	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T119	13		T38	5		T27	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T23	5		T162	7		T58	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	1		T123	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1834	1			T1	1		T4	1		T8	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T9	2		T37	15		T57	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T41	3		T205	15		T213	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T219	1		T220	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	10		T43	15		T12	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T5	1		T192	9		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T206	12		T129	11		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T89	13		T123	11		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T27	2		T57	2		T122	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T128	17		T13	12		T88	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	10		T38	3		T30	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	5		T31	8		T212	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T23	13		T206	9		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T35	13		T119	12		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T37	17		T57	2		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T23	4		T215	13		T62	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T2	13		T176	9		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T119	12		T38	4		T27	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T23	4		T162	6		T58	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	5		T123	1		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T4	7		T35	12		T127	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T37	8		T57	7		T89	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T7	11		T43	16		T119	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	2		T192	10		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T141	1		T27	12		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T128	18		T13	16		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T27	3		T30	14		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T118	1		T46	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	11		T38	5		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	1		T172	1		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T43	1		T23	14		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	6		T35	14		T119	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	14		T5	1		T37	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T119	13		T23	5		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T1	1		T4	8		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T37	6		T38	5		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T23	5		T162	7		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T89	9		T123	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T35	13		T24	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	1		T37	9		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T46	18		T58	6		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T57	8		T209	11		T210	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T43	3		T119	5		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T192	11		T40	1		T58	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T27	9		T95	1		T129	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	12		T123	11		T143	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T27	13		T30	11		T95	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T46	2		T211	3		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	12		T22	12		T57	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T31	10		T222	5		T21	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	7		T23	6		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	7		T35	12		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T2	12		T37	11		T57	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T119	12		T23	6		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T8	15		T42	33		T44	39
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T38	4		T22	16		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T23	4		T162	6		T58	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	1		T223	13		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	10		T24	6		T224	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	14		T191	1		T225	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T46	16		T58	4		T208	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T57	6		T210	14		T226	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T41	6		T205	16		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T58	1		T218	1		T219	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	11		T43	16		T12	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	2		T192	10		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T119	1		T141	1		T206	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	4		T48	1		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	3		T57	3		T122	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T118	1		T46	1		T128	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	11		T38	5		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	6		T172	1		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T43	1		T23	14		T206	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T35	14		T119	13		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T37	18		T141	1		T57	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	1		T23	5		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	14		T5	1		T176	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T119	13		T38	5		T27	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T23	5		T162	7		T58	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	6		T123	2		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T1	1		T4	8		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	2		T37	9		T57	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T41	1		T205	12		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T58	2		T218	9		T220	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T43	3		T27	9		T95	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T192	11		T88	7		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T119	5		T129	9		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	1		T123	11		T143	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	13		T57	12		T95	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	2		T13	12		T211	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T46	12		T22	12		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	7		T31	10		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T43	7		T23	6		T161	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	12		T119	12		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	11		T57	1		T227	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T22	16		T23	6		T228	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	12		T163	23		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T119	12		T38	4		T27	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T23	4		T162	6		T58	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	3		T17	1		T209	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T8	15		T35	10		T42	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T37	14		T57	6		T191	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23945

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3198

1

T2

26

T5

3

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21014

1

T2

26

T3

12

T5

115

auto[1]

6129

1

T1

1

T4

8

T7

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T229	1		T230	6		-	-
values[0]	30	1			T231	17		T232	13		-	-
values[1]	541	1			T6	13		T37	29		T118	1
values[2]	680	1			T46	3		T119	31		T141	1
values[3]	794	1			T5	2		T9	1		T43	19
values[4]	3069	1			T1	1		T4	8		T8	17
values[5]	723	1			T38	5		T27	16		T128	18
values[6]	579	1			T22	30		T23	11		T24	7
values[7]	810	1			T2	26		T7	11		T46	34
values[8]	620	1			T43	8		T38	9		T30	25
values[9]	1240	1			T5	1		T35	49		T37	29
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	736	1			T6	13		T37	29		T118	1
values[1]	717	1			T5	2		T9	1		T119	6
values[2]	700	1			T43	19		T141	1		T23	9
values[3]	3130	1			T1	1		T4	8		T8	17
values[4]	705	1			T9	1		T38	5		T23	11
values[5]	639	1			T2	26		T46	34		T22	30
values[6]	783	1			T7	11		T119	25		T13	28
values[7]	621	1			T43	8		T23	20		T30	25
values[8]	844	1			T5	1		T35	23		T37	29
values[9]	208	1			T35	26		T57	15		T149	1
minimum	18060	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	8		T37	16		T206	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T118	1		T46	3		T119	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T184	1		T94	1		T233	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	1		T9	1		T119	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	4		T23	5		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T141	1		T27	12		T192	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1810	1			T1	1		T4	1		T8	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T215	1		T149	1		T214	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T38	2		T23	7		T88	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	1		T128	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T46	17		T22	30		T27	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	13		T24	7		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	16		T120	1		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	1		T119	13		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T23	7		T176	1		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	8		T30	12		T57	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	12		T38	5		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	1		T35	11		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T35	13		T57	13		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T132	1		T230	6		T234	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	5		T37	13		T206	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T119	12		T27	11		T57	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T236	11		T133	10		T213	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	1		T139	6		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	15		T23	4		T143	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	14		T192	9		T162	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T4	7		T127	25		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T215	13		T214	10		T237	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T38	3		T23	4		T88	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T128	17		T139	2		T123	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T46	17		T27	2		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	13		T58	5		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	12		T162	6		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	10		T119	12		T206	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T23	13		T176	9		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	13		T57	7		T89	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	17		T38	4		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T35	12		T46	10		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T35	13		T57	2		T239	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T234	10		T135	13		T240	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T235	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T229	1		T230	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T231	9		T232	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	8		T37	16		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T118	1		T141	1		T57	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T94	1		T229	1		T233	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	3		T119	19		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T43	4		T23	5		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T9	1		T27	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1775	1			T1	1		T4	1		T8	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T215	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T38	2		T27	14		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T128	1		T139	1		T95	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T22	30		T23	7		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	7		T120	1		T58	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T46	17		T120	1		T162	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	13		T7	1		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	5		T176	1		T13	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T43	8		T30	12		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T35	13		T37	12		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T5	1		T35	11		T46	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T231	8		T232	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	5		T37	13		T206	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T57	2		T241	2		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T213	3		T243	8		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T119	12		T27	11		T139	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	15		T23	4		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T27	14		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T4	7		T127	25		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T215	13		T123	1		T214	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	3		T27	2		T88	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T128	17		T139	2		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T23	4		T206	5		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T58	5		T123	1		T245	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	17		T162	6		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	13		T7	10		T119	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T38	4		T176	9		T13	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	13		T89	8		T241	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T35	13		T37	17		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T35	12		T46	10		T227	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2