Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21618

1

T3

12

T5

113

T6

13

auto[ADC_CTRL_FILTER_COND_OUT]

5525

1

T1

1

T2

26

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21052

1

T3

12

T5

114

T6

13

auto[1]

6091

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	274	1			T30	25		T215	14		T48	1
values[0]	29	1			T236	27		T252	1		T313	1
values[1]	591	1			T46	3		T119	25		T141	1
values[2]	831	1			T9	1		T35	23		T37	23
values[3]	628	1			T5	1		T43	8		T24	7
values[4]	520	1			T37	29		T119	25		T23	31
values[5]	715	1			T7	11		T37	6		T38	5
values[6]	597	1			T43	19		T27	21		T120	1
values[7]	844	1			T6	13		T9	1		T35	26
values[8]	632	1			T5	2		T46	34		T13	28
values[9]	3432	1			T1	1		T2	26		T4	8
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	715	1			T35	23		T119	25		T22	13
values[1]	3073	1			T1	1		T4	8		T8	17
values[2]	594	1			T5	1		T43	8		T24	7
values[3]	520	1			T37	29		T119	25		T23	31
values[4]	790	1			T7	11		T37	6		T38	5
values[5]	588	1			T9	1		T43	19		T27	21
values[6]	776	1			T6	13		T35	26		T118	1
values[7]	643	1			T5	2		T46	34		T13	28
values[8]	1044	1			T2	26		T46	23		T30	25
values[9]	146	1			T89	14		T249	4		T236	30
minimum	18254	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T35	11		T119	13		T22	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T27	14		T41	4		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T37	15		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1657	1			T1	1		T4	1		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T57	7		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T43	8		T24	7		T95	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T23	14		T14	9		T143	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	12		T119	13		T57	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	1		T120	1		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T38	2		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T89	1		T16	2		T225	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T43	4		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T6	8		T35	13		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	1		T12	3		T27	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	17		T184	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T13	16		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T30	12		T215	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T2	13		T46	13		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T236	16		T294	5		T301	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T89	1		T249	4		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17970	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T141	1		T236	17		T222	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	12		T119	12		T23	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T27	2		T41	3		T255	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T37	8		T38	4		T50	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	988	1			T4	7		T127	25		T29	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T57	7		T206	9		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T17	1		T214	10		T306	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T23	17		T14	3		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T37	17		T119	12		T57	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	5		T123	11		T31	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	10		T38	3		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T89	8		T133	10		T213	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T43	15		T27	11		T128	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	5		T35	13		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	2		T27	14		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	17		T242	8		T213	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	1		T13	12		T162	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T30	13		T215	13		T58	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	13		T46	10		T176	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T236	14		T294	3		T301	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T89	13		T315	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T236	10		T222	12		T196	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T30	12		T215	1		T48	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T285	8		T136	9		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T236	17		T252	1		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	3		T119	13		T22	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T141	1		T27	14		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	1		T35	11		T37	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	17		T228	8		T182	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T120	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	8		T24	7		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T23	14		T57	7		T14	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T37	12		T119	13		T57	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T37	1		T120	1		T123	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T38	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T89	1		T152	1		T225	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	4		T27	10		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	8		T35	13		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	1		T141	1		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	17		T149	2		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T13	16		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T58	14		T88	8		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1828	1			T1	1		T2	13		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T30	13		T215	13		T58	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T285	7		T316	15		T317	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T236	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T119	12		T23	4		T57	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T27	2		T41	3		T222	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T35	12		T37	8		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T291	10		T318	16		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T206	9		T211	2		T282	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T123	1		T17	1		T306	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T23	17		T57	7		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	17		T119	12		T57	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	5		T123	11		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	10		T38	3		T139	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T89	8		T242	14		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T43	15		T27	11		T206	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	5		T35	13		T295	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	2		T27	14		T128	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	17		T221	3		T213	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T13	12		T162	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T58	8		T224	6		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1090	1			T2	13		T4	7		T127	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	13		T119	13		T22	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	3		T41	6		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	1		T37	9		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1322	1			T1	1		T4	8		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T57	8		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T43	1		T24	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T23	19		T14	9		T143	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	18		T119	13		T57	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	6		T120	1		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	11		T38	5		T206	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T89	9		T16	2		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	1		T43	16		T27	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T6	6		T35	14		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T141	1		T12	5		T27	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	18		T184	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	2		T13	16		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T30	14		T215	14		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	14		T46	11		T176	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T236	15		T294	6		T301	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T89	14		T249	1		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18129	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T141	1		T236	11		T222	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T35	10		T119	12		T22	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T27	13		T41	1		T288	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	14		T38	4		T209	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1323	1			T8	15		T42	33		T44	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T57	6		T58	2		T228	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	7		T24	6		T95	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T23	12		T14	3		T143	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	11		T119	12		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T123	11		T31	10		T214	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	9		T237	11		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T225	15		T163	15		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T43	3		T27	9		T205	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	7		T35	12		T119	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T27	11		T17	2		T261	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	16		T242	12		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	12		T40	1		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	11		T58	17		T88	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	12		T46	12		T192	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T236	15		T294	2		T301	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T249	3		T315	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T46	2		T162	6		T247	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T236	16		T222	5		T226	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T30	14		T215	14		T48	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T285	8		T136	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T236	11		T252	1		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T46	1		T119	13		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T141	1		T27	3		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T9	1		T35	13		T37	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T22	1		T228	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T120	1		T206	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T43	1		T24	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T23	19		T57	8		T14	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	18		T119	13		T57	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	6		T120	1		T123	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	11		T38	5		T139	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T89	9		T152	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T43	16		T27	12		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T6	6		T35	14		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	1		T141	1		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	18		T149	2		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	2		T13	16		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T58	9		T88	1		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1448	1			T1	1		T2	14		T4	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	11		T58	4		T277	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T285	7		T136	8		T317	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T236	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	2		T119	12		T22	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T27	13		T41	1		T288	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T35	10		T37	14		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T22	16		T228	7		T182	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T58	2		T228	17		T211	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	7		T24	6		T95	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T23	12		T57	6		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T37	11		T119	12		T57	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	11		T31	10		T214	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T161	12		T129	9		T130	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T225	15		T163	15		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	3		T27	9		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	7		T35	12		T119	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	11		T205	12		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T46	16		T221	5		T213	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	12		T40	1		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T58	13		T88	7		T224	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1470	1			T2	12		T8	15		T42	33

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15