Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21573

1

T3

12

T5

113

T6

13

auto[ADC_CTRL_FILTER_COND_OUT]

5570

1

T1

1

T2

26

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21067

1

T3

12

T5

115

T6

13

auto[1]

6076

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T285	15		T255	1		T265	12
values[0]	54	1			T23	9		T236	27		T319	17
values[1]	592	1			T37	23		T46	3		T119	25
values[2]	864	1			T9	1		T35	23		T38	9
values[3]	571	1			T5	1		T43	8		T24	7
values[4]	517	1			T119	25		T23	20		T57	29
values[5]	703	1			T7	11		T37	35		T23	11
values[6]	619	1			T43	19		T118	1		T38	5
values[7]	887	1			T6	13		T9	1		T35	26
values[8]	579	1			T13	28		T121	1		T162	17
values[9]	3658	1			T1	1		T2	26		T4	8
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	812	1			T46	3		T119	25		T141	1
values[1]	3169	1			T1	1		T4	8		T8	17
values[2]	579	1			T5	1		T43	8		T38	9
values[3]	496	1			T37	29		T119	25		T23	31
values[4]	837	1			T7	11		T37	6		T43	19
values[5]	570	1			T9	1		T27	21		T128	18
values[6]	779	1			T6	13		T35	26		T118	1
values[7]	677	1			T5	2		T46	34		T13	28
values[8]	873	1			T46	23		T30	25		T176	10
values[9]	284	1			T2	26		T227	20		T89	14
minimum	18067	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T46	3		T119	13		T23	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T141	1		T27	14		T41	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	1		T35	11		T37	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1663	1			T1	1		T4	1		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T38	5		T57	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T43	8		T24	7		T95	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T23	14		T14	9		T143	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	12		T119	13		T57	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T37	1		T120	1		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T43	4		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T89	1		T16	2		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	1		T27	10		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	8		T35	13		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T141	1		T12	3		T27	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T46	17		T184	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	1		T13	16		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T30	12		T215	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T46	13		T176	1		T192	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T236	16		T294	5		T301	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T2	13		T227	9		T89	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17925	1			T3	12		T5	112		T9	140
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T119	12		T23	4		T57	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T27	2		T41	3		T236	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T35	12		T37	8		T143	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	996	1			T4	7		T127	25		T29	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T38	4		T57	7		T206	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T17	1		T214	10		T306	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T23	17		T14	3		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	17		T119	12		T57	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	5		T123	11		T31	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	10		T43	15		T38	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T89	8		T133	10		T213	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	11		T128	17		T88	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	5		T35	13		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	2		T27	14		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	17		T242	8		T213	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T13	12		T162	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	13		T215	13		T58	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	10		T176	9		T192	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T236	14		T294	3		T301	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T2	13		T227	11		T89	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T9	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T255	1		T265	12		T320	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T285	8		T315	5		T321	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T23	5		T319	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T236	17		T313	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T37	15		T46	3		T119	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T141	1		T27	14		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T9	1		T35	11		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	17		T228	8		T182	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T120	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	8		T24	7		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T23	7		T57	7		T14	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T119	13		T57	13		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	1		T23	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T37	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T118	1		T89	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	4		T38	2		T27	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	8		T35	13		T46	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T141	1		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T149	2		T184	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	16		T121	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T30	12		T215	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1851	1			T1	1		T2	13		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T320	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	7		T315	4		T321	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T23	4		T319	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T236	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	8		T119	12		T57	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T27	2		T41	3		T222	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T35	12		T38	4		T143	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T291	10		T318	16		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T206	9		T50	14		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T123	1		T17	1		T306	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T23	13		T57	7		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T119	12		T57	2		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	5		T23	4		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	10		T37	17		T139	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T89	8		T242	14		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T43	15		T38	3		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T6	5		T35	13		T46	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T27	14		T128	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T221	3		T213	11		T281	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	12		T162	16		T142	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T30	13		T215	13		T58	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1124	1			T2	13		T4	7		T5	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	1		T119	13		T23	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T141	1		T27	3		T41	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T9	1		T35	13		T37	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1332	1			T1	1		T4	8		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T38	5		T57	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T43	1		T24	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T23	19		T14	9		T143	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T37	18		T119	13		T57	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T37	6		T120	1		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	11		T43	16		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T89	9		T16	2		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	1		T27	12		T128	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	6		T35	14		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	1		T12	5		T27	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	18		T184	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	2		T13	16		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T30	14		T215	14		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	11		T176	10		T192	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T236	15		T294	6		T301	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T2	14		T227	12		T89	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18055	1			T3	12		T5	112		T7	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T46	2		T119	12		T23	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	13		T41	1		T236	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T35	10		T37	14		T143	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T8	15		T42	33		T44	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	4		T57	6		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	7		T24	6		T95	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T23	12		T14	3		T143	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	11		T119	12		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T123	11		T31	10		T214	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	3		T129	9		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T133	8		T266	2		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	9		T237	11		T205	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	7		T35	12		T119	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T27	11		T40	1		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	16		T242	12		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	12		T143	4		T124	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	11		T58	17		T88	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T46	12		T192	11		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T236	15		T294	2		T301	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T2	12		T227	8		T249	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T22	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T255	1		T265	1		T320	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T285	8		T315	5		T321	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T23	5		T319	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T236	11		T313	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	9		T46	1		T119	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T141	1		T27	3		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T9	1		T35	13		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T22	1		T228	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T120	1		T206	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	1		T24	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T23	14		T57	8		T14	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T119	13		T57	3		T206	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	6		T23	5		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	11		T37	18		T139	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T118	1		T89	9		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	16		T38	5		T27	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T6	6		T35	14		T46	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T141	1		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T149	2		T184	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	16		T121	1		T162	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T30	14		T215	14		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1491	1			T1	1		T2	14		T4	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T265	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T285	7		T315	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T23	4		T319	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T236	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T37	14		T46	2		T119	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T27	13		T41	1		T288	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T35	10		T38	4		T143	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T22	16		T228	7		T182	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T58	2		T211	3		T282	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	7		T24	6		T95	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T23	6		T57	6		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T119	12		T57	12		T161	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T23	6		T123	11		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	11		T31	5		T129	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T225	15		T163	15		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T43	3		T27	9		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	7		T35	12		T46	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	11		T205	12		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T221	5		T213	12		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	12		T40	1		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T30	11		T58	17		T88	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1484	1			T2	12		T8	15		T42	33

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15