Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23682

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3461

1

T2

26

T6

13

T35

49

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21077

1

T2

26

T3

12

T5

115

auto[1]

6066

1

T1

1

T4

8

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T187	11		T322	9		-	-
values[0]	53	1			T214	24		T323	1		T284	12
values[1]	814	1			T119	25		T23	20		T27	26
values[2]	3080	1			T1	1		T4	8		T8	17
values[3]	587	1			T5	2		T38	5		T176	10
values[4]	718	1			T6	13		T37	52		T215	14
values[5]	887	1			T7	11		T9	1		T37	6
values[6]	726	1			T5	1		T43	19		T119	6
values[7]	501	1			T2	26		T46	3		T38	9
values[8]	598	1			T43	8		T46	23		T12	5
values[9]	1109	1			T9	1		T35	49		T118	1
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1047	1			T23	11		T27	26		T121	1
values[1]	3041	1			T1	1		T4	8		T8	17
values[2]	597	1			T5	2		T37	52		T38	5
values[3]	673	1			T6	13		T128	18		T57	4
values[4]	930	1			T7	11		T9	1		T37	6
values[5]	648	1			T46	3		T119	25		T30	25
values[6]	548	1			T5	1		T43	8		T46	23
values[7]	496	1			T2	26		T141	1		T12	5
values[8]	844	1			T9	1		T35	49		T118	1
values[9]	223	1			T233	11		T246	1		T243	12
minimum	18096	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T23	7		T27	12		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T121	1		T162	1		T95	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T1	1		T4	1		T8	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T46	17		T13	16		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T37	15		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	12		T38	2		T94	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T57	2		T31	6		T249	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	8		T128	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T9	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T43	4		T119	6		T22	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T119	13		T161	13		T58	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	3		T30	12		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T43	8		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	13		T38	5		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T141	1		T12	3		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T2	13		T23	7		T57	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	1		T22	13		T24	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T35	24		T118	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T233	11		T243	7		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T246	1		T292	5		T324	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17919	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T119	13		T325	1		T326	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T23	4		T27	14		T122	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T162	16		T31	8		T50	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T4	7		T127	25		T23	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	17		T13	12		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T37	8		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	17		T38	3		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T57	2		T31	8		T294	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	5		T128	17		T215	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	10		T37	5		T41	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T43	15		T27	2		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T119	12		T58	8		T16	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	13		T214	9		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T206	5		T162	6		T139	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T46	10		T38	4		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T14	3		T58	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	13		T23	13		T57	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T57	2		T143	13		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	25		T192	9		T206	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T243	5		T247	15		T286	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T292	2		T309	18		T232	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T119	12		T326	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T187	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T322	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T214	14		T327	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T323	1		T284	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T23	12		T27	12		T142	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T119	13		T121	1		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1697	1			T1	1		T4	1		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T46	17		T13	16		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T176	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T38	2		T206	1		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	15		T139	1		T124	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	8		T37	12		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T9	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T22	17		T128	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T184	1		T95	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	4		T119	6		T27	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T162	7		T161	13		T58	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	13		T46	3		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	8		T12	3		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T46	13		T23	7		T57	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T9	1		T141	1		T22	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T35	24		T118	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T187	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T214	10		T327	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T284	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T23	8		T27	14		T142	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T119	12		T50	14		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T4	7		T127	25		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	17		T13	12		T162	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	1		T176	9		T89	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	3		T206	9		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	8		T139	2		T236	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	5		T37	17		T215	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	10		T37	5		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T128	17		T227	11		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	4		T242	7		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T43	15		T27	2		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T162	6		T58	8		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	13		T38	4		T123	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	2		T206	5		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	10		T23	13		T57	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T57	2		T123	11		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T35	25		T192	9		T206	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T23	5		T27	15		T122	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T121	1		T162	17		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T1	1		T4	8		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T46	18		T13	16		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	2		T37	9		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T37	18		T38	5		T94	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T57	3		T31	9		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	6		T128	18		T215	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	11		T9	1		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T43	16		T119	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T119	13		T161	1		T58	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T46	1		T30	14		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T43	1		T206	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	11		T38	5		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T141	1		T12	5		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T2	14		T23	14		T57	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T22	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T35	27		T118	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T233	1		T243	6		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T246	1		T292	3		T324	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18063	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T119	13		T325	1		T326	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T23	6		T27	11		T142	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T95	1		T31	10		T129	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T8	15		T42	33		T44	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	16		T13	12		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T37	14		T143	3		T250	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	11		T152	3		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T57	1		T31	5		T249	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	7		T58	2		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T95	9		T41	1		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	3		T119	5		T22	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	12		T161	12		T58	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	2		T30	11		T214	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T43	7		T162	6		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T46	12		T38	4		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	3		T58	4		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T2	12		T23	6		T57	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T22	12		T24	6		T57	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T35	22		T192	11		T88	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T233	10		T243	6		T247	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T292	4		T309	9		T312	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T327	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T119	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T187	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T322	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T214	11		T327	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T323	1		T284	12		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T23	10		T27	15		T142	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T119	13		T121	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T1	1		T4	8		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T46	18		T13	16		T162	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	2		T176	10		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	5		T206	10		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	9		T139	3		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	6		T37	18		T215	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	11		T9	1		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T22	1		T128	18		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T184	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T43	16		T119	1		T27	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T162	7		T161	1		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	14		T46	1		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	1		T12	5		T206	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T46	11		T23	14		T57	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T141	1		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T35	27		T118	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T322	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T214	13		T327	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T23	10		T27	11		T142	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T119	12		T129	4		T133	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T8	15		T42	33		T44	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	16		T13	12		T95	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T143	3		T250	8		T221	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T18	1		T152	3		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	14		T124	7		T230	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	7		T37	11		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T119	12		T57	1		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T22	16		T227	8		T58	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T95	9		T16	3		T228	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	3		T119	5		T27	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T162	6		T161	12		T58	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T2	12		T46	2		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T43	7		T14	3		T58	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T46	12		T23	6		T57	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T22	12		T24	6		T57	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T35	22		T192	11		T88	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15